EXPERIMENT No. 02(i) OBJECTIVE Write a VHDL program to implement a full adder using basic logic gates. PRACTICAL SIGNIFICANCE HDL (Hardware Description Language) based design has established itself as the modern approach to design of digital systems, with VHDL (VHSIC Hardware Description Language) and Verilog HDL being the two dominant HDLs.

RESOURCE REQUIRED Computer System, Software : Xilinx ise 9.2i, Book : Digital Logic and Computer Design by M. Morris Mano

PRINCIPAL OF EXPERIMENT Full Adder is a combinational circuit that performs the arithmetic sum of three bits (two significant bits and previous carry). It consists of three inputs and two outputs, The first two inputs are x and y represents significant bits & the third input represents the carry form the previous position.

If x and y are the significant input bits & z is previous carry, then sum bit (S) is the X-OR of x, y and z and the carry bit (C) will be the OR of AND of x & y and AND of z & XOR of x & y. From this it is clear that a full adder circuit can be easily constructed using two X-OR gate , two AND gate and one OR gate.

S=(xy) z S=xyz+xyz+xyz+xyz C=z(xy)+xy C=xyz+xyz+xy

Full adder can also be implemented using two half adders and one OR gate . The full adder is usually a component in a cascade of adders, which add 8, 16, etc, binary numbers.

TRUTH TABLE OF FULL ADDER

inputsoutputs

Xyzcs

00000

00101

01001

01110

10001

10110

11010

11111

CIRCUIT DIAGRAM

a) Full Adder block diagram --

b) Full Adder circuit diagram

c) for carry

d)for sum

VHDL CODE FOR FULL ADDER

library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating---- any Xilinx primitives in this code.--library UNISIM;--use UNISIM.VComponents.all;

entity fulll_adder is Port ( x : in STD_LOGIC; y : in STD_LOGIC; z : in STD_LOGIC; s : out STD_LOGIC; c : out STD_LOGIC);end fulll_adder;

architecture Behavioral of fulll_adder is

begins