Fujitsu Semiconductor...s 40 nm S i-g a te CMO S ＋ 1.1V± 0.1V C S 201 erie 65 nm S a te CMO S pport s a wide r a nge from ＋ 0.9V ～＋ 1. 3 V C 101 erie 90 nm S a te CMO S Over

i

DesignExpress, Cedar, PLACATE, Signaly, FCRAM and CoolAdjust are registered trademarks of Fujitsu Semiconductor Co.,Ltd.

FAITH is the registered trademark of Fujitsu Kyushu Network Technologies Co., Ltd.

AMBA, ARM, ARM1176JZF-S, ARM7TDMI-S, ARM926EJ-S, ARM946E-S, ETM11, Cortex-M3, Cortex-R4F and Cortex-A9 are

trademarks or registered trademarks of ARM Limited.

CompactFlash is registerd trademark of SanDisk Corporation.

Memory Stick is registered trademark of Sony Co., Ltd.

HDMI,HDMI Logo and High-Definition Multimedia Interface are trademarks or registerd trademarks of HDMI Licensing LLC.

Other company names and product names are trademarks or registered trademarks of their respective owners.

Shanghai

Fujitsu Semiconductor (Shanghai) Co., Ltd

30F, Kerry Parkside, 1155 Fang Dian Road,

Pudong District, Shanghai 201204

Tel: (86 21) 6146 3688

Fax: (86 21) 6146 3660, 6146 3680

http://www.fujitsu.com/cn/fss

Chengdu

Fujitsu Semiconductor Design (Chengdu) Co., Ltd

B-5 No. 3 GaopengDaDao, Hi-Tech Zone

Chengdu, Sichuan (Postcode: 610041)

Tel: (86 28) 8515 0023

Fax: (86 28) 8515 0523

Hong Kong

Fujitsu Semiconductor Pacific Asia Ltd.

10/F, Wolrd Commerce Centre 11 Canton Road

Tsim Sha Tsui, Kowloon, Hong Kong

Tel: (852) 2736 3232

Fax: (852) 2314 4207

Singapore & Oceania

Fujitsu Semiconductor Asia Pte Ltd

151 Lorong Chuan

New Tech Park #05-08

Singapore 556741

Tel: 65-6281-0770

Fax: 65-6281-0220

India

Fujitsu Semiconductor Asia Pte Ltd

Unit No.3, Level 8, Innovator,

International Tech Park, Whitefield Road

Bangalore, India 560066

Tel: (91): 80-28419990

Fax: (91) 80-28416660

Xi’ an


Xi’ an Branch

Room B0903, Pioneering Square,

No. 48 Ke Ji Road, High-Tech Zone,

Xi’ an, Shanxi Province, 710075

Tel: (86 29) 8799 8600

Fax: (86 29) 8799 8465

Taiwan


Taiwan Branch

10FI., No.451, Chang-Chun Rd.,

Taipei 105, Taiwan

Tel: (886 2) 2719 2011

Fax: (886 2) 2545 3690

Beijing

Fujitsu Semiconductor (Shanghai) Co., Ltd.

Beijing Branch

Room 1501B, 15th Floor, Tower A,

Ocean International Center,

No. 5 Dong Si Huan Zhong Rd.,

Chaoyang District Beijing 100025, China

Tel: (86 10) 5969 1600

Fax: (86 10) 5969 1611

Shenzhen


Shenzhen Branch

Rm 4509, Di Wang Commercial Centre,

5002 Shen Nan Dong Rd,

Shenzhen (Postcode: 519008)

Tel: (86 755) 2583 0028

Fax: (86 755) 8246 1510

FS

S-A

SIC

-201

111E

N The contents of this document are subject to change without notice. Customers are advised to consult with sales representatives before ordering.

The information, such as descriptions of function and application circuit examples, in this document are presented soley for the purpose of reference to show examples

of operations and uses of Fujitsu Semiconductor device; When you develop equipment incorporating the device based on such information, you must assume any

responsibility arising out of such use of the information. Fujitsu Semiconductor assumes no liability for any damages whatsoever arising out of the use of the information.

Any information in this document, including descriptions of function and schematic diagrams, shall not be construed as license of the use or exercise of any intellectual

property rught, such as patent right or copyright, or ay other right of Fujitsu Semiconductor assumes no liability for any infringement of the intellectual property rights or

other rights of third parties which would result from the use of information contained herein.

The products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary industrial

use, general office use, personal use and household use, but are not designed, developed and manufactured as contemplated for use accompanying fatal risks or

dangers that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage

or other loss (i.e. nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch

control in weapon syste,), or for use requiring extremely high reliability (i.e. submersible repeater and artiificial satellite). Please note that Fujitsu Semiconductor will not

liable against you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products.

Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design

measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current level and other abnormal operating conditions.

Exportation/release of any products described in this document may require necessary procedure in accordance with the regulations of the Foreign Exchange and

Foreign Trade Control Law.

The company names and brand names herein are the trademarks or registered trademarks of their respective owners.

i

Leading Advanced SoCFujitsu Semiconductor

2011.102011.10

2

Architecture Design・Verification

Automotive Electrical Devices

MobileCommunicationDevices

NEq

DigitalAV devices

ReliabilityTechnology

DesignTechnology

Technology

IP MacroDesignServices

P

Products･Technology that supports ASIC/SoC

System SolutionsCodesign L

Achieving “One Pass Success”From LSI to System

3

Due to rapid market change and diversification of

user needs, it is necessary to develop market products

in shorter development period.

As product development becomes increasingly

complex and lengthy, not only LSI, reducing iterations of

whole system becomes an extremely important issue

during development.

Fujitsu Semiconductor provides the “One Pass

Success” technology cultivated around 30 years of

ASIC development. Furthermore, we provide system

solutions integrated with upstream design, verifica-

tion, co-design and low power consumpiton design,

which would contribute to product development. In

addition, we organize business activities such as

restricting Co2 emissions, and pay continual efforts

towards global environment protection. By coping

with various customer needs, we aim to create a pros-

perious future together with you.

IndustryAmusementEquipment

ＯＡNetworkEquipment

Package

cro

ＡＲＭPlatform

Low Power Design

C O N T E N T S

5

6

10

20

24

34

38

48

Technology Roadmap

ASIC Lineup

IP Macro

Package

Design Methodology

Reliability

Design Center

Tech

nolo

gy R

oad

map

1

Technology Roadmap

Technology Roadmap■ Technology Roadmap

Fujitsu Semiconductor offers a wide range of technologies and products from 0.18μm to 40nm and beyond to meet customer needs.

For 40nm and 28nm, the wafer manufacture was committed to TSMC’s fabs, which will bring together Fujitsu’s IC desgin technolo-

gies, leading edge imaging and communication intellectual property (IP), and high-quality technical support to customers with

TSMC’s foundry-leading process technology and capability.

Year of Production

Gat

e L

eng

th (

nm

)

10

100

1000

1998 2000 2002 2004 2006 2008 2012 20142010

0.18 m 0.13 m 90nm 65nm 40nm 28nm 20nm

500

200

20

50

AS

IC L

ineup

2

ASIC lineup

ASIC Product Lineup■ Overview of ASIC Products

●Standard Cell

●Embedded Array

●Gate Array

■ CS302 SeriesThe CS302 series is a line of 40nm standard cells that satisfy demands for lower power-consumption, higher speed and higher inte-

gration.

These cells are able to implement a mixture of core transistors with three different threshold voltages according to different applica-

tions. Their “High Integration・ Low Power Consumption・High Speed” features achieve optimum conditions for LSI development.

The integration level in this series is twice the CS201 series.

＊：Available package and memory vary with the circuit configuration, please contact our representative.

Series Name Technology Gate Supply voltage（Standard）CS302 Series 40 nm Si-gate CMOS ──── ＋ 1.1V± 0.1V CS201 Series 65 nm Si-gate CMOS ──── Supports a wide range from

＋ 0.9V ～＋ 1.3VCS101 Series 90 nm Si-gate CMOS Over 91 million gates Supports a wide range from

＋ 0.9V ～＋ 1.3VCS91 Series 0.13 µm Si-gate CMOS Over 48 million gates ＋ 1.2V± 0.1VCS86 Series 0.18 µm Si-gate CMOS Over 40 million gates ＋ 1.8V± 0.15V

Series Name Technology Gate Supply voltage (Standard)

CE88 Series 0.18 µm Si-gate CMOS 13 million gates ＋ 1.8V± 0.15V

Series Name Technology Gate Supply voltage (Standard)

CG88 Series 0.18 µm Si-gate CMOS 13 million gates ＋ 1.8V± 0.15V

Technology 40 nm Si-gate CMOS

Supply voltage Internal：+1.1V±0.1V　External：1.8V, 2.5V, 3.3VRandom logiccells librarylineup

For high integration For high speedCS302SL（Low Leakage Transistor） CS302ML（Low Leakage Transistor）CS302SN（Standard Transistor） CS302MN（Standard Transistor）CS302SZ（High Speed Transistor） CS302MZ（High Speed Transistor）

Package lineup ＊ FBGA、FC-BGA、PBGA、TEBGA

Memory capacity（bit）＊

Name Type Capacity Range

Clock-synchronized single-port RAM（1RW）

Clock-synchronized dual port RAM（2RW）Clock-synchronized ROMClock-synchronized register file（1R/1W）Clock-synchronized register file（2R/2W）Clock-synchronized register file （1RW）

－Large capacity－－－－－

1k ～ 1152k64k ～ 9M32 ～ 72k64 ～ 256k16 ～ 72k16 ～ 18k32 ～ 36k

AS

IC L

ineup

3

■ CS201 SeriesThe CS201 series is a line of 65nm standard cells achieving low power consumption, high speed and high integration.

These cells are able to implement a mixture of core transistors with three different threshold voltages according to different applications.Their “High Integration・ Low Power Consumption・High Speed” features achieve optimum conditions for LSI development. The integration level in this series is twice the CS101 series.

＊ 1：Available package and memory vary with the circuit configuration, please contact our representative.＊ 2：Please contact our representative for the memory capacity range.＊ 3：Technology from MoSys Corporation is used.

■ CS101 SeriesThe CS101 series is a line of 90nm standard cells achieving lower consumption power and higher speed. These cells can consoli-date core transistors with three different threshold voltages according to different applications. Random logic cell library of transistor withmultiple cell height and threshold voltages can be used in either block unit or cell unit. The integration level in this series is twice the CS91 series and it provides a maximum of 91 million gates. 。



Supply voltage Internal：Supports a wide range from +0.9V ～ +1.3V　External：1.8V, 2.5V, 3.3VRandom logiccells librarylineup

For high integration For high speedCS202SNC（Low Leakage Transistor） CS202MNC（Low Leakage Transistor）CS202SN（Standard Transistor） CS202MN（Standard Transistor）CS202SZ（High Speed Transistor） CS202MZ（High Speed Transistor）

Package lineup ＊ 1 FBGA、FC-BGA、PBGA、TEBGA

Memory capacity（bit）＊ 1



Clock-synchronized dual port RAM（2RW）

Clock-synchronized 2-port RAM（1R/1W）Clock-synchronized ROMClock-synchronized register file（1R/1W）Clock-synchronized register file（2R/2W）

－－Large capacityHigh speed－High speed－－－－

＊ 2

16 ～ 640k64k ～ 9M128 ～ 144k32 ～ 72k64 ～ 72k64 ～ 72k256 ～ 1M16 ～ 18k16 ～ 18k


Supply voltage Internal：Supports a wide range from +0.9V ～ +1.3V　External：1.8V, 2.5V, 3.3VRandom logiccells librarylineup

For high integration For high integration For super high integrationCS104SL（Low Leakage Transistor） CS101SL（Low Leakage Transistor） CS104DL（Low Leakage Transistor）CS104SN（Standard Transistor） CS101SN（Standard Transistor） CS104DN（Standard Transistor）CS104SZ（High Speed Transistor） CS101SZ（High Speed Transistor） CS104DZ（High Speed Transistor）For high speed For high speedCS104ML（Low Leakage Transistor） CS101ML（Low Leakage Transistor）CS104MN（Standard Transistor） CS101MN（Standard Transistor）CS104MZ（High Speed Transistor） CS101MZ（High Speed Transistor）

Package lineup ＊ FBGA、FC-BGA、PBGA、TEBGA





Clock-synchronizes 2-port RAM（1R/1W）Clock-synchronized ROMClock-synchronized register file（1R/1W）Clock-synchronized register file（2R/2W）

High integrationSuper high integrationSuper high integration and large capacityHigh speedHigh integrationSuper high integrationHigh integration－High integrationHigh integration

16 ～ 576k32 ～ 288k64k ～ 9M64 ～ 144k16 ～ 144k64 ～ 288k64 ～ 72k256 ～ 4M8 ～ 18k8 ～ 18k

AS

IC L

ineup

4

■ CS91 SeriesThe CS91 series is a line of 0.13µm standard cells for low power-consumption, high speed and high integration.

These cells can implement a mixture of core transistors with three different threshold voltages according to different applications. Random

logic cell library of transistor with multiple cell height and threshold voltages can be used in either block unit or cell unit. Their features

achieve optimum conditions for LSI development. This series has a high integration level of up to 48 million gates.


■ CS86 SeriesThe CS86 series is a line of 0.18µm standard cells based on higher integration implemented by introducing wiring pitch reduction

technology and on I/O pad placement technology to the conventional CS81 series.

These cells can implement a mixture of core transistors with three different threshold voltages according to different applications. Randomlogic cell library of transistor with multiple cell height and threshold voltages can be used in either block unit or cell unit. Their “HighIntegration・ Low Power Consumption・High Speed” features achieve optimum conditions for LSI development.


Technology 0.13 µm Si-gate CMOS

Supply voltage Internal：+1.2V±0.1V　External：2.5V, 3.3V

Random logiccells librarylineup

For high integrationCS92SL（Low Leakage Transistor）CS92SN（Standard Transistor）CS92SZ（High Speed Transistor）CS91SL（Low Leakage Transistor）CS91SN（Standard Transistor）CS91SZ（High Speed Transistor）

For high speedCS91HN（Standard Transistor）CS91HZ（High Speed Transistor）

Package lineup ＊ FC-BGA、FBGA、QFP





Clock-synchronized dual port RAM（1RW/1R）Clock-synchronized ROMClock-synchronized register file（1R/1W）Clock-synchronized register file（2R/2W）

High integrationSuper high integrationHigh speedSuper high integration and large capacityHigh speedSuper high integrationHigh integration－High integrationHigh integration

32 ～ 288k32 ～ 288k256 ～ 144k16k ～ 4M32 ～ 144k32 ～ 288k64 ～ 144k256 ～ 1M8 ～ 18k8 ～ 18k


Supply voltage Internal：+1.8V±0.15V　External：2.5V, 3.3V


CS86ML（Low Leakage Transistor）CS86MN（Standard Transistor）CS86MZ（High Speed Transistor）

Package lineup ＊ QFP、LQFP、HQFP、PBGA、FBGA、FLGA



Clock-synchronized single-portRAM（1RW）

Clock-synchronized dual port RAM（1RW/1R）Clock-synchronized ROMClock-synchronized register file（2R/1W）Clock-synchronized register file（2R/2W）Delay-line memory

High integration/Partial light typeLarge capacityHigh speedSuper high integration/ Partial light typeSuper high integration and large capacityHigh integration－High integrationHigh integration－

16 ～ 72k24k ～ 1152k256 ～ 144k256 ～ 144k16k ～ 1152k16 ～ 72k256 ～ 1M4 ～ 46084 ～ 4608256 ～ 32k

AS

IC L

ineup

5

■ CE88 Series The CE88 series is a line of 0.18µm macro embedded array with regulators and developed by 3.3V single power supply.

This series incorporates up to 13 million gates and it can be developed with environment of CS86 series.


■ CG88 SeriesThe CG88 series is a line of 0.18µm gate array embedded with regulators with 3.3V single power supply.

This series embeds PLL to the frame with large memory capacity. It also incorporates metal program for maintaining high flexibility.

It is optimum for reducing cost of LSI development and developing main LSI companion products.


＊ 1：Other frames are to be considered, please contact our representative.＊ 2：With thermal balls（The number of pins include value of thermal balls）


Supply voltage Internal：+1.8V±0.15V　or　+3.3V±0.30V（With built-in regulator）　External：3.3V


CE88

Package lineup QFP、FBGA、PBGA



Clock synchronous single-port RAM（1RW）

Clock synchronous dual port RAM（1RW/1R）Clock synchronous ROMClock synchronous register file（2R/2W）

High integration/Partial light typeHigh speedSuper high integration/Partial light typeSuper high integration and large capacityHigh integration－－

32 ～ 72k256 ～ 144k256 ～ 144k16k ～ 1152k32 ～ 72k256 ～ 1M8 ～ 4608


Supply voltage Internal：+1.8V±0.15V　or　+3.3V±0.30V（With built-in regulator）　External：3.3V


CG88

Package lineup ＊ QFP、FBGA、PBGA



Clock synchronous single-port RAM（1RW）

Clock synchronous dual port RAM（1RW/1R）

Embedded partial light typeEmbedded gate array typeEmbedded partial light typeEmbedded gate array type

64k256 ～ 102416k256 ～ 512

PackageFrame name / Total BC no.＊1

PackageFrame name / Total BC no.＊1

CG88424　 CG88974　 CG88135　 CG88424　 CG88974　 CG88135　

420k　 970k　 1300k　 420k　 970k　 1300k　

LQFP

48 ○

FBGA

112 ○64 ○ 144 ○ ○ ○80 ○ ○ 192 ○ ○ ○

100 ○ ○ 240 ○ ○120 ○ ○ 272 ○ ○144 ○ ○ ○ PBGA 320 ＊ 2 ○176 ○ ○ ○ 416 ＊ 2 ○216 ○ ○256 ○

IP M

acro

6

IP Macros

IP Macros■ IP Macro・Roadmap

With provision of high-quality macros which are tested by IP macro dedicated testing system, Fujitsu accelerates the development

of the leading-edge SoCs. We aim to satisfy the extensive demands of different customers by developing various IPs available for

CPU, media processors, image processors and communication I/F devices, etc., and also by cooperating with external IP vendors

to gather different IPs. In the future, we will continue to proceed in circuit technology and provide advanced IP for customers.

■ IP macro verification

Fujitsu Semiconductor provides IP marcos verified by IPV (IP Verification Flow) which enables customers to enjoy first pass suc-

cess of advanced SoC development, regardless internal or external macros. In addition, Fujitsu Semiconductor has system of inde-

pendent IP verification team to ensure high-quality IP macros.

CY20010CY2008 CY2009 CY2011 CY2012 CY2013 CY2014

PC peripheral IF

Storage IF

Audio/Video IF

Memory IF

Display intra IF

PC peripheral IF

Storage IF

Audio/Video IF

Memory IF

Display intra IF

USB2.0

DDR3DDR2

LPDDR

FPD-link85MHz(65nm)

FPD-link135MHz(40nm)

iDP3.24Gbps(40nm)

iDP next(40nm or 28nm)FPD-link

135MHz(65nm)

LPDDR2-S4 LPDDR2-S2 LPDDR3

DDR4

HDMI1.3 HDMI1.4 post HDMI

SATA1.5/3Gb SATA

6GbSATA AHCISATA HostSATA Device

USB3.065nm USB3.0

40nm/28nmPCleGen3

PCle5Gb/lane

PCle2.5Gb/laneEndpoint Root

Complex Dual Mode

Developed

Under development

Under planning

Cedar verificationBus Function model testProtocol random verification

Asynchronous verification tool

Function

60%BUS interface25%

Clock Domain

15%15%

Fujitsu developed original method that verifies asynchronous metastable in RTL level Patent Pending)

Failure Analysis in Development of IP Macro ExampleFailure Analysis in Development of IP Macro Example

Internal DesignTeam

External IP Provider

IP design and verification

IP verification palnningCollection and reflection of failure case studies

IP development unit

IP design team IP qualification team

Verification executing teamby third partiesRandom verificaition

Asynchronous verification

IP Macro Verification FlowIP Macro Verification Flow

IP M

acro

7

■ ARMTM Core・Macro●ARM core・RoadmapFujistu possesses licenses for ARM7TDMI-STM, ARM946E-

STM, ARM026EJ-STM, ARM1176JZF-STM, Cortex-M3TM,

Cortex-R4FTM and Cortex-A9TM. ASIC can be applied exten-

sively from microcontroller to embedded devices and applica-

tion equipment. All ARM core are synthesizable and are

suitable for a wide variety of technologies.

●ARM platformFujitsu Semiconductor utilizes FASP (Fujitsu ARM based

SoC Platform) to reduce production cost and risks of ARM

core SoC development.

○Reference design for ARM cores based ASIC

・Verified reference design significantly reduce design cost andverification items.

・Reference designs are optimized for each ARM core.・Outstanding extensibility and customizability・Test bench, simulation environment, sample boot-code・Supports various process technologies

○Prototyping environment for ASIC

・Our prototyping environment combined with original ARMevaluation chip and FPGA

・Enables verification of hardware system operation, perfor-mance evaluation and software development in shorterperiod.

・Provides ARM11 based (embedded with ARM926 andARM946 too) ASIC prototyping boards

・Prototyping kit (FPGA reference design, simulation model forevaluation chip, etc) for each prototyping board allows shorterlaunch of prototyping environment.

ARM Core FASP RoadmapARM Core FASP Roadmap

2010 2011 2012 2013 2014

Application

ARM Core Lineup

FASP Roadmap

Real Time

Microcontroller

ARM1176ARM1176

ARM926ARM926

ARM946ARM946

ARM7ARM7M3M3

A9A9

ARM1176JZF-S Cortex-A9

Cortex-R4F

Cortex-M3

Cortex-A5

Cortex-A15

Cortex-R5

Cortex-M4

Cortex-M0

ARM926EJ-S

ARM946E-S

ARM7TDMI-S

A5A5 A15A15Under operationUnder operation

Under developmentUnder development

Under planningUnder planning

R5R5

M4M4M0M0

R4FR4F

NEW!NEW!

FASP Reference Design Block DiagramFASP Reference Design Block DiagramWhen When CPU is ARM1176JZF-SCPU is ARM1176JZF-S

1176 Reference DesignARM1176 Core Block

ARM1176JZF-SInterrupt

L2Cache(option)

ETM11TMCSSingle

P I RW DMA

DMAC(max8ch)

AMBA 3 interconnect (32-bit)

AMBA 3 interconnect (64-bit)

AMBA 3 interconnect (32-bit) SRAM64kB MEMCS DMC

XDMACReg.

APB

GPIO 32ch

UART3ch MRBC CRG

Clock and Reset

MEMCSReg.

DMCReg.

Trace port

JTAG

SDR SDRAM

Flash, SRAM

VIC Ext. IRC WDT Timer

ARM11 Prototyping EnvironmentARM11 Prototyping Environment

ARM11,ARM9 evaluation chip MB8AA0350 MB8AA0350+FPGA embedded board

ARM, ARM7TDMI-S, ARM926EJ-S, ARM946E-S, ARM1176JZF-S, Cortex-M3, Cortex-R4F, Cortex-A9 and AMBA are the trademarks of ARM Limited in the EU and other countries.

IP M

acro

8

■ Interface・Macro

Fujitsu supports customers’ advanced SoC development with various interface macros.

●USB3.0 InterfaceFujitsu Semiconductor provides device macros and PHY

macros of standard USB 3.0 specification in November 2008.

This innovative product achieves low power consumption with

enhanced efficiency and power management.

○USB3.0 Device Link macro

・Super Speed Link Layer and Protocol Layer embedded・Super Speed protocol process on hardware・FIFO for EndPoint embedded･DMA interface for data transfer is separated from CPU BUS

○USB3.0 PHY macro

・Supports Super Speed (5Gbps)・SSC (Spread Spectrum Clocking) generator embedded・CDR (Clock Data Recovery) function compliant to SSC mod-

ulation embedded・Receiver detection equipped・LFPS transmitter and receiver function embedded・8810B encoder/decoder embedded

・Supports Loopback BERT function for compliance test・LINK macro interface is compliant with PIPE specification

●HDMI® InterfaceHDMI (High-Definition Multimedia Interface) connects with AV

equipment such as camcorder/digital camera/HDD recorder,

etc. It also inputs/outputs digital video/ audio signals.

The latest HDMI-V1.4 supports 3D images and 4K2K panels.

We provide controller macros and PHY macros which comply

with this HDMI specification.

○HDMI macro

・Transmission of uncompressed video・Transmission of multi-channel audio signals・Content protection with HDCP・Guarantees connectivity between equipment by compliance

test・Supports Deep Color・Supports 3D images and 4K2K panels・Functionally equivalent to ASSP products by Silicon-Image ・Mutual recognition between connected equipment・Equipment control function by CEC (Consumer Electronic

Control)・Elastic buffer embedded・Compliance test of pattern generator embedded

USB3.0 Evaluation board & 5.0Gbps Eye DiagramUSB3.0 Evaluation board & 5.0Gbps Eye Diagram

SATA3Gbps

SATASATAPHYPHY

USB2.0USB2.0PHYPHY

FPGAFPGA

SATAPHY

USB2.0PHY

FPGA

200psSuperSpeed USB PHY

- test chip- 65nm CMOS- PBGA package, wire bonding

USB3.05Gbps

Generator&

Analyzer SSD

Purposes of HDMIPurposes of HDMI

HDMIHDMI Evaluation Board Evaluation Board

CamcorderCamcorder MonitorMonitor

DigitalFrontend

Image/AudioProcess Unit

SensorImage SensorMicrophone M

emor

y

HDMICable

Imgae/AudioEngine

Panel/Speaker

HD

MI

-Tx

HD

MI

-Rx

IP M

acro

9

●DDR InterfaceFujitsu Semiconductor provides DDR interface macros from

low-mid range transfer bandwidth to higher transfer band-

width, with various technology nodes. We also support cus-

tomers’ SoC development with design support such as initial

timing budgeting and guidelines.

○DDR Interface・Macro

・Supports high speed operation/ various calibration (high-speed macros)

・supports low latency/low power consumption (low-mid speedmacros)

・DFI compliant (all macros)

○DDR Interface Design Support

・Power-supply design in LSI to reduce SSO/SSI Noise・Early detection for critical issues by initial Timing Budget・Hybrid timing analysis for STA (in LSI), Spice (including PCB)

(provides guideline for timing design)

●PCI Express InterfaceDue to the expansion of CPU processing capacity and data

transfer needs, the existing BUS has difficulty to achieve good

system performance. The high-speed PCI Express Interface,

which enables data transfer with few hundred mega bytes,

can solve the problem. PCI Express macros passed the com-

pliance test of PCI Express standard by PCI-SIG, and verified

connectivity and reliability with many PCI Express interfaces.

○PCI Express LINK Macro

・Compliant with PCI Express Base Specification rev.2.0・Selectable Root/Endpoint(Dual Mode)・Supports lane number of x1/ x4・Supports multifunction(8 at maximum)・Supports a maximum of 8 channels of VC on board・AHB BUS Interface・PHY Macro Interface compliant with PIPE Specification

○PCI Express PHY Macro

・Actual transfer bandwidth is over 800MB/s (with x4 lanes)・Guarantees high-speed signal-transmission by De-emphasis

function・Interface of LINK macro complies with standard PIPE

DDR Interface Timing Design (Example)DDR Interface Timing Design (Example)

DDR Interface Development RoadmapDDR Interface Development Roadmap

Core Logic

DDR3-SDRAMPCB

Package

System LSI

533MHz

DDR3-1.066Gbps/pin

32bit BUS

1.066Gbps/pin32bit BUS

MemoryController

MemoryInterface

Macro

I/OCell

1.5VSSTL15

PLL1.066GHz

DivDiv

266MHz

533MHz

DLL

Designed by customer Released by Fujitsu DRAM VendorDesigned bycustomer

533Mbps/pin64bit BUS

28nm28nm

40nm40nm

65nm65nm

LPDDR2-400 800Mbps

DDR3-600M 1.6Gbps

CY2010/1H CY2010/2H CY2011/1H CY2011/2H CY2012/1H CY2012/2H

DDR3-600M 1.6Gbps

LPDDR-250 400Mbps Now AvailableDDR2-250 800Mbps Now AvailableLPDDR2-250 667Mbps Now Available

LPDDR-250 400Mbps Now AvailableDDR2-250 800Mbps Now AvailableDDR3-600M 1.33Gbps Now Available

User CoreInterface

PIPE

PIPE: PHY Interface for Express Architecture

Logical Sub-block

Electrical Sub-block

Physical layer

Macro configuration byFujitsu Semiconductor

Data link layer

Transaction layer

PHYmacro

LINK macro

PCI Express Macro ConfigurationPCI Express Macro Configuration

PCI Express system evaluating boardPCI Express system evaluating board

IP M

acro

10

●Serial ATA InterfaceFujitsu Semiconductor provides AHCI macro complied with

Serial ATA R3.0 Specification and AHCI R1.3 Specification,

we also provide PHY macros of 3Gbps/1.5Gbps. AHCI macro

equips with NCQ (Native Command Queuing) to enhance the

performance of DMA transfer.

PHY macros satisfy Interoperability Test Revision 1.1 Specifi-

cation by SATA-IO and confirm high connectivity with different

drives.

○Serial ATA AHCI macro

・Compliant with Serial ATA R3.0 Specification・Compliant with AHCI Revision1.3 Specification・Supports NCQ (Native Command Queuing) hardware・Supports Partial to Slumber・AXI BUS interface

○Serial ATA PHY macro

・Auto Speed Negotiation (1.5Gbps/3Gbps)・Supports Dual mode (HOST mode/ DEVICE mode)・1channel on-board・Supports Asynchronous Signal Recovery・Supports SSC (Spread Spectrum Clocking)*

*: In case of applying SCC to transmission, it requires externalSSC to reference clock of the macro.

●USB2.0 InterfaceFujitsu Semiconductor provides host macros and device mac-

ros with PHY complying with standard USB2.0 specification.

Products are equipped with Hi-speed macro and Full-speed

macro respectively. Since the provision of USB1.1 macro in

1999, we have been occupied a large market share.

○USB2.0 Host macro

・Compliant with EHCI (Version1.0), OHCI (Version1.0a)・Hi-Speed/Full-Speed/Lo-Speed・AHB BUS interface

○USB2.0 Device macro

・Hi-Speed/Full-Speed・Supports Endpoint customization・Automatic response to control transfer

○USB2.0 HDCmacro (Under development)

・Switching of device function and simplified host function (orig-inal resister set)

・Transmission endpoint count is configurable (max.16 indevice/max.8 in host) and RAM size is selectable

○USB2.0PHY

・Supports Hi-Speed/Full-Speed/Lo-Speed PHY・Supports Hi-Speed/Full-Speed PHY・Supports Full-Speed/Lo-Speed I/O cell・Supports Full-Speed I/O cell

SATA System Evaluation BoardSATA System Evaluation Board

SATA PHY 3Gbps Eye DiagramSATA PHY 3Gbps Eye Diagram

USB2.0 PHY Evaluation BoardUSB2.0 PHY Evaluation Board

USB2.0 PHY 480Mbps Eye Diagram USB2.0 PHY 480Mbps Eye Diagram PBGA Package Filter Not In UsePBGA Package Filter Not In Use

IP M

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11

■ Analog・Macro

We offer various analog macros (ADC/DAC PLL DC-DC LDO)

for customers to develop advanced SoCs of various applica-

tions such as communication system, image processing and

sensor/ control LSI, etc

●Data･ConverterWe provides various data converter macros that achieve low

power consumption, small area and low cost.

●Full lineup●All macros are silicon-proven●Embedded on various ASIC with mass production results

○High Speed SAR Type ACDC

・Achieves the best-in class lowest power consumption (1/10 of others)

・Applicable for mobile communication in place of conven-tional pipeline type ADC

●Various Evaluation Boards○Evaluation board for communication

Recently, various blocks (such as PLL) are used in large-

scale SoC construction. Evaluation boards are available for

communication purposes and to facilitate selection of ADC

and PLL according to system demands.

・Embedded with pinelined ADC for communication・Embedded with 2 types of high precise PLL・Enable prototyping environment of customers

○Audio AFE Evaluation Boards

High precise Audio Codec can be evaluated in real acoustic

environment. Evaluation boards are set in accordance with

system specifications

・Embedded with world’s best quality Audio Codec macro・Various proven guidelines

●Power･ManagementWe provide various power management macros that enable

SoCs single power source.

●DC-DC converter (switching regulator)●LDO (Linear regulator)●All macros are silicon-proven

Various Data ConvertersVarious Data Converters

0.010 2 4 6 8 10 12 14 16 18 20 22 24

10

1

100

0.1

1000

10000

Resolution [bit]C

onve

rsio

n F

requ

ency

[MH

z]

Sound/Audio Codec

Sensor/ ADC

Network Graphics/ Pipeline ADCCurrent D AC

High Speed IF/FlashADCCurrent DAC

Network/High Speed SARADCCurrent DAC

Controller/SAR ADCLow Speed DAC

1.2V 10bit 50MS/s High Speed SAR ADC1.2V 10bit 50MS/s High Speed SAR ADC

Low power consumption Small area pipleine type ADC(For mobile communicatin)

High Speed SAR ADC

Various Evaluation BoardsVarious Evaluation Boards

Evaluation Board for Communication

Evaluation board for Audio AFE

IP M

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12

■ IP Macro・LineupFujitsu Semiconductor supports customers’ advanced SoC development with various interface macros.

●Overview of Function/ Interface macrosCategory Function

Process Technology0.13µm 90nm 65nm 40nm

CPU Core

ARM7TDMI-S Now Now Now NowARM946E-S/ARM926EJ-S Now Now Now NowARM1176JZF-S Now Now Now NowCortex-M3 Now Now Now NowCortex-R4F Now Now Now NowCortex-A9 Now Now Now Now

Image CoreJPEG Codec

Standard Version Now Now Now NowHigh Speed Version Now Now Now NowLow Power Version Now Now Now Now

JPEG Encoder High Speed Version Now Now Now NowNTSC/PAL Encoder Now Now Now Now

Security CoreDES/3DES Now Now Now NowAES Now Now Now Now

Interface Controller Core

I2CI2C Master/Target (100k/400kbps) Now Now Now NowI/OCell for I2C Now Now Now Now

PCIPCI V2.2 (32bit,33/66MHz) Contoroller Now Now Now Now

I/OCell for PCI Now Now Now Under planning

IrDA (SIR/MIR/FIR) Now Now Now NowE-IDE Host (66MHz) Now Now Now NowUART Now Now Now NowPCMCIA Host Now Now Now NowCardBus Host Now Now Now NowCompactFlash Host Now Now Now NowMemory Stick PRO V2.0 Host Now Now Now NowSD V1.1/ MMC V3.3 Host Now Now Now Now

SD V3.0/ MMC V4.41 Host - Underdevelopment

Under development

Underdevelopment

IP M

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13

●Overview of Special I/O/ High-speed Interface MacroCategory Function

Process Technology0.13µm 90nm 65nm 40nm

USB

USB2.0 (FS) Device Link Now Now Now Now

USB2.0 (FS/LS) I/O Cell Now Now Underdevelopment

Under planning

USB2.0 (HS/FS/LS) Host LINK - Now Now NowUSB2.0 (HS/FS) Device LINK Now Now Now NowUSB2.0 (HS/FS/LS are HOST only)Host/Device LINK Now Now Now Now

USB2.0 (HS/FS) Device PHY Now Now - -USB2.0 (HS/FS/LS) Host/Device PHY - Now Now Now

USB3.0 (SS/HS) Device LINK - Under development Now Now

USB3.0 (SS/HS) Device PHY - - Now Under development

USB3.0 (SS/HS) Host LINK - - Under planning

Under planning

Ethernet Gigabit Ethernet MAC Now Now Now Now

LVDSLVDS Transmitter I/O cell (~666Mbps) Now Now Now Now

LVDS Receiver I/O cell (~666Mbps) Now Now NowUnder

development

FPD Link

FPD Link Transmitter (1-clock/5-data) - Now~945Mbps

Now~1120Mbps

Underdevelopment

FPD Link Receiver (1-clock/5-data) - Now~595Mbps

Now~595Mbps

Under development~945Mbps

Underdevelopment

SubLVDSSubLVDS Transmitter I/O cell -

Now~650Mbps

Now~1Gbps Now

SubLVDS Receiver I/O cell - Now~650Mbps

Now~1Gbps Now

MIPI

MIPI D-PHY (SLVS) Transmitter I/O cell - Now~850Mbps

Now~1Gbps

Underdevelopment

MIPI D-PHY (SLVS) Receiver I/O cell -Now

~850MbpsNow

~1GbpsUnder

development

MIPI D-PHY Transmitter macro (to PPI) - Now~650Mbps

Underdevelopment~800Mpbs

Underdevelopment

MIPI D-PHY Receiver macro (to PPI) - Now~650Mbps

Under development~800Mpbs

Underdevelopment

HDMI

HDMI V1.2 Tx LINK - Now Now NowHDMI V1.3 Tx LINK - Now Now Now

HDMI V1.4 Tx LINK - Underdevelopment

Underdevelopment

Underdevelopment

HDMI Transmitter - Now~2.25Gbps

Now~1.485Gbps

Now ~1.485Gbps

PCI Express

PCIe Endpoint TRAN/LINK - Now Now NowPCIe RootComplex TRAN/LINK - Now Now Now

PCIe Dual Mode TRAN/LINK - Underdevelopment

Underdevelopment

Under development

PCI Express PHY (PMA+PCS) - Now2.5Gbps

Now2.5Gbps

Underdevelopment

Serial ATA

Serial ATA Gen2 AHCI TRAN/LINK - Underdevelopment

Under development

Under development

Serial ATA Gen2 Host TRAN/LINK - Now Now NowSerial ATA Gen2 Device TRAN/LINK - Now Now Now

Serial ATA PHY -Now

1.5G/3GbpsNow

1.5G/3GbpsNow

1.5G/3Gbps

XAUI XAUI Transmitter/ Receiver (3.125Gbps x 4) - Now Underdevelopment

Under planning

IP M

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14

DRAM Interface (PHY)

DDR1 250~400Mbps Now Now Now -DDR2 250~400Mbps - Now Now Now

DDR2 400~800Mbps - Now NowUnder

developmentDDR3 600~1066Mbps (1.066Gbps) - Now Now -

DDR3 600~1333Mbps (1.333Gbps) - - Underdevelopment

Underplanning

Mobile DDR ~400Mbps - Now Now Now

LPDDR2-S2 250~400Mbps - - Underplanning

Underdevelopment

LPDDR2-S4 400~800Mbps - - - Underdevelopment

Combined DDR2 / DDR3 - Now NowUnder

developmentCombined DDR2 / Mobile DDR - Now Now Now

Combined LPDDR2/Mobile DDR/DDR3/DDR2 - - - Underdevelopment

SSTL2 Now Now Now -

SSTL18 - Now Now Underdevelopment

SSTL15 - Now NowUnder

developmentLVCMOS18 (MDDR) - Now Now Now

HSUL12 - - Underplanning

Underdevelopment

IP M

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15

●Overview of Analog Macro

●＊： S.A.R = Successive Approximation Register

Category FunctionProcess Technology

0.13µm 90nm 65nm 40nm

ADC

6bit 100MS/s 3.3V Half Flash Now Now - -7bit 1GS/s 1.2V Flash - Now - -8bit 3MS/s 2.8V S.A.R＊ Now - - -8bit 50MS/s 3.3V Half Flash Now Now Now -8bit 110MS/s 1.2V dual channel pipeline - Now Now -10bit 1MS/s 3.3V S.A.R＊

（Input numbers of ch)Now

Now(17ch)

Now(12ch)

Now (16ch)

10bit 30MS/s 3.3V Half Flash Now Now - -10bit 40MS/s 1.2V dual channel pipeline Input MUX - Now Now -

10bit 50MS/s 1.2V S.A.R＊ - - Now Under development

10bit 80MS/s 1.2V dual channel pipeline - Now Now -10bit 165MS/s 3.3V single channel pipeline - Now - -12bit 500kS/s 3.3V S.A.R＊ - - Now -12bit 2MS/s 3.3V S.A.R＊ - - - -12bit 50MS/s 1.2V dual channel pipeline - Now Now -

16bit 10kS/s 3.3V Delta-Sigma - Under development - -

DAC

8bit 1MS/s 3.3V with x1 amp Now Now Now -

10bit 1MS/s 3.3V with x1 amp Now Now Now Under planning

10bit 45MS/s 3.3V Differential O/P - Now Now -10bit 54MS/s 3.3V Now Now Now Now

10bit 220MS/s 3.3V Now(110M)

Now Now Now (160M)

12bit 54MS/s 3.3V - Now Now -

16bit 48kS/s 3.3V - Now Under planning -

AFEAudio Codec (High-end) - Now Now -Touch Panel - Now Now -

RegulatorVin=3.3V, Output=1.0V, 1.2V, Iout=200mA LDO - Now Under

development -

Vin=3.3V, Output=1.2V, Iout=400mA DCDC - Now Underdevelopment -

Standard PLL

Fout:100~300MHz, Fin:2.5~200MHz Now Now Now -Fout:300~600MHz, Fin:2.5~200MHz Now Now Now -Fout:400~800MHz, Fin:10~100MHz Now Now Now NowFout:600~1200MHz, Fin:10~200MHz Now Now Now Now

Low Jitter PLLFout:300~400MHz, Fin:4~32MHz - Now Under

developmentUnder

developmentFout:300~600MHz, Fin:11~100MHz - Now Now NowFout:600~1200MHz, Fin:11~100MHz - Now - Now

High-speedPLL

Fout:800~1600MHz, Fin:16~200MHz - - Now -Fout:1000~1600MHz, Fin:16~200MHz - Now - -

Fout:1000~2000MHz, Fin:16~200MHz - - - Underdevelopment

High-multipliedPLL Fout:50~300MHz, Fin:>15kHz, Low Phase Jitter Now Now Now Under

planningFractional-N PLL Fout:400~500MHz, Fin:10~50MHz - - Now Under

planning

SSCG

Fout:300 ～ 600MHz, Fin:10 ～ 40MHz - Now - -Fout:400 ～ 800MHz, Fin:10 ～ 50MHz - - Now NowFout:600 ～ 1200MHz, Fin:10 ～ 50MHz - Now - -

Fout:800 ～ 1600MHz, Fin:10 ～ 50MHz - - Now Underdevelopment

Packag

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16

Package

Packages■ Package RoadmapFujitsu Semiconductor has been providing high-integrated packages in past 20 years.

Based on our knowledge and experiences, we will continue to provide total solutions which fit customers’ needs.

■ Package SystemWe provide a wide range of high-end packages supporting customers to meet market demands.

1984 1994 2004 2014

Miniaturization

DIP

FBGA

BCC

FD-FBGA

CSP

WL-CSP Bare Die

KGD Module

EWLP

Embedded Die

SOJ TSOP SSOP

CSOP SON

LQFP

SiP

Stacked-FBGA

PoP

3D Package

3D CHIP Stacked(TSV Technology)

QFP SQFP

High Performance

FDH-BGA

TAB-BGA

EBGA

TEBGA

FC-BGA

High-speed

COC High-speed

H-SiP

PGA BGA

Enhanced BGA

ConsumerAppliance

FC-CBGA

Package StructurePackageType Pin count

450 2116 5 7 Routers, severs,workstations, backbone transmisstiondevices

Routers, personal computers, graphics, digital TVs, set top boxes,printers

Personal computers, mobile,digital video cameras, digital still cameras, PDAs

Mobile, digital videocameras,digital still cameras,PDAs

7

13

15

17 60

20 40

25 60

2.5

1

1.5

2.5

1.6

1.6

450 2116

256 1156

256 1156

66 906

16 68

42 309

ApplicationI/O frequencyGHz

Heat resistance jaºC /W 0m/s

FC-PBGA(AlSiC-LID)

92.5450 1156FC-PBGA(Cu-LID)

TEBGA

PBGA

FBGA

QFN

WL-CSP

Personal computers, digitalTV, set tip boxes, printers15 1002.548 304

QFPLQFP

TEQFP

Packag

e

17

■ PBGA Low-heat Resistance Package（Ag paste type）As PBGA package, we provide Ag paste type which achieves both low-heat resistance and low cost.

A wider range of packages are available for high performance products.

■ QFP Low-heat Resistance Package（Stage-exposed type）We provide thermal enhanced QFP which achieves both low-heat resistance and low cost.

Heat resistance can be reduced significantly by exposing the die pad and connecting motherboard to ground.

■ SiP（System in Package） - Embedded example of QFPDue to the adoption of bonding/LF bus bar structure, internal pins are collaborated and external pins are reduced. We provide vari-

ous SiP-QFP which achieve high integration and low cost.

3W

4W

5W

PBGAPBGA Ag PasteAg Paste

PBGA

TEBGA

TEBGATEBGA Ag PasteAg Paste

Ag Paste

SubstrateLSI ChipEpoxy Resin

Ball AdhesiveAdhesive Insulator FilmInsulator Film

Wire

0

5

10

15

20

25

30

35

0m/s 1m/s 3m/s

Hea

t res

ista

nce

/W

Wind speed

Upper view Bottom view

LQFP Conventional product TEQFP

Exposed die pad

SolderSolder

Heat transferHeat transfer

Connection with TEQFP package Example

Motherboard

Die Padis exposed

LQFP144 Existing

TEQFP144Not connected with circuit board

TEQFP144Connected with circuit board

Data is reference value

Example of SiP stack &LF bus bar structure QFP208

- GND Chip-Stage- GND Stage-Lead- Power supply Chip-Bus Bar- Signal Chip-Lead / Chip-Chip

LSI Chip RF

Lead

Au Wire

LSI Chip Logic

LSI Chip Logic

Mold Resin

Mold Resin Mold Resin

Lead

Au Wire

Adhesive

Adhesive

LSI Chip FCRAM R

Die Stage

Die Stage Die Stage LSI Chip Logic

Au WireLSI Chip Flash

Bus Bar

Lead

Adhesive

SiP side-by-side structure Conventional

SiP stack structure Conventional

SiP stack LF bus bar structure

Packag

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18

■ Packages Lineup

※Please contact Fujitsu for more package types.

※Please contact Fujitsu for more package types.

PKG typeBody size

(mm)Ball pitch

PKG typeBody size

(mm)Ball pitch

1.27mm 1.00mm 0.80mm 0.65mm 1.27mm 1.00mm 0.80mm 0.65mm

PBGA

17.0x17.0 － 256 －－

FC-BGA

17.0x17.0 －－－ 625

19.0x19.0 － 321 －－ 21.0x21.0 －－ 592 －

27.0x27.0 256, 320

416, 480, 484, 493, 496, 544,

676

－－

23.0x23.0 － 484 －－

27.0x27.0 － 625 －－

29.0x29.0 － 729 －－

31.0x31.0 － 900 －－

31.0x31.0 353 564, 900 －－ 33.0x33.0 625 1020 －－

35.0x35.0352, 416, 420, 484,

520

676, 772,808, 868,900, 1156

－－

35.0x35.0 729 1156 －－

37.5x37.5 － 1206, 1369 －－

40.0x40.0 900 －－－

TEBGA

27.0x27.0 320416, 480, 484, 543,544, 676

－－

42.5x42.5 1089 1681 －－

45.0x45.0 1225 －－－

47.5x47.5 － 2116 －－

35.0x35.0416, 484,

520

676, 772,808, 868,900, 1156

－－※Please contact Fujitsu for more package types.

PKG typeBody size

(mm)Ball pitch

0.80mm 0.65mm 0.50mm

FBGA

5.0x5.0 －－ 66

6.0x6.0 －－ 82, 96

7.0x7.0 －－100, 112, 130, 144

9.0x9.0 －－ 168, 208

10.0x10.0 112 － 240, 289

11.0x11.0 － 176, 204 －

12.0x12.0144, 176,

192 －232, 304, 345, 385

13.0x13.0 －－304, 337,

385

14.0x14.0 －－ 506, 562

15.0x15.0 188, 240 －400, 586,

650

16.0x16.0 224 360, 385 610, 770

18.0x18.0256, 272, 320, 441 －

753,842, 906

PKG typeBody size

(mm)Reid pitch

0.65mm 0.50mm 0.40mm

QFP

14.0x20.0 100 －－

28.0x28.0 － 208 256

32.0x32.0 － 240 －

LQFP/TEQFP

7.0x7.0 － 48 64

10.0x10.0 52 64 －

12.0x12.0 64 80 －

14.0x14.0 － 100 －

16.0x16.0 － 120 144

20.0x20.0 － 144 －

24.0x24.0 － 176 216

28.0x28.0 － 208 256

HQFP

28.0x28.0 － 208 256

32.0x32.0 － 240 296

40.0x40.0 － 304 －

QFN

2.5x3.5 －－ 24

3.0x3.0 － 16 20

4.0x4.0 16 16, 20, 24 28

5.0x5.0 － 28, 32 40

6.0x6.0 － 40 48

7.0x7.0 － 48 56

8.0x8.0 －－ 68

9.0x9.0 － 64 －

Packag

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19

FC-BGA 450 pins 2116 pins0.65mm pitch 1.00mm pitch

PBGA 256 pins 1156 pins1.00mm pitch

QFP 100 pins 256 pins0.40mm pitch 0.65mm pitch

LQFP 48 pins 256 pins0.50mm pitch

QFN 16 pins 64 pins0.40mm pitch

0.80mm pitch

0.65mm pitch

1.27mm pitch

0.50mm pitch

FBGA 66 pins 906 pins0.50mm pitch

62517 17

48427 27

32027 27

25628 28

487 7

10014 14

14420 20

10014 20

48435 35

966 6

38512 12

75318 18

17611 11

11210 10

203 3

567 7

325 5

649 9

24015 15

32018 18

38516 16

67627 27

56431 31

115635 35

115635 35

168142.5 42.5

20828 28

[Example of notation] 625 Pin count 17 17 Package size Unit

■ Representative Packages（Actual size）

Design Methodology

20

Design Methodology

Design Methodology■ Overview of design methodology

Increased gates can be embedded in accordance with progressively miniaturization of LSI. There are chip designs with more than

10 million gates in recent ASIC development. We construct design environment “Reference Design Flow (RDF)” which targets

90nm ASIC, and now we have developed ASIC ranging from 0.13μm, 0.18μm, 65nm and 40nm.

We provide optimized design environment required for each technology and support customers’ LSI development.

For 40nm ASIC, we provide flexible business model and design support which are different from traditional ASIC model.

DesignExpressDesignExpress

User InterfaceUser InterfaceIntegration of customer properties

and our design technology

Chip-Package CodesginChip-Package CodesginPrototyping of chip and package

One Pass Success

Low Noise Design•••••

••

••

•••••

Early IR Drop EstimationEarly SSO Noise EstimationDecoupling Cell EstimationDynamic IR Drop AnalysisClock Jitter Analysis

Low Power Consumption TechnologyCPF/UPF SupportMulti power Multi Voltage DesignPower GatingMulti-Vth CellsClock Gating

Design For ManufacturingLayout Considering YieldStatistical Timing Analysis

Design For TestCompression Scan BIST Technology Actual Speed Test

LSI Design FlowLSI Design FlowOptimum design enviroment which supports

LSI based on our reference flow

System For “One Pass Success”System For “One Pass Success”

Milestone of Design MethodologyMilestone of Design Methodology

Power Closure

Desi

gn S

olut

ion Power Integrity & Noise Analysis

Timing Closure

Design For ManufacturingLitho Aware DesignLitho Aware Design

Electrical DFMElectrical DFM

Rule BaseRule Base Analysis & Optimization Analysis & Optimization

GHz IF AnalysisGHz IF AnalysisDynamic IR Drop/Substrate NoiseDynamic IR Drop/Substrate Noise

SSO Noise / Static IR Drop / Core NoiseSSO Noise / Static IR Drop / Core Noise

CPF Base Design FlowCPF Base Design Flow

DVFSDVFSAdaptive Supply VoltageAdaptive Supply Voltage

MCMM OptimizationMCMM OptimizationTiming Closure / SI ClosureTiming Closure / SI Closure

SSTA BaseSSTA BaseOptimizationOptimization

Statistical OCV AnalysisStatistical OCV Analysis Statistical Timing AnalysisStatistical Timing Analysis

Clock Gating/ Multi-VDD/ Multi-Vth Optimization/ On Chip Power Gating Clock Gating/ Multi-VDD/ Multi-Vth Optimization/ On Chip Power Gating

2002 2003 2004 2005 2006 2007 2008 2009 2010 2011 2014

TechnologyNode

Year

90nm 65nm 40nm 28nm0.18 m/0.13 m

Design Methodology

21

■ User Interface

Fujitsu provides design methods with 5 basic development interfaces.

ASIC development project can be done with efficiency by harmonizing customer design and our design technology.

1

Library

IP

Design

Wafer Process

Probe Test

Assembly

Final Test

Pure ASIC TGD ASIC COT+DS,FTK

COT+IP Support Pure COT

ASIC COT

Business Models

Customer

Fujitsu Design Methodology

22

■ LSI Design Flow

We adopt Reference Design Flow (RDF) as a basis and apply design flow which complies with LSI characteristics.

Logic Synthesis

Back EndBack EndDesignDesign

Sign Off VerificationSign Off Verification

Test circuit insertionPrototyping

Formal VerificationTiming constraint verification

Static timing verification Trial layout simulation Handoff verification

LayoutPlacement Routing

Physical Verification

Resource verification

Statatical static timing verification

Crosstalk noise analysisPower analysis

Test pattern generation

Gate simulation Power analysis

Logic Synthesis

PhysicalDesign

Sign off

DFT

LSI Design FlowLSI Design Flow OverviewOverview

Design Methodology

23

■ DFT（Design For Test） Technology

Required numbers of test pattern become increasingly large in accordance with refined manufacturing process, high integration and

high speed operating frequency. In the past, test pattern is able to maintain its high quality for faults. However, test patterns which

are applicable for delay fault become general recently due to increasing percentages of delay fault. For achieving high quality stan-

dards, we provide mechanism for delay fault testing in system operation and same cycle.

●Compression ScanBIST technology can be applied to compress ATPG pattern,

its compression performance is 10 to 100 times of traditional

scan. We and other third parties are adopting this technology.

It enables application of large numbers of required test pat-

terns for achieving high quality standards.

●At-speed test using PLLAt-speed test can be carried out at the same time as system

operating frequency for defect detection in regards to delay

fault. If the speed exceeds the capability of tester system, we

would prepare a clock control inside the chip, control the inter-

nal clock such as PLL, and generate a necessary clock for

test. At-speed test supports core logic and memory BIST. It

enables small defect detection and high quality provision.

Internal Scan Chain

Core Logic

BIST Controller

Overview Diagram of Compression ScanOverview Diagram of Compression Scan

PLLClock

Controller

Reference Clock

PLL Output Clock

Clock ForMemory BIST

Clock For Logic Delay Test

Block For Actual Speed Test Using PLLBlock For Actual Speed Test Using PLL

Design Methodology

24

■ Back-end Design

Based on “Reference Design Flow”, we provide design layout for customers by high precision analysis technology, advanced P&R/

optimization technology, low power consumption technology and low noise design technology.

●PrototypingAs circuit scale is increased in accordance with LSI miniatur-

ization, the development period becomes longer.

We validate early design condition and timing convergence by

prototyping.

●CPF and UPF SupportWe support CPF and UPF, perform physical design and phys-

ical verification according to power specification with func-

tional verification. High design quality can be achieved even

for complex low power consumption technology.

●Multiple modes・Corner OptimizationIncreasing numbers of process, voltage and temperature con-

dition (corner conditions) need to be considered in accor-

dance with LSI miniaturization. Also, operating modes have

increased to ensure multi-functionality and reliability of LSI.

Our physical design performs placement/ routing/ optimiza-

tion which considers multiple corner conditions and operating

modes. Repetition and development period can be reduced.

●Power Analysis・Crosstalk Noise AnalysisAs increasing miniaturization and low power voltage of LSI,

delay variations become greater by IR drop (voltage drop)

and crosstalk noise inside LSI.

By high precision IR drop and crosstalk noise analysis, we

have verified that it does not influence system operation.

Early Estimation• Area estimation• IR drop estimation• SSO noise estimation

Floorplan Simple Layout• Demonstration of estimated results• Verification of timing and routing convergence• Pad assignment• Verification of timing constraint

Verification• Timing• Power• Noise

Short TAT

PrototypingPrototyping

TimingConstraintCorner

Condition

Multiple modes Corner OptimizationMultiple modes Corner Optimization

Power AnalysisPower Analysis Crosstalk Noise AnalysisCrosstalk Noise Analysis

Design Methodology

25

■ Low Power Technology

There are increasing demands of power consumption reduction towards LSI in recent years. We make various efforts in ASIC

design with low power consumption which cope with customer needs.

It would be effective to combine different technologies for

achieving LSI with low power consumption.

Our design environment “Reference Design Flow” supports

various low power technologies, power consumption can be

reduced at LSI operation and standby.

By controlling power supply, we especially organize and

develop CoolAdjustTM to reduce power consumption.

Through full adoption of CPF/UPF, it can minimize changes to

customers’ design and to facilitate the application of CoolAd-

justTM. In addition, design with high reliability can be per-

formed even for low power technology.

●Multi Power Supply・Multi Voltage DesignDue to multi voltage technology in LSI, different voltages can

be supplied according to the operating speed of circuit block.

Hence, power consumption can be reduced during operation.

Circuit block with different voltages can be designed and veri-

fied by adopting CPF/UPF, development period can be mini-

mized with low power design.

●Clock GatingPower consumption can be reduced during LSI operation by

stopping clock supply of suspended circuit block.

●Power GatingPower gating is a technology which shut off power supply to

suspended blocks by switches. Power consumption during

standby can be reduced up to 1/1000.

We suppress the power supply noise generated by controlling

the power switch, hence malfunction of LSI can be avoided.

Suspended circuit blocks can be designed and verified by

adopting CPF/UPF, development period can be minimized

with low power consumption design.

●Multi-Vth CellsMulti-Vth design is technology which efficiently uses low-Vth

cells consisting of transistors with high speed in paths with

critical timings and high-Vth cell consisting of transistors with

low speed in non-critical paths. The overall speed of LSI can

be maintained and power consumption can be reduced dur-

ing standby mode.

Rewiring after Vth modification is unnecessary. the develop-

ment period would not be affected.

Design Level Design Technology Effects

Memory Access Reduction

Computation Reduction

Architecture Selection

Effective Use of Cache

Netlist Optimization

Clock Gating

Multi-Vth Cells

Cells with Multiple Gates

Low-power SRAM

RTL Design

Logic Sysnthesis

Layout

CoolAdjust™

RTL Optimization

Small

Large

Dyn

amic

Sta

tic C

ontr

ol T

echn

olog

y of

Vol

tage

,

Cur

renc

y an

d V

thA

dapt

ive

Vol

tage

Con

trol

Pow

er G

atin

g, M

ulti

pow

er

supp

lyM

ulti

Vol

tage

Des

ign

Low Power Technology And Its EffectsLow Power Technology And Its Effects

SystemLevel Design

Low Power TechnologyLow Power Technology

Power switch

Power-off area

Leve

l shi

fter

& I

sola

tor

Enable

Clc

ok

Enable

Always-on area

Retention FF

Low power SRAM

Power-off area

Power switch

Low Vth Cell

High Vth Cell

Critical pathClock gating

Always-on buffer

Design Methodology

26

●SRAM with Low Power ConsumptionPower consumption of SRAM macro would be a problem

when LSI is embedded with large capacity SRAM. By using

multi-mode SRAM, power consumption can be reduced.

In addition to normal operation mode, multi-mode SRAM also

has standby mode and sleep mode.

Same as clock gating techniques, operating power of SRAM

macro would become almost 0 by stopping internal clock

operation in standby mode.

In sleep mode, leak power would be reduced by deviating the

peripheral circuits of SRAM macro.

＊ : Depends on SRAM configuration

●Low power design environments that fully employed CPF/UPFBy full employment of CPF*1 and UPF*2, we provide full solu-

tions which support power gating, functional verification and

physical verification of multi power・multi voltage designs.

Operation of suspended circuit blocks can also be verified by

this design environment.

Through defining multi power・multi voltage by CPF/UPF, logic

synthesis can be optimized with consideration of voltage in

each logic block.

The verified RTL and CPF/UPF would be directly transferred

to physical design and physical verification. Hence, vague

power supply information of interface can be verified and

design with high reliability can be carried out.

*1: CPF(Common Power Format) is a standard specification which

describes standardized low power design in Si2.

(http://www.si2.org/?page=811)

*2: UPF(Unified Power Format) is a standard specification which

describes standardized low power design as IEEE Std. 1801-

2009.

(http://www.ieee.org/)

Operating Mode Function EffectNormal operation mode Normal RAM operation －

Standby mode Suspended operation Operating power is almost 0

Sleep mode Data maintenance Leak power is about 1/3*

Design EnvironmentDesign Environment Our Design Environment employed CPF/UPFOur Design Environment employed CPF/UPF

Specification

CPF/UPF

Functional VerificationVerification of power-on state only

Logic SynthesisSynthesis without considering

supply voltage

Physical DesignDesign based on

Paper Specification

Physical VerificationVerification based on

Paper Specification

Functional VerificationVerify power ON/OFF state

Logic SynthesisOptimum synthesis per supply voltage

Physical DesignDesign baed on CPF/UPF

Physical VerificationVerification based on CPF/UPF

Design Methodology

27

■ Low Noise Design

●Estimation of IR Drop/SSO Noise at Early StageIn conventional design flow, IR drop analysis and SSo noise analysis

are done at latter stage. If any errors were detected, a lot of time is

needed to recover. Besides, these analysis are extremely high load-

ing. Fujitsu innovates the technology for IR drop and SSO noise esti-

mation at early design stage which can optimize I/O arrangement and

power supply design, and avoid design iterations significantly.

●In-house tool for Estimation and Place-ment of Decoupling-Capacitance Cells

For decreasing Dynamic IR drop caused by simultaneous

switching of core cells, placement of decoupling capacitance

cells near the noise sources is effective. Fujitsu has in-house

developed tool that can estimate the required capacitance

from power, operating frequency, and supply voltage, then

place decoupling capacitance cells automatically to the ade-

quate place to minimize Dynamic IR drop.

●Dynamic IR Drop AnalysisAs process is refined with low voltage, possibility of delay

variation and memory malfunction becomes increasingly

higher due to fluctuation of power supply and ground voltage.

On top of static IR drop analysis, we support LSI development

by capturing voltage variations considered time axis, reinforc-

ing power supply wiring, inserting decoupling cells and mov-

ing noise cells etc., hence “one pass success” can be

achieved.

●Clock Jitter AnalysisVoltage variations of power supply and ground vary gate

delay of clock line. It would especially affect high-speed DDR

and characteristic of analog・macro. By introducing above-

mentioned dynamic IR drop analysis and clock jitter analysis,

we can make design with consideration of those impacts.

Early IR Drop AnalysisEarly IR Drop Analysis

Assignment of Decoupling CellsAssignment of Decoupling Cells

Cell

Decoupling Cell

Power Trunk

Power Rail

PowerSupply

Ground Occurence of Jitter

The GroundThe Ground

Power SidePower Side

Dynamic IR Drop Analyzed WaveformsDynamic IR Drop Analyzed Waveforms

Design Methodology

28

■ DFM（Design For Manufacturing）Our DFM technology can achieve high yield. Part of them will be introduced as follows.

●Statistical Timing Analysis Statistical variation of transistor can be handled by incorporat-

ing delay analysis and it enables accurate delay analysis.

While circuit operates correctly with target frequency, process

capability can be brought out to the maximum.

●Layout considering yieldOur cells and macros are developed by taking the impact of

lithography into account during development.

In addition, we adopt various measures that lead to improved

yield and other redundant vias as required.

Process optimization &control

APC : Advanced Process ControlLMS : Lithographic Management System

APC LMS

Tecnologyparameter

Layout considering yield cost

Yield Analysis Variation Analysis

Statistical timing analysisCD

FREQ

UEN

CY

Yield & failure analysis technologyDefect Model

Yield Model

DFMData Base

Cell/macro designOptimization & Control

Lithographic DRC Layout Analysis

Cells and macros are optimized according to technology

parameter which gained from optimized process.

Optimized cells and macros

actualize optimum layout based

on technology parameter in LSI

desgin.Yield & failure analysis results would

be performed in process and design.

DFDFM Design for ManufacturingDesign for Manufacturing

Statistical Timing Analysis

Delay is circulated as statatical information but not min/max absolute value.

Delay=f(X1,X2,…,Xn)Statatical Delayed Information

Wiring that considers yield

Redundant Via

Wire Spreading

Considering lithographic influence

Layout Pattern Lithographic DRC

Design Methodology

29

■ Chip-package codesign with noise consideration

We perform LSI development based on chip-package codesign flow and achieve “one pass success”.

Chip designers and package designers would cooperate closely and to perform prototyping of chip and package. It optimizes floor

plan examination of chip and pin assignment for pad-package, hence wiring and electrical characteristic of packages can be

enhanced.

Problems discovered in actual design process can be handled by prototyping process.

Wiring and electrical characteristic of packages can be

enhanced by optimizing pin arrangement of pad-packages.

Efficient timing analysis considering noise can be made

according to timing analysis environment template.

Chip Chip - Package Codesign Flow Package Codesign Flow

Prototyping

FujitsuCustomer

Feedback

Tranmission path condition

PackagePin Arrangement

AC Spec

PC B DesignConstraint

Examination

PC BDesign

ChipPackage

I/O Selection

Floorplan Examination

IR-Drop Estimation

Optimization of pad-package pin assignment

Electrical Characteristic Estimation

Noise Timing Verification

Package Design Chip Design

Electrical Characteristic Sampling

Noise Timing Verification

LSI Manufacture

Pro

toty

pin

gA

ctu

al

De

sig

nV

er

ifica

tion

Chip

Package

PackagePin

Pad

Optimization of Pad-Package Pin AssignmentOptimization of Pad-Package Pin Assignment Timing Analysis Considering NoiseTiming Analysis Considering Noise

SSO Noise

Chip Package PCB DRAM

O

I

Jitter

Jitter caused by SSO Noise

Reliability

30

Reliability

Reliability■ Pursuit of quality and reliabilitySemiconductor devices of Fujitsu adopt most advanced technology and have been regarded as high quality and reliable products

both domestically and overseas. We always have a serious commitment to quality and reliability. Particularly, we believe people,

process and product contribute significantly to this outstanding result.

●High quality by personnel educationDue to our special education program and Qfinity activity, our

workers are not only equipped with proficient skills in processes,

we are dedicated to achieve high quality and reliability.

It is a comprehensive system which enables workers to fully

aware of the importance of assuring high quality products.

●High quality built-in at every stageMaintenance of optimum manufacturing process is the key point

of stably supplying high-yield and high-quality LSIs.

From planning to final delivery, every stage of manufacturing pro-

cess is under thorough checks based on strict quality standards.

●High reliability for all sectors of societyAs a leading company of computers and communication devices,

we manufacture products according to various needs of custom-

ers. We aim to provide high reliable goods which produce from

high reliable semiconductor devices that are suitable for all sec-

tors of society.

■ Manufacture of ASIC products with high reliability

● Quality Assurance ProgramWe evaluate and examine semiconductor devices in every stage

from marketing research to planning, design, development,

experiment and mass production according to quality assurance

program. The building of quality has started in the stage of pro-

duction already. We incorporated customer demands which are

analyzed from marketing research into product planning, and it

can be reflected in the quality. This kind of quality building will be

continued in all stages of production such as design, develop-

ment and mass production.

Our Quality SupportOur Quality Support

CustomerCustomer

Sat is f i cat ionSat is f i cat ion

High QualityHigh Quality

Continual ImprovementContinual Improvement

Mechanisms and techniques Mechanisms and techniques

supporting qualitysupporting quality

Awareness for the realization of high qualityAwareness for the realization of high qualityPersonal development to support qualityPersonal development to support quality

PlanningPlanning DevelopmentDevelopmentMassMass

ProductionProduction MarketMarket

Manufacturing thatfully emcompasses

high quality

All-company All-company

improvement activitiesimprovement activities

SCRUMSCRUM

Remarks: SCRUM (Satisfying Cusomers & Reforming of Us Movement) includes

Qfinity Activity” of whole Fujitsu Group and it is initiated for resolving

assignments with the aim of reaching goals.

Verificationof productplanning

DesignFMEA

Verificationof basicdesign/technology

Evaluation ofelectrical characteristic and reliability Process FMEA

Productionqualificationtest

ScreeningReliabilitymonitoring test

Market researchProduct planningDevelopment plan

ProductDesign

Prototype ofpilot circuit

Developmentprototype

Mass productionprototype

Massproduction

PlanningReview

DR0

TechnologyReview

DR1

Mass ProductionTransitionReview

DR2

Mass ProductionStartedReview

DR3

Mass ProcutionStabilityReview

DR4

Flowchart of Quality Assurance ProgramFlowchart of Quality Assurance Program

Reliability

31

● Basic Assessment TestIn order to ensure reliability in new technology development, assessment is taken place by using TEG*1 for each basic failure

modes. Assessment has been carried out between transistor and wiring relationship. (Refer to table 1)＊1: TEG (Test Element Group)

Collection of single element for evaluating specific failure modes.

Table-1　Basic Assessment Test

● Production Qualification TestWe focus on technical items which affect product reliability and would take its novelty and combination into account to perform prod-

cut grouping. Each group is represented by use of TEG, hence production qualification test (evaluation assessment) is conducted.

◆ Reliability Assessment for Representative Product

We would consider the following topics when determining product grouping and representative product:

　●Process technology　　　・Design rule　　　・Employed material　　　・Structure　●Assembly technology　　　・Design rule　　　・Employed material　　　・Structure　●Circuit technology　●Combination of process technology and assembly technologyTesting items and sample size are determined in accordance with technology novelty and assessment purposes. (Refer to Table-2)

Table-2　Production Qualification Test

*2 : For surface mount packages, heat stress is added before testing.

Assessment Item Design elements Acceleration factorsElectro migration Wiring material, structure, current density Current density, temperature

Stress migration Wiring material, structure Temperature, stress

Hot Carrier Injection Transistor structure, impurity concentration

Electric field

Gate Oxide Integrity Structure, oxide characteristics Electric filed, temperature

NBTI　[NegativeBiasTemperatureInstability]

Transistor structure,oxide characteristics Electric filed, temperature

Commission of new process technology

Circuit technology unitCombination of process

and assembly technologyAssembly technology

High temperature continuous operation*2

125 ℃77×3lot 77×1lot Option 31×1lot

High temperature and humidity operation *2

85 ℃ , 85%RH46×3lot 46×1lot Option 18×1lot

Temperature cycle ＊２ -65 ℃ ~150 ℃ 46×3lot 46×1lot 18×3lot 18×3lot

PCT*2 121 ℃ , 100%RH 46×3lot 46×1lot 18×3lot 18×3lot

PCT-Bias 121 ℃ , 100%RH 26×3lot 26×1lot Option 11×1lot

Low temperature operation -55 ℃ 26(Option) 26(Option) 11(Option) 11(Option)

High temperature placement 150 ℃ 26(Option) 26(Option) 11(Option) 11(Option)

Thermal shock　0 ℃ ~100 ℃ 26(Option) 26(Option) 11(Option) 11×1lotMechanical environment －－ 11(Option) 11(Option)Electrostatic destruction-1 (machine) 3 3 －－

Electrostatic destruction-2 (human charge) 3 3 －－

Latch up 3 3 －－

Temperature characteristic assessment 2 2 －－

Reliability

32

● Production StageMaintaining high quality and steady production after development stage is essential. It is necessary to manage and understand the

condition of manufacturing sites to ensure its stability.

●Management of ProcessIf there are problems affecting quality and reliability in manufacturing process, quality assurance department would take the lead,

determine the cause immediately and take measures. Also, quality assurance department would confirm the effectiveness of mea-

sures.

● Failure Analysis and Cause InvestigationWe do not only monitor the manufacturing process, but also results of wafer probing test and final test of finished goods. Failure

analysis of defective goods would be executed. The results would be feedback in the process. In addition, analysis result of defec-

tive products from customers is valuable for preventing defects. The results would be reported to relevant departments for measure

planning.

Analysis results do not only contribute to the improvement of cause, but also to progressive development. In addition, horizontal

expansion is also carried out.

●Failure Analysis of defective productsWe would analyze failures thoroughly and prevent recurrence of problems. Effective information analysis would be carried out. We

devote great effort to this since the feedback would become direct policies for reliability improvement.

Customer complaints are first handled by our sales department. Then, reliability assurance department would analyze the electrical

and physical cause by the use of EMS, SEM and FIB etc,. Technical and manufacture department would take measures based on

the analysis results.

Moreover, we do not only focus on the problematic site, we are required to carry out measures towards all our manufacturing sites.

Please visit http://jp.fujitsu.com/microelectronics/brochures/catalog/ for quality and reliability assurance of Fujitsu semiconductor

devices.

FSSQuality Assurance Department

Reliability Assurance Department

Engineering Department

DesignTesting

AssemblyProcess

Process

Assembly

Testing336h48h

Final reportMid-term report

Objective Arrangement

Custom

ers

Technical Departm

ent

Factory

Quality A

ssurance D

epartment

Production Management Department

ProductionPlanning

Circulation

Supporting Flow of ClaimSupporting Flow of Claim

Number of days since the reception of reliability assurance department.

Reliability

33

■ Certification Acquisition: ISO9001:2008, ISO/TS16949:2009

＊ 1： TS16949 Akiruno Technology Center is included in their scope of certification as a supporting department.＊ 2： TS16949 FIM head office and Aizu Factory are included in the scope of certification of Miyagi Factory as a supporting department.

■ Certification Acquisition: ISO14001:2004

Plant name・office Acquisition specification

Registration day Certification number

Certification body

Fujitsu Semiconductor Co., LtdAkiruno Technology Center ＊ 1Iwate FactoryAizuwakamatsu FactoryMie Factory

Fujitsu Semiconductor Technology Co., Ltd

ISO9001（2008）

5th December 2003 JQA-QMA10719

JQA

TS16949（2009）

29th August 200829th August 2008

5th December 2003

23rd July 2010

JQA-AU0010-1JQA-AU0010-4JQA-AU0010-5

JQA-AU0010-6

Fujitsu Integrated Macro Technology Co., LtdHead office・Aizu Factory ＊ 2Miyagi FactoryKyushu Factory

ISO9001（2000）

26th November 2004 JQA-QMA11777

TS16949（2002）

31st October 200823rd October 2009

JQA-AU0197-1JQA-AU0197-2

Plant name・office Registration Day Certification number

Certification body

Fujitsu Group WORLD-WIDE Certification　(Including the following plants and offices)

　Fujitsu Semiconductor Co., Ltd　　Akiruno Technology Center　　Mie Factory　　Aizuwakamatsu Factory　　Iwate Factory　Fujitsu Integrated Macro Technology Co., Ltd　　Head office・Aizu Factory　　Miyagi Factory　　Kyushu Factory　Fujitsu Semiconductor Technology Co., Ltd

12th September 1995 EC98J2005 JACO

34

Desig

n C

ente

r

Design Center

Design CenterCollaboration with customers is one of the key success factors in ASIC design. We construct satisfactory support environment for

customers by our corporation’s main office and expanding design centers with outstanding achievements and design capability.

■ Design Center

■Fujitsu Semiconductor (Shanghai) Co., Ltd. (FSS)・Shanghai : Headquarters, Sales & Marketing Office, IC

Design Center

■Fujitsu Semiconductor Asia Pte. Ltd. (FSAL)・Singapore : Headquarters, Sales office, ASIC Support Design

Center

■Fujitsu Semiconductor Pacific Asia Ltd. (FSP)・Hong Kong : Headquarters, Sales Office, ASIC Support

Design Center, System Solution Design Center, IC Design CenterSingapore

Shanghai

Hong Kong

Documents

Fujitsu Semiconductor...s 40 nm S i-g a te CMO S ＋ 1.1V± 0.1V C S 201 erie 65 nm S a te CMO S pport s a wide r a nge from ＋ 0.9V ～＋ 1. 3 V C 101 erie 90 nm S a te CMO S Over