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Ladder Diagram

for Festo Controllers

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Programming Ladder Diagram with Festo FST

2

Order no.: 18348Description: MANUAL KOPDesignation: E.HB-KOP-GBStatus: 02/97Author: B. PlagemannEditor: S. Baerwald, YC-ECI

2nd edition

Copyright by Festo KG, 73734 Esslingen,Germany, 1991

All rights, including translation rights, reserved.No part of this document may be reproducedin any form (printing, photocopy, microfilm orany other process) without the prior writtenpermission of Festo KG.

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Programming Ladder Diagram with Festo FST

3

Preface

This book is intended as an aid to anyone whohas to program programmable logic controllersfrom Festo.

It is not intended as a textbook but as a refer-ence work and an aid to solving problems as-sociated with control technology. All operationsand operands that can be used with a FestoPLC are explained and - in most cases - illus-trated with examples.

You know the sort of question that sometimesoccurs when working on a project. "How doyou carry out an exclusive OR operation inLadder diagram?"

This is where this book provides help: simplyrefer to the section "Exclusive Or" and you’llfind a program example.

It’s as simple as that.

Have you found any errors? Have you foundany particular question unanswered?

Certainly there will be room for improvement.Help us to improve this book by sending apostcard with a description of the missing so-lution, the error or with any other comments to:

Festo KGRuiter Str. 82D-73734 EsslingenGermany

Many thanks!

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Programming Ladder Diagram with FESTO FST

4

Contents

Chapter 1 Fundamental characteristics ofFST software.................................................. 71.1 Notes ...................................................... 91.2 Structure of FST Software...................101.3 Programming languages......................11

Chapter 2 Entering a program.....................................13

Chapter 3 Operands ......................................................193.1 Notes ....................................................213.2 Bit and word operands .........................233.3 Bit operands .........................................243.4 Word operands ....................................263.5 Retentive operands..............................29

Chapter 4 Structure of a Ladder diagram program.314.1 Notes ....................................................334.2 What is a rung comprised of? .............344.3 Conditional and executive part ............374.4 How is a rung processed?...................384.5 How fast is a controller? ......................46

Chapter 5 Operations - an overview..........................47

Chapter 6 The operations in detailExamples for reference..............................59

Chapter 7 Addressing operands ..............................1437.1 Absolute and symbolic addresses.....1457.2 Information content of

absolute addresses............................153

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Chapter 8 Programming timers .................................1598.1 General ...............................................1618.2 Timer types.........................................1658.3 Examples ............................................1698.4 Evalutation of the individual

timer elements ....................................178

Chapter 9 Programming counters ............................1819.1 What is an incremental counter? ......1849.2 Elements of the counter.....................1869.3 Programming counters.......................191

Chapter 10 Using registers..........................................197

Chapter 11 Using flags .................................................20111.1 Flag bit.................................................20311.2 Flag word ............................................207

Appendix A Example programs ....................................209A.1 Sequence programs...........................211A.2 Measuring the cycle time...................220A.3 Structured programming in

Ladder diagram ..................................233

Appendix B Differences in program execution.........239B.1 Process image ...................................241B.2 Multitasking.........................................244B.3 Multiprocessing ..................................246B.4 Interrupt capability ..............................247B.5 Internal inputs and flags .....................248B.6 Serial data port ...................................251B.7 Behaviour after battery failure...........253B.8 Input signal delay................................255

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6

Appendix C Subroutines, Multitasking andMultiprocessing ........................................257C.1 Modules ..............................................265C.2 Multitasking.........................................267C.3 Multiprocessing ..................................272

Appendix D The binary and hexadecimalnumber system ..........................................277D.1 The structure of number systems .....279D.2 The binary number system ................282D.3 Differentiation in Ladder diagram......289

Index ......................................................................291

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7

Chapter 1

Fundamental characteristics

of FST Software

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8

Contents

1.1 NOTES ................................................... 9

1.2 STRUCTURE OF FST SOFTWARE.10

1.3 PROGRAMMING LANGUAGES.......11

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9

1.1 NOTES

In FST software every self-contained PLCsystem is called a project. Each project cancontain one or more programs, modules andprogram and module versions.

Each project has an allocation list that cancontain several (internal and external) parts.

Each program or module version has its ownerror list, which records all errors found bythe system.

Within a project individual programs andmodules can be processed together (cross-reference list, load, print).

Programs or modules can be imported fromother projects.

Documentation on a project can be createdwith a comment header and operating instruc-tion.

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10

1.2 STRUCTURE OF THE FST SOFTWARE

You want to program an automatic assemblymachine for pneumatic valves. A rotary index-ing table offers 8 automatic work stations anda manual work station. The valve is fully as-sembled on this rotary indexing table. It is thenplaced on a conveyor belt which transports thevalve to an automatic testing machine and to apacking machine.

A programmable logic controller is used for theautomatic assembly machine. The entire pro-gram for this controller is a project.

Each automatic work station and the rotary in-dexing table are individual programs ormodules within this project. The arrange-ment will depend on the programming methodused by the programmer.

Sensors and actuators are mounted on theautomatic assembly machine. These are con-nected to the inputs and outputs of the PLC -the operands of the PLC. In addition thereare internal operands such as flags, timers,counters, registers, programs and modules.

A project may not only contain several pro-grams or modules but also - when using theFPC 405 - several processor modules. All ofthese processor modules access the inputsand outputs. Each processor module canagain execute several programs or modules -but only within one project.

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11

Documentation is prepared for the entireproject. The documentation comprises

• Cover sheet with the name of the project

• Text to describe in the project and the indi-vidual processor modules, programs, mod-ules, etc., possibly with notes on operation,spare parts, etc.

• Allocation list with all operands

• Printout of all programs and modules withcomment lines

• Cross-reference list showing which oper-and is used at which point in which programor module.

1.3 PROGRAMMING LANGUAGES

The FST software comprises a range of pro-gramming languages for programming thevarious PLCs. These include

• Ladder diagram

• Statement list

• BASIC

• Assembler

• Matrix programming

This book deals only with ladder diagram pro-gramming, which is available with all FestoPLCs (FPC 100, FPC 405, IPC, FEC).

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12

Notes

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2. Entering a program

13

Chapter 2

Entering a program

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14

Contents

Entering a program ............................ 15

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15

When creating a Ladder diagram program withFST software, we recommend the followingprocedure:

• Plan the program as a function chart, se-quence diagram, text, structure chart orsimilar.

• Call up FST software

• Create project:The project name must meet the require-ments of the MS-DOS operating system, asa subdirectory is created on your massstorage medium (normally the hard disk) forthe project. This means that the projectname can be up to 8 characters, and mustnot contain spaces or periods. For MS-DOS version 3.0 or later, a subdirectorymay also contain special characters suchas the German Umlaut (ä, ü, etc.). Thisdoes not apply to DOS versions prior to3.0.

• Enter text for Title page and page header:This makes your printout easier to read.

• Create an allocation list for inputs andoutputs:It makes sense to create the allocation listfor inputs and outputs before entering theprogram and then to print it out immediately.Then it is not necessary to write down in-puts and outputs.

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16

• Entering the Ladder diagram program:When creating the program you areprompted for some or all of the followingentries, depending on the controller type:

Central control unitAllows the entry of the processor module num-ber for projects involving several processors(FPC 405).Important: If only one CCU is used, no. 0must be used.Default value: No. 0

Type program/moduleAllows you to indicate whether you want tocreate a program or a module.Important: At least one program must be en-tered.Default value: Program

Prog./module no.Allows entry of the number for the program ormodule.Important: A program number 0 must alwaysexist, otherwise your processor module can-not start execution.Default value: 0

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Version numberAllows you to create up to 9 different versionsof a program or module.Important: You can only load one version of aprogram or module into a processor module.Default value: 1

TaskHere you can enter a commentary which willhelp you to relocate this particular program,version or module. This commentary does notappear on any printout and is only intended asa programming aid.

You want to start a completely new program?Simple. Leave everything as it is and press the<F1> key for "Create". The default values aresuch that you can load a controller with a sin-gle program and execute it.

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18

• • Enter program:The Ladder diagram editor for FST soft-ware is controlled by means of the functionkeys and/or mouse (version 3.1 or later).You only use the keyboard of your PC forentering the names of operands. All opera-tions (with the exception of entries in theboxes) are called with the aid of functionkeys or the mouse. Function key <F9> isthe help key. It opens a help window whereever you are in the FST software.Function key <F10> toggles the functionkey allocation.

• • Save program:Using function key "File menu" (normally<F8>).

• Test the syntax after program. If neces-sary, view or print the error list and correctthe errors.

• Print out the program.

• • Load the program into the controller.

• Test the program with the aid of the on-line function and with the aid of the statusdisplay (version 3.1 or later).

• Create Documentation.

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3. Operands

19

Chapter 3

Operands

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3. Operands

20

Contents

3.1 NOTES .................................................21

3.2 BIT AND WORD OPERANDS...........23

3.3 BIT OPERANDS..................................25

3.4 WORD OPERANDS............................27

3.5 RETENTIVE OPERANDS ..................30

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3. Operands

21

3.1 NOTES

The FST software allows the use of bit oper-ands and word operands (no byte and nodouble/longword operands).

The FST software allows the use of absoluteand symbolic operand addresses. Only abso-lute addresses are used in the following. Fordetails on symbolic addresses see Chapter 7,"Addressing the operands".

The number of operands of an individual typethat can be used depends on the type of FestoPLC.

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3. Operands

22

The absolute operand address has the follow-ing structure:

Fig. 3/1: Construction of an absolute operandaddress

The operand address must never containspace characters!

F3 . 12

Number of bit

. 4

Point separating bit and word

Number of word

Point separating processormodule and word(not for FPC100B/AF, IPCand FEC)

Number of CCU(not for FPC100B/AF, IPCand FEC)

Operand identifier(here F for flag)

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3. Operands

23

3.2 BIT AND WORD OPERANDS

All Festo PLCs have a word-oriented internalorganization. This means that all operands areorganized and can be used as words (with theexception of the initialization flag FI, the one-bit operands T for Timer and C for Counterand the operands P1 for Program andCMP/CFM for modules).

Every word is 16 bits long and can be used foran unsigned decimal number (0 to 65,535), asa signed decimal number (-32,767 to+32,7676) or as a hexadecimal number ($0 to$FFFF). For inputs and outputs not all 16 bitsare always available externally, so that in manycases only 8 bits of an input or output wordcan be used.

In the case of input, output and flag wordseach bit can be addressed individually.

In the case of registers, timer preselects,counter words and error word, the words canonly be addressed as words.

The counter commands increment and dec-rement can be used with all words, not onlycounter words.

Arithmetic and logic operations can be usedfor all words.

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3. Operands

24

3.3 BIT OPERANDS

Operand Designator Syntax Application Example

Output O On.n(On)

Condition O0.3

Output O On.n(On)

Execution

O0.3

Module CMP CMP n ExecutionCMP 0Module

Input I In.n(In)

Condition I3.2

Error E E Condition E

Functionmodule

CFM CFM n ExecutionCFM 0Module

Flag F Fn.n.n(Fn.n)

Condition F3.2.0

Flag F Fn.n.n(Fn.n)

Execution

F3.2.0

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3. Operands

25


Initializa-tion flag

FI FI Condition FI

Program1 P Pn Condition P2

Program1 P Pn Execution

S

P3

Timer T Tn Condition T9

Timer T Tn Execution

S

T0

Counter C Cn Condition C21

Counter C Cn Execution

S

C21

Counter C Cn ExecutionINC

C212

Counter C Cn ExecutionDEC

C212

1. The FPC 100 does not have the operand Program.

Important: There is no „Program“ operand for the FPC 100B/AF.The syntax may vary according to the controller (as shown inbrackets).

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3. Operands

26

3.4 WORD OPERANDS


Outputword

OW OWn(OW)

Condition OW2

>M_B_OP

Outputword

OW OWn(OW)

Execution M_B_OPTO

OW5

1

Input word IW IWn(IW)

Condition IW3

M_B_OP 1

=

Error word EW EW Condition EW

M_B_OP 1

=

Error word EW EW Execution M_B_OPTOEW

1

Functionunit

FU FUnn Condition FU12

>

M_B_OP1

Functionunit

FU FUnn Execution FU3TO

M_B_OP2

Constant V Vnnnnn Condition M_B_OP

>V33441

1

1. Any multibit operand can be entered here.2. Any multibit operand can be entered here with the exception of an input word.

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3. Operands

27


Constantdecimal

V Vnnnnn Execution V22312TO

M_B_OP2

Constanthexade-cimal

V$ V$nnnn Execution V$A1CTO

M_B_OP2

Constantsigned

V± V±nnnnn Execution V-40TO

M_B_OP2

Flag word FW FWn.3

(FWn)Condition FW3

<=

M_B_OP1

Flag word FW FWn.3

(FWn)Execution FW2

TOM_B_OP

2

Register R Rn Condition M_B_OP

>R3

1

Register R Rn Execution M_B_OPTOR1

1

Timerpreselect

TP TPn Condition TP0

<=

M_B_OP1

1. Any multibit operand can be entered here.2. Any multibit operand can be entered here with the exception of an input word.3. See note on page 28.

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3. Operands

28


Timerpreselect

TP TPn Execution TP2TO

M_B_OP2

Timer word TW TWn Condition TW2

< >

M_B_OP1

Timer word TW TWn Execution TW0TO

M_B_OP2

Counterpreselect

CP CPn ConditionCP28

>

M_B_OP1

Counterpreselect

CP CPn Execution CP31-M_B_OPM_B_OP

1

2

Counterword

CW CWn Condition CW19

>=

M_B_OP1

Counterword

CW CWn Execution1

2

CW7+M_B_OPM_B_OP

1. Any multibit operand can be entered here.2. Any multibit operand can be entered here with the exception of an input word.

Important: The syntax of the flag word varies with a greater orlesser number of operands depending on the type of controllerused. nn always starts at 0 and goes to the type-dependentmaximum value.

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3. Operands

29

3.5 RETENTIVE OPERANDS

Retentiveness is the property of an operand toretain its status even during a power failure.As operands are always stored in RAM, thisproperty is only possible if a buffer battery isinstalled, or in a flash memory.

In the case of Festo PLCs, all operands areretentive where it makes sense, i.e. all flags,registers, counters, counter preselects,counter words and timer words.

All outputs are generally volatile. For safetyreasons all outputs must not remain ON in theevent of a power failure.

In the event of power failure and battery fail-ure all operands (except outputs) must be ini-tialized by the application program, settingthem to the desired initial value (possibly withthe aid of an appropriate module to zero alloperands).

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3. Operands

30

Notes

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4. The structure of a ladder diagram program

31

Chapter 4

Structure of a Ladder diagram program

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32

Contents

4.1 NOTES .................................................33

4.2 WHAT IS A RUNGCOMPRISED OF?...............................34

4.3 CONDITIONAL ANDEXECUTIVE PART .............................37

4.4 HOW IS A RUNG PROCESSED? .....38Advantages of the process imagemethod ..................................................44Advantages of the directaccess method.....................................45

4.5 HOW FAST IS A CONTROLLER?....46

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33

4.1 NOTES

A Ladder diagram program consists ofRungs. Each rung has a minimum of onecontact set, and a maximum of 12 contacts inseries. Each rung also has at least one, andgenerally at least 6 rung sections.

Additionally up to 9 parallel branches can beinserted, resulting in a maximum of 10 con-tacts in parallel.

The parallel branches can be positioned any-where, except that they must not overlap.

Coils can also be configured in parallel, butthey must all have one common input. Arung can thus only send a single logical signalto all coil contacts.

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34

4.2 WHAT IS A RUNG COMPRISED OF?

In its simplest form the Ladder diagram is animage of the American circuit diagram. It issimilar to the German circuit diagram, but isalways read from left to right.First let's look at some terms:The Ladder diagram consists of rungs, parallelpaths, rung sections, contacts, boxes, coilsand parallel coils.

Fig. 4/1: The rung

A Box can be used to replace a contact or acoil. Boxes are used for functions that are dif-ficult or impossible to represent in the Ladderdiagram or circuit diagram, for example anarithmetic operation, like the addition of twonumbers.

Fig. 4/2: Adding two numbers

Important: A maximum of 5 boxes can beused in one rung.

+IW2V321R3

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35

Parallel branches can be used at any point inthe rung, as long as their connections do notcross. Parallel branches are called parallelcoils.

Fig. 4/3: Parallel branches and parallel coils

Parallel coil

Parallel branch

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36

The rungs displayed so far only contain op-erations, and therefore represent nothingmore than a logical linkage of binary elements.Each operation, that is each contact, coil andbox (but not each rung section) requires anoperand. If the operand is missing, the FSTsoftware will reject the program as containingerrors and will not load it into the controller.

The operand is written over the contact/coil.This is done with the aid of the function key (orfor FST software version 3.1 or later with themouse) activating the function "Enter oper-and".

In the case of boxes it is quite common fortwo, three or more operands to be entered.More on that later.

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37

4.3 CONDITIONAL AND EXECUTIVE PART

Like all Boolean or logic operations, the rungcan be divided into a conditional part and anexecutive part. The conditional part (in rungsection) contains the condition for a given ac-tion; the executive part (coils and parallel coils)contains the action to be carried out if thecondition is met.

This is the same in an electrical circuit dia-gram. An electrical "load" represents the ex-ecutive part of the current path. The contactsin series or parallel, with normally-open andnormally-closed contacts, represent the condi-tional part.

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38

4.4 HOW IS A RUNG PROCESSED?

The rungs are numbered. The numbering iscarried out automatically. For this reasonthere is a clear sequence of rungs. Beforeloading the ladder diagram program into thecontroller the program is translated into themachine code used by the controller. Therungs are translated consecutively in theirnumber sequence. Even within a rung the ma-chine code uses the sequence programmedby you. It follows that a second coil in a rungwill also appear second in the machine code.

In the case of the FPC 405, the second coil isalso switched second, with a delay measuredin microseconds. In the case of the FPC 100,IPC and FEC, the second coil is written assecond in the process image, and transmis-sion to the physical outputs takes place inde-pendent of the programmed sequence.

The entire program is then executed strictly insequence (as in every computer with onlyone processor). When powering up or startingwith the run/stop switch each controller beginsat the first program line. So when you are pro-gramming you always know which operationwill be executed first.

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39

This is utilized in particular when applying theso-called initialization flag. Initialization flagFI is a special one-bit operand which has thevalue logic 1 for the first cycle of a program.With the aid of FI it is possible to put any op-erand into the desired initial status for the pro-gram (initializing operands). This method isused to reset retentive operands after power-ing up, but also to set particular outputs to aninitial value (displays, for example, showing theoperating mode).The initialization flag FI has the value logic 1from the beginning of the program for one cycle.

Fig. 4/4: Interrogation of FI

The negated interrogation of FI is an existing1, which has the value logic 1 as long as theprogram is executed after the first cycle.

Fig. 4/5: Negated interrogation of FI

This treatment of the initialization flag FI is thesame for all Festo controllers programmed inLadder diagram.

FI O0.1

FI O0.1

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40

However, the internal processing of certainFesto controllers differ slightly:

The FPC 100, IPC and FEC controllers (astypical single processor system) use a proc-ess image for program execution. The proc-ess image represents the status of inputs andoutputs. Before processing the first rung thisprocess image is updated. During execution ofthe program the status of the inputs is neverread in, and the status of externally visible out-puts is not changed. (The process image isalso updated when jumping to an earlier part ofthe program. It is also updated before proc-essing the first rung of each Ladder diagramprogram. So, if you use a project with severalprograms, the process image is updated be-fore commencing the execution of each pro-gram.)

Fig. 4/6: Program execution with/without process image

Updating of processimage

Rung 1

Rung 2

Rung 3

Rung 4

Rung 1

Rung 2

Rung 3

Rung 4

FPC100 / IPC / FEC FPC 405

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41

The FPC 405 controller (as a typical multi-processor system) does not use a processimage. The status of an input is interrogatedimmediately following the input signal delay,when the input is interrogated in the program.An output signal is written to an output at ex-actly the time the appropriate command isexecuted in the program.

What does it mean in practice?

The following program could be written for anyFesto PLC:

Fig. 4/7: Program

Rung No. 1I0.1 O0.1

O0.1

O0.1

O0.1

O0.1

O0.1

O0.1

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42

The program does not make a lot of sense, asoutput O0.1 is simply switched on and offagain continually. In the case of a controllerwith process image - for example the FPC 100- the external output would not be switched onand off in this way. The output remains on ifthe input is logic 1 or off if the input is logic 0,because the last thing that happens in thiscommand before updating of the process im-age is setting the output (if the condition ismet).

On the other hand, a controller that accessesinputs and outputs directly will switch the exter-nal output on and off as programmed. This isnecessary, so that in an environment with mul-tiple processor modules, all modules have di-rect access to the inputs and outputs. In thecase of the FPC 405, you can see the rapidflashing of the outputs using an oscilloscope.In most cases you can also see that the outputlight-emitting diode appears less bright.

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43

The following program can also be executedby any Festo PLC:

Fig. 4/8: Program

Here an input is interrogated for logic 1 andlogic 0. A superfluous program, as a perma-nent 1 can be much more easily programmedwith NOP. At first glance it appears that thiscondition will always be met as each input canonly be logic 0 or logic 1.

However, this only applies for a controller withprocess image (FPC 100, IPC, FEC). Onlythen can you be sure that the logical status ofthe input cannot change between the two inter-rogations of the input.

In the case of the controllers with direct ac-cess to inputs (FPC 405) it is quite possiblethat the logical status of input I0.1 couldchange between the two interrogations. Thisdoes not happen very often, but in practicecannot be ignored.

I0.1

I0.1

O0.1

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44

Advantages of the process image

On the one hand the process image methodensures that inputs cannot change their logicalstatus during the program cycle.

Secondly, it is ensured that the outputs canonly adopt the logical status last programmed.This allows safety or checking routines to bewritten at the end of the program to pick upprogramming errors. (If such check routinesare absolutely necessary for controllers withdirect input and output access, they are pro-grammed with flags. Only at the end of theprogram are these flags written to the outputsas required by the check routines.)

And finally, program execution is much fasterwhen a process image is used. However,when creating the process image, the cyclictime of the program must be checked.

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45

Advantages of the direct access method

Direct access makes it possible to operateseveral processor modules in parallel, that isto use a multiprocessor system.

Furthermore, the direct access method en-sures that only the current status of an input isused. The cycle time does not need to take thetime for updating the process image into ac-count.

Finally, the rapid switching of outputs can beused for driving electronic peripherals (for ex-ample stepper motors, electronic counters,electronic displays, electronic multiplexers).

Which of the two methods is better for a spe-cific application will depend on a number ofcriteria. In case of doubt it is good to know:

FPC 100, IPC and FEC are single processorsystems and use the process image method.

FPC 405 is a multiprocessor system andworks with direct access to inputs and outputs.

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46

4.5 HOW FAST IS A CONTROLLER?

Each contact and each coil involve time.Therefore it follows that the cycle time of acontroller will increase with program length.This is the case with all modern PLCs.

In order to avoid excessively long cycle times,modern controllers offer the jump command.This allows unnecessary program parts to beskipped. This command is also available inLadder diagram for the Festo controllers.

The cycle times of controllers vary greatly. Inaddition, as the time taken to process variouscommands can vary greatly (an arithmetic op-eration takes longer than simply switching anoutput), it is difficult to make a global statementabout the cycle time of a controller. Brochurestatements such as "6 milliseconds per 1000statements" look good but have no value, asdifferent statements require a different lengthof time for execution. For this reason the ex-ample programs in Appendix A contain simpleprograms with which you can measure theactual cycle time, the longest and shortest cy-cle time of the program and the reaction time(that is cycle time and input signal delay). Useone of these programs if you want to checkthe cycle time for a specific application.

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5. Overview of operations

47

Chapter 5

Operations - an overview

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48

ContentsARITHMETIC/LOGIC BOX ..........................50MODULE........................................................50SWAP .............................................................50FUNCTION MODULE...................................50INVERTING....................................................50CREATING COMPLEMENT ........................50LOAD TO .......................................................50LOGIC ............................................................51Exclusive OR (EXOR) ...................................51Exclusive OR (EXOR) with 3 outputs............51Exclusive OR (EXOR) with words.................51Identity.............................................................52NOT (at output) ..............................................52NOT (at input).................................................52OR ...............................................................53OR with words ................................................53AND ...............................................................53AND with words..............................................53NOP ...............................................................53ARITHMETIC FUNCTIONSAdding.............................................................54Dividing ...........................................................54Multiplying .......................................................54Subtracting......................................................54ROTATINGTo left..............................................................54To right............................................................54SHIFTINGTo left..............................................................54To right............................................................54LATCHING (memory) ...................................55

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49

JUMPING to a flag .......................................55ENTERING a jump destination .................55COILS.............................................................55RESET (delete)..............................................55SET ...............................................................55Assignment.....................................................55Negated assignment......................................55COMPARATORS..........................................55Equal55Greater than ...................................................55Greater than or equal.....................................56Less than........................................................56Less than or equal .........................................56Unequal...........................................................56NUMBERSConversion BCD to BINARY.........................56Conversion BINARY to BCD.........................56COUNTINGInterrogated preselect achieved? .................57Interrogated preselect not achieved? ...........57Decrement......................................................57Increment........................................................57Set counter .....................................................57TIMEStart switch-off delay .....................................57Switch-off delay time expired? ......................57Switch-off delay time running?.......................58Start switch-on delay......................................58Switch-on delay time expired?.......................58Switch-on delay time running?.......................58Start pulse timer .............................................58Pulse timer running? ......................................58

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50

Operation Symbol Function

Arithmetic/logicbox

Arithm./logic

This box allows arithmetic or logicword operations to be carried out.

ModuleCMP 0Module

Call user modules or standardmodules

Swap FW4SWAP

R3

Swap the high and low byte of theupper word (here FW4) and writethem to the lower word (here R3).

Functionmodule CFM 0

Module

Call Function module supplied byFesto.

Invert R2INVR2

Invert every bit of the upper word(here R2) individually and write theresult to the lower word (here R2).

Complement R2CPLR2

Write the two's complement of theupper word (here R2) (i.e. changesign).

LOAD TO V12TO

CW4

Load the value from the upper word(here 12) into the lower word (hereCW4).

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51


Logic:Exclusive

OR

I0.1

I0.1

I0.2

I0.2

Exclusive OR logicLogic operation with 2 inputs

Logic:Exclusive

OR with

3 inputs

I0.1

I0.1

I0.1

I0.2 I0.3

I0.3

I0.3

I0.2

I0.2

Exclusive OR logicLogic operation with 3 inputs

Logic:Exclusive

OR with

words

R2IW0FW1

X

EXOR each individual bit of theupper word (here R2) with each bitof the middle word (here IW0) andwrite the result to the lower word(here FW1).

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52

Operation Function

Logic:Identity

Direct transfer of the logic status of a bit to the output bit

I0.1 O0.1

Operation Function

Logic:NOT

(at output)

Negation of the output signals

I0.1 O0.1

Operation Function

Logic:NOT

(at input)

Negation of the input signals

I0.1 O0.1

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53


Logic:OR

I0.1

I0.2

I0.3

OR connection of binary signals

Logic:OR with

words

R2IW0FW1

v

Bitwise OR connection of twowords

Logic:AND

I0.1 I0.2 Logical AND connection of binarysignals

Logic:AND with

words

R2IW0FW1

v

Logical AND connection of theindividual bits of two words

NOP NOP Non operationProduces permanent 1.The condition NOP is alwaysfulfilled.

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54


Arithmetic:Addition

CW5V12CW6

+

The addition of two whole numbersand storing the result

Arithmetic:Division

CW5V2

CW5

/

DividingIgnoring places after decimal point

Arithmetic:Multiplication

CW5CW1R4

*

Multiplies two whole numbers(places beyond decimal point areignored)

Arithmetic:Subtraction

V244R4

TW5_

Subtract two whole numbers

Rotation:left

OW4ROLOW4

Rotates all word bits to the left

Rotation:right

OW4ROROW4

Rotates all word bits to the right

Shift:left

FW2SHLOW0

Shifts the bits of a word one placeto the left

Shift:right

FW2SHROW0

Shifts the bits of a word one placeto the right

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55


Jump tolabel

Destination>>

Jump to label clearly indicated atsome point in the program (herethe label is DESTINATION).

Jumpdestination

Destination

L

Enter label that can be jumped to

Coils:RESET

O0.1

R

Resetting,i.e. erasing a stored bit

Coils:SET

O0.1

S

Setting a stored bit

Coils:Assignment

O3.2 The output bit must always have thesame logical status as the result ofthe previous condition.

Coils:Assignment

negated

O3.2 The output bit must always have thenegated logical status of the resultof the previous condition.

Comparison:Equal

CW7

=CW12

The rung signal is 1, if both wordsare identical.

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Comparison:Greater

CW3

>

V3467

The rung carries a logic 1 if theupper word (here CW3) is greaterthan the lower word (here the value3467).

Comparison:Greater/

equal

CW3

>=

V34777

The rung carries a logic 1 if theupper word (here CW3) is greaterthan or equal to the lower word(here the value 34777).

Comparison:Less

IW4

<

FW12

The rung carries a logic 1 if theupper word (here IW4) is less thanthe lower word (here FW12).

Comparison:Less/

equal

TW5

<=

V332

The rung carries a logic 1 if theupper word (here TW5) is equal toor less than the lower word (herethe value 332).

Comparison:Unequal

CW4

<>

OW1

The rung carries a logic 1 if thetwo words (here CW4 and OW1)are unequal.

Numbers:CONVERT

BCD

TO BINARY

FW4DEBOW3

The upper word (here FW4) isinterpreted as a decimal numberand converted into binary. Theresult is written to the lower oper-and (here OW3).

Numbers:CONVERT

BINARY

TO BCD

FW4BID

OW3

The upper word (here FW4) isinterpreted as binary and con-verted into BCD-code. The result iswritten into the lower word (hereOW3).

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57


Counting:Preselect

interrogation

achieved?

C4 Rung is logic 1, if the counter(here No. 4) has reached or ex-ceeded the preselect of has not yetbeen started.

Counting:Preselect

interrogation

not achieved?

C4 Rung is logic 1, if the counter(here No. 4) has not reached thepreselect.

Counting:Decrement

CW41DEC

The upper word (here CW4) isdecremented by 1.

Counting;Increment

R51INC

The upper word (here R5) is in-cremented by 1.

Counting:Set

counter

C47663

Counter

The counter preselect (here for No.4) is set to the value indicated(here 7663), and the counter bit(here C4) becomes logic 1.

Time:Start

switch-off

delay

TOFF30200sTimer

The timer (here No. 30) is set as adelay timer with the duration indi-cated (here 200 seconds).

Time:Switch-off

delay

Time expired?

TOFF30 Rung is logic 1, if the preselecttime has expired.

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Time:Switch-off

delay

Time running?

TOFF30 The rung is logic 1, if the preselecttime has not yet expired.

Time:Start

switch-on

delay

TON53.4s

Timer

The timer (here No. 5) is set as aswitch-on delay with the durationindicated (here 3.4 seconds).

Time:Switch-on

delay

Time expired?

TON5 Rung is logic 1, if the preselecttime has expired.

Time:Switch-on

delay

Time running

TON5 Rung is logic 1, if the preselecttime has not yet expired.

Time:Start

pulse timer

T04s

Timer

The timer (here No. 0) is started asa pulse timer with the preselectindicated (here 4 seconds).

Time:Pulse timer

Time expired?

T0 Rung is logic 1, if the preselecttime has expired or the timer hasnot been started.

Time:Pulse timer

Time running

T0 Rung is logic 1, if the preselecttime has not yet expired.

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6. Operations in detail

59

Chapter 6

The operations in detail

Examples for reference

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60

ContentsARITHMETIC/LOGIC BOX ..........................62MODULE........................................................65SWAP .............................................................67FUNCTION MODULE...................................69INVERTING....................................................71CREATING COMPLEMENT ........................73LOAD TO .......................................................75LOGICExclusive OR (EXOR) ...................................76Exclusive OR (EXOR) with 3 outputs............77Exclusive OR (EXOR) with words.................79Identity.............................................................81NOT (at output) ..............................................82NOT (at input).................................................83OR ...............................................................84OR with words ................................................85AND ...............................................................87AND with words..............................................88NOP ...............................................................90ARITHMETIC FUNCTIONSAdding.............................................................91Dividing ...........................................................93Multiplying .......................................................95Subtracting......................................................97ROTATINGTo left..............................................................99To right..........................................................101SHIFTINGTo left............................................................103To right..........................................................105LATCHING (memory) .................................107

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61

JUMPING to a flag .....................................110ENTERING a jump destination ...............111COILSRESET (delete)............................................113SET .............................................................114Assignment...................................................115Negated assignment....................................116COMPARATORSEqual .............................................................117Greater than .................................................119Greater than or equal...................................121Less than......................................................123Less than or equal .......................................125Unequal.........................................................127NUMBERSConversion BCD to BINARY.......................129Conversion BINARY to BCD.......................131COUNTINGInterrogated preselect achieved? ...............133Interrogated preselect not achieved? .........135Decrement....................................................137Increment......................................................138Set counter ...................................................139TIMEStart pulse timer ...........................................141Interrogate pulse timer.................................142

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62

The Arithmetic/Logic Box

The Arithmetic/Logic Box is only used in theexecutive part. It allows coherent programmingof word operations in contrast to the multi-bitboxes which only allow one command each.

The Arithmetic/Logic Box is indicated in therung as a box. In the printout the contents ofthe box are printed immediately following therung containing the Arithmetic/Logic Box.

During programming you can examine thecontents of the box by positioning the cursoron the box and pressing the <Enter> key. Thecontents of the box are then displayed on thescreen. You can cancel the display of contentsby pressing the <ESC> or <Enter> key.

Independent of the number of command lineswithin the box, the Arithmetic/Logic Box is onlyregarded as a single box. Up to 16 lines canbe entered into the Arithmetic/Logic Box. Asonly 5 boxes can be used in a rung, only 4other boxes can be used in addition to anArithmetic/Logic Box.

Within the Arithmetic/Logic Box, multi-bitcommands are entered as text and thereforenot always the same as the commands other-wise entered in Ladder diagram boxes. In ad-dition, there is a space for comments belowthe Arithmetic/Logic Box.

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63

Each field of the Arithmetic/Logic Box mayonly contain one entry.

Example:

Fig. 6/1: Logic, EXOR using words

The same operation in an Arithmetic/LogicBox has the following structure:

Fig. 6/2: Logic, EXOR with words in arithmetic box

Rung No. 66

Conditionx IW0

R2

FW1

Rung No. 67

ConditionArithm./logic

Arithmetic/logic

LOADEXORTO

R2IW0FW1

Contents of Register 2EXOR with Input word 0Write result to Flag word 1

Boxes in Rung No. 67

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64

Figures 6/1 and 6/2 show an EXOR operationon two words. 6/1 in a multi-bit box and 6/2 inthe Arithmetic/Logic Box. (For details of thisoperation see "Exclusive OR with words".) Inthe Arithmetic/Logic Box the multi-bit operationbegins with the LOAD command. This indi-cates that the entered multi-bit operand isloaded into the processor module's multi-bitaccumulator. The required operation is carriedout in this multi-bit accumulator. The result isloaded from the multi-bit accumulator into anyother multi-bit operand of your choice(command: TO). In the multi-bit box, EXOR isindicated by an x. In the Arithmetic/Logic BoxEXOR is indicated by EXOR.

The result of the operation in the multi-bit boxand in the Arithmetic/Logic Box is completelyidentical.

The Arithmetic/Logic Box is better when youwant to use several multi-bit operations in asingle rung, and/or when you want to entercomments.

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65

MODULE

Modules (also called program modules) areMODULES created by the user that can becalled up at any point in a Ladder diagram pro-gram. Modules must be clearly identified as amodule when calling them from the Ladderdiagram editor.

These modules or program MODULES arenothing more than subroutines. Subroutinesallow repetitive procedures in a program to bewritten once but called up many times.

The individual controllers support the followingnumber of modules:

• FPC 100B/AF: 8 program modules

• • IPC: 100 program modules

• • FEC: 100 program modules

• FPC 405: 32 program modules (The pro-gram modules for the FPC 405 may only bewritten in assembler if they are to be calledfrom the Ladder diagram program.)

For example, a text display may be connectedto a controller. The transmission of data to thistext display can be programmed by means of aprogram module.

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66

The contents of a text display need to be up-dated from various parts of the program: fromthe automatic program as well as from themanual program. An error message changesthe text, as does an operator entry.

At this point in your program you call theMODULE that handles data transmission tothe text display.

This makes the program shorter and easier toread.

Fig. 6/3: Module

CPM0Module

Rung No. 1

Condition

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67

SWAP

All operands in the Festo controllers arestructured as 16-bit words. Each word con-sists of two 8-bit bytes, the low byte (right) andthe high byte (left).

Sometimes it may be necessary to swap thetwo bytes of a word. This can be done with theLadder diagram command SWAP.

The command SWAP changes:

0 1 1 1 0 1 1 0 0 1 1 0 0 1 1 1

to:

0 1 1 0 0 1 1 1 0 1 1 1 0 1 1 0

In Ladder diagram SWAP is programmed witha box:

Fig. 6/4: SWAP bytes

Rung No. 1

ConditionSWAPFW3

FW4Rung No. 2

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68

The same operation can be programmed inthe Arithmetic/Logic Box:

Fig. 6/5: SWAP bytes in arithmetic box

Rung No. 2

ConditionArithm./logic

Arithmetic/logic

LOADSWAPTO

FW3

FW4

Load contents of Flag word 3SWAP BYTESWrite result to Flag word 4

Boxes in Rung No. 2

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69

FUNCTION MODULE

Function modules – as opposed to programmodules – are sub-programs pre-programmedinto the controller by Festo. So these are sub-routines in the accepted sense, or to be moreprecise procedures, as generally used inhigher programming languages. These sub-routines are supplied with the controller or canbe ordered separately from Festo.

One example of a function module (CFM) isfor opening a network for the FPC 405. Func-tion module CFM 70 is used for this purpose.The station number of the calling processormodule and the desired timeout are passed toCFM 70 as parameters. CFM 70 leaves themessage in function unit 32 indicating whethernetwork setup was successful or not.

Fig. 6/6: Function module CFM 70

Rung No. 1

ConditionCFM 70Module

CFM 70 / Initialize network

V12 120 ms timeout

Boxes in Rung No. 1

Network connection for this processor module is established

V1 Station 1 of the network

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70

Another typical function module is CFM 0 forthe FPC 100B/AF. This function module facili-tates deletion of all retentive operands, as re-quired for many applications.

The following application is typical:

Fig. 6/7: Function module CFM 0

The function modules offered depend on thecontroller type. For details please see thesystem manual for the appropriate controllertype.

Rung No. 1

ConditionCFM 0Module

CFM 0 / Delete function units

Boxes in Rung No. 1

Delete retentive function units

V3 Delete timers and counters

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71

INVERTING

INVERT is an operation for use with multi-bitoperands. INVERT negates each bit of aword.

Fig. 6/8: Inverting

The same result can be achieved by using IN-VERT in the Arithmetic/Logic Box:

Fig. 6/9: Inverting in arithmetic box

In this example register 2 is inverted and theresult is written back to register 2.

Rung No. 58

ConditionINVR2

R2

Rung No. 59

ConditionArithm.&Logic

Arithmetic/logic


LOAD Contents of Register 2INVTO

R2

R2INVERTWrite result to Register 2

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72

30311ñ10, 3031110 or 766716

0 11

1 1 0 1 1 0 0 1 1 0 0 1 1 1

↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓

0 1 1 1 0 1 1 0 0 1 1 0 0 1 1 1

becomes -30312ñ10, 3522410 or 899816.

Any multi-bit operand can be entered as theoperand to be inverted (the upper operand inthe box). The result can be returned to anymulti-bit operand (the lower operand in thebox) with the exception of input words.

If the operand at the top is not the same as theoperand at the bottom, the contents of the up-per operand are not changed.

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73

COMPLEMENT

COMPLEMENT is an operation for use withmulti-bit operands.

The COMPLEMENT operation is used tochange the sign of a number. The value -5 be-comes 5, the value 2734 becomes -2734. TheCOMPLEMENT operation only makes senseif you are working with signed numbers.

Fig. 6/10: Creating the complement

The same function is programmed in the

Arithmetic/Logic Box as follows:

Fig. 6/11: Creating the complement in arithmetic box

Rung No. 56

ConditionCPLR2

OW4

Rung No. 57


Arithmetic/logic


LOAD Contents of Register 2CPLTO

R2

OW4COMPLEMENTWrite result to Output word 4

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74

In this example the COMPLEMENT of register2 is written to output word 4 (register 2 re-mains unchanged).

30311ñ10, 3031110 or 766716

0 1 1 1 0 1 1 0 0 1 1 0 0 1 1 1

↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓

1 0 0 0 1 0 0 1 1 0 0 1 1 0 0 0

becomes -30311ñ10, 3522510 or 899916.

The COMPLEMENT operation can be usedfor all multi-bit operands. The destination(lower operand) can be any multi-bit operandwith the exception of an input word. If theupper operand (source) and lower operand(destination) are different, the upper operandis left unchanged.

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75

LOAD TO

LOAD TO is an operation for use with multi-bitoperands.

LOAD TO allows the contents of a multi-bitoperand to be loaded into another multi-bit op-erand. The source can be any multi-bit oper-and, the destination can also be any multi-bitoperand with the exception of an inputword.

Fig. 6/12: Load to

The identical function is programmed using theArithmetic/Logic Box as follows:

Fig. 6/13: Load to (Arithmetic/Logic Box)

In this example the decimal value 12 is trans-ferred to counter word 4.

Rung No. 2

ConditionT0V12

CW4

Rung No. 3


Arithmetic/logic

Boxes in Rung No. 3

LOAD Value 12 (decimal)TO

V12Write to counter word 4CW4

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76

LOGIC: EXCLUSIVE OR (EXOR)

EXOR is one of the common logic operations.The logic module is shown thus:

Fig. 6/14: Logic module

The truth table for EXOR is as follows:

I1 I2 O1

0011

0101

0110

Ladder diagram does not offer an independentoperation for EXOR. The EXOR must beconstructed using a combination of paralleland series circuits and negations.

Fig. 6/15: LOGIC: Exclusive OR

= 1 O1I1

I2

Rung No. 4

I0.1 I0.2

I0.1 I0.2

Execution

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77

LOGIC: EXCLUSIVE OR (EXOR) with 3 inputs

There are different views on the truth table foran EXOR with three inputs. In many cases –particularly when programming with statementlist – the EXOR can only be used with a maxi-mum of two inputs.

Here the EXOR with three inputs is shown forthe sake of completeness and to demonstratehow you can expand the logical function ofEXOR (and any other logical function) to meetyour requirements.

The logic element for EXOR with three inputsis shown thus:

Fig. 6/16: Logic module

The truth table can also be expanded:

I1 I2 I3 O1

00001111

00110011

01010101

01101000

= 1 O1I1

I3I2

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78

In Ladder diagram, this type of EXOR is pro-grammed as follows:

Fig. 6/17: LOGIC: Exclusive OR

Rung No. 4

I0.1

I0.1

I0.2

I0.2

I0.3

I0.3

I0.1 I0.2 I0.3

Execution

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79

LOGIC: EXCLUSIVE OR (EXOR) with words

The EXOR that can be used with multi-bit op-erands is used in the executive part of theLadder diagram. Thus, this EXOR does notrepresent a condition for an action, but is onlycalled if the condition is met (the rung evalu-ated to logic 1).

Fig. 6/18: LOGIC: Exclusive OR using words

This operation can be programmed identicallywith the Arithmetic/Logic Box as follows:

Fig. 6/19: OR with words in arithmetic box

Rung No. 66

ConditionIW0R2

FW1X

Rung No. 67


Arithmetic/logic


LOAD Contents of Register 2EXOR

R2EXOR with Input word 0IW0

TO FW1 Write result to Flag word 1

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80

In this example an EXOR operation is carriedout on each of the bits from register 2 with thecorresponding bits of input word 0. This iscarried out 16 times, each time with two inputs.The result is written to flag word 1, so thatregister 2 and input word 0 remain unchanged.

Register 2:

0 1 1 1 0 1 1 0 0 1 1 0 0 1 1 1

X X X X X X X X X X X X X X X X

EXOR input word 0

1 1 1 0 1 0 0 0 1 1 0 0 0 0 0 0

↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓

becomes:

1 0 0 1 1 1 1 0 1 0 1 0 0 1 1 1

and is written to flag word 1.

The EXOR can be used for any multi-bit oper-ands and the result can be written to any multi-bit operands with the exception of an inputword.

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81

LOGIC: IDENTITY1

The IDENTITY (yes function) is one of thebasic logic operations. It has one input andone output (like negation).

The logic symbol for IDENTITY is shown thus:

Fig. 6/20: Logic symbol for IDENTITY

The truth table for IDENTITY is as follows:

I1 O1

01

01

IDENTITY is programmed in Ladder diagramas follows:

Fig. 6/21: LOGIC: IDENTITY

1. Logic: Identity with words, see under: LOAD TO

1I1 O1

O0.1I0.1

Rung No. 6

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82

LOGIC: NOT1 (at output)

The NOT or negation is the inversion of iden-tity. The logic signal of an input is negated. InLadder diagram this negation can be used forthe input or the output. For this reason the twomethods are described separately. The logicsymbol for the NOT function (at output) isshown thus:

Fig. 6/22: Logic symbol for NOT function

The truth table for the NOT function is as fol-lows:

I1 O1

01

10

The NOT function is programmed in Ladderdiagram as follows:

Fig. 6/23: NOT (at output)

The slant (oblique stroke) within the coil

brackets indicates negation.

1I1 O1

O0.1I0.1

Rung No. 6

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83

LOGIC: NOT1 (at input)

NOT or negation is the inverse of identity.The logic signal of an input is negated.

In Ladder diagram this negation can be usedfor the input or the output. For this reason thetwo methods are described separately here.The logic symbol for a NOT function (at input)is shown thus:

Fig. 6/24: Logic symbol for NOT function

The truth table for the NOT function is as fol-lows:

I1 O1

01

10

The NOT function is programmed in Ladderdiagram as follows:

Fig. 6/25: LOGIC: NOT (at input)

The slant (oblique stroke) in the contact sym-bol indicates negation.

1. Logic: NOT with words, see under: INVERT

1I1 O1

O0.1I0.1

Rung No. 6

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84

LOGIC: OR

OR is one of the basic logic operations (likeAND and NOT).

The logic symbol for OR is shown thus:

Fig. 6/26: Logic symbol OR

The truth table for the OR function is as fol-lows:

I1 I2 O1

0011

0101

0111

In Ladder diagram OR is represented by a

parallel branch:

Fig. 6/27: LOGIC: OR

O1I1

I2> 1_

Rung No. 4

I0.1

I0.2

Execution

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85

LOGIC: OR with words

The OR operation can be used for multi-bitoperands. In this case it is not a condition forthe command in the executive part.

When carrying out an OR operation usingwords, we speak of "masking". If for exampleyou want the fifth bit of a word (counting fromthe least significant bit) to have the value logic1 you OR this word with another word in whichonly the fifth bit has the value logic 1. The re-sulting word contains all the bits of the outputword and guarantees that the fifth bit has thevalue 1.

Register 2:

0 1 1 1 0 1 1 0 0 1 1 0 0 1 1 1

vv

v v v v v v v v v v v v v v v

OR value 16

0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0

↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓

becomes:

0 1 1 1 0 1 1 0 0 1 1 1 0 1 1 1


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86

In Ladder diagram you can OR-mask in themulti-bit box or in the Arithmetic/Logic Box:

Fig. 6/28: LOGIC: OR using words

The same function can be programmed withthe Arithmetic/Logic Box:

Fig. 6/29: LOGIC: OR using words in arithmetic box

Masking does not have the same significancefor programmable logic controllers as it doesin other areas of computing. You could simplyset the fifth bit of the word by loading the wordinto a flag or output word. There you couldchange the fifth bit to logic 1 using the setcommand and, if required, load the word back.

You can OR any two multi-bit operands. Thedestination for the result can be any multi-bitoperand with the exception of an inputword.

Rung No. 64

ConditionV16R2

FW1v

Rung No. 65


Arithmetic/logic


LOAD Contents of Register 2OR

R2OR with the value 16V16


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87

LOGIC: AND

AND belongs to the basic logic operations(like OR and NOT).

The logic symbol for AND is as follows (shown

here with three inputs):

Fig. 6/30: Logic symbol AND

The truth table for AND is as follows:

I1 I2 I3 O1

00001111

00110011

01010101

00000001

In Ladder diagram AND is represented by se-

ries connection:

Fig. 6/31: LOGIC: AND

O1I1

I3I2 &

Rung No. 10

I0.1 I0.2 I0.3I0.3 Execution

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88

LOGIC: AND with words

The AND operation can also be used for multi-bit operands. In this case it is not a conditionbut a command in the executive part.

When carrying out an AND operation withwords, we speak of "masking". For example, ifyou want to establish whether the fifth bit of aword (counting from the least significant bit)has the value logic 1, you AND this word withanother word in which only the fifth bit has thevalue logic 1. If the result is 0, the fifth bit in theword you are testing is 0. If the result isgreater than 0, the fifth bit has the value 1.

Register 2:

0 1 1 1 0 1 1 0 0 1 1 0 0 1 1 1

^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^

AND value 16

0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0

↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓

becomes:

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0


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89

In Ladder diagram you can AND in the multi-bitbox or in the Arithmetic/Logic Box:

Fig. 6/32: LOGIC: AND with words

The same function can be programmed withthe Arithmetic/Logic Box:

Fig. 6/33: LOGIC: AND with words in arithmetic box

Masking does not have the same significancefor programmable logic controllers as it doesin other areas of computing. You could simplyinterrogate the fifth bit of a word by loading theword into a flag or output word. From a flag oroutput word you can interrogate the fifth bit inbinary as Fx.4 or Ox.4. You can AND anymulti-bit operands. The destination for the re-sult can be any multi-bit operand with the ex-ception of an input word.

Rung No. 63

ConditionV16R2

FW1^

Rung No. 63


Arithmetic/logic


LOAD Load contents of Register 2AND

R2AND-mask with value 16V16


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90

NOP

NOP is the null operation, that is, an opera-tion that "does nothing". All programming lan-guages have null operations. In Ladder dia-gram, NOP can be used as an operand desig-nation or contact but not for coils. If NOP isused, this contact is always switched through,which has the same effect as the negated in-terrogation of the initialization flag FI after thefirst cycle of the program.

Fig. 6/34: NOP

In this example, output O0.1 is alwaysswitched through.

If NOP is used, this means that the rung is al-ways active and that signal-edge recognition isswitched off. In the following example countingtakes place for each cycle, not only for the 0-

1 signal edge of the condition:

Fig. 6/35: NOP

O0.1NOP

Rung No. 6

CW3NOP

Rung No. 12

CP

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91

Arithmetic function: ADDING

The four basic arithmetic functions ADDING,subtracting, multiplying and dividing are avail-able for all Festo controllers. These arithmeticfunctions can also be used in Ladder diagram.

In the Festo controller, these arithmetic func-tions are always used for whole, signednumbers in the range ñ32767.

The overflow cannot be interrogated.

If you use these numbers outside this range,no error message is given. Overflow is simplytruncated (not rounded).

The FPC 405 also allows the use of functionmodule 20 to program arithmetic operationswith an overflow that can be interrogated.

ADDITION can be programmed as follows:

Fig. 6/36: Arithmetic function: Adding in the arithmetic box

Rung No. 12

ConditionV12CW5

CW6+

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92

The same operation with the same functioncan be programmed with the Arithmetic/LogicBox as follows:

Fig. 6/37: Arithmetic: Adding in the arithmetic box

Please note that you always need at leastthree operands for an arithmetic operation.The first two operands are added and the re-sult is written to the third operand. The con-tents of the first operands (or other operandsincluded with arithmetic functions) are notchanged, if neither of these operands is givenin the result field. Any multi-bit operand can beused as a source; any multi-bit operand withthe exception of an input word may beused as a destination.

Rung No. 13


Arithmetic/logic


LOAD Contents of Counter word 5+

CW5Add value 12V12

TO CW6 Write result to counter word 6

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93

Arithmetic function: DIVIDING

The four basic arithmetic functions adding,subtracting, multiplying and DIVIDING areavailable for all Festo controllers. Thesearithmetic functions can also be used in Lad-der diagram.

In the Festo controller, these arithmetic func-tions are always used for whole, signednumbers in the range ñ32767.The overflow cannot be interrogated.If you use these numbers outside this range,no error message is given. Overflow is simplytruncated (not rounded).The FPC 405 also allows the use of functionmodule 20 to program arithmetic operationswith an overflow that can be interrogated.

DIVISION can be programmed as follows:

Fig. 6/38: Arithmetic function: Dividing

Rung No. 14

ConditionV2CW5

CW5/

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94


Fig. 6/39: Arithmetic function: Dividing in the arithmetic box

Please note that you always need at leastthree operands for an arithmetic operation.The first two operands are divided and the re-sult is written to the third operand. The con-tents of the first operands (or other operandsincluded with arithmetic functions) are notchanged, if neither of these operands is givenin the result field. Any multi-bit operand can beused as a source; any multi-bit operand withthe exception of an input word may beused as a destination.

Rung No. 15


Arithmetic/logic


LOAD Contents of Counter word 5/

CW5Divide by 2V2

TO CW5 Write result to counter word 5

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95

Arithmetic function: MULTIPLYING

The four basic arithmetic functions adding,subtracting, MULTIPLYING and dividing areavailable for all Festo controllers. Thesearithmetic functions can also be used in Lad-der diagram.





MULTIPLYING can be programmed as fol-lows:

Fig. 6/40: Arithmetic function: Multiplying

Rung No. 16

ConditionCW1CW5

R4*

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96


Fig. 6/41: Arithmetic function: Multiplying in the arithmetic box

Please note that you always need at leastthree operands for an arithmetic operation.The first two operands are multiplied and theresult is written to the third operand. The con-tents of the first operands (or other operandsincluded with arithmetic functions) are notchanged, if neither of these operands is givenin the result field. Any multi-bit operand can beused as a source; any multi-bit operand withthe exception of an input word may beused as a destination.

Rung No. 17


Arithmetic/logic


LOAD Contents of Counter word 5*

CW5Multiply by contents of Counter word 1CW1

TO R4 Write result to Register 4

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97

Arithmetic function: SUBTRACTING

The four basic arithmetic functions adding,SUBTRACTING, multiplying and dividing areavailable for all Festo controllers. Thesearithmetic functions can also be used in Lad-der diagram.





SUBTRACTING can be programmed as fol-

lows:

Fig. 6/42: Arithmetic function: Subtracting

Rung No. 18

ConditionR4

V244

TW5*

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98


Fig. 6/43: Arithmetic function: Subtracting in the arithmetic box

Please note that you always need at leastthree operands for an arithmetic operation.The first two operands are subtracted and theresult is written to the third operand. The con-tents of the first operands (or other operandsincluded with arithmetic functions) are notchanged, if neither of these operands is givenin the result field. Any multi-bit operand can beused as a source; any multi-bit operand withthe exception of an input word may beused as a destination.

Rung No. 19


Arithmetic/logic


LOAD Value 244-

V244Subtract contents of Register 4R4

TO TW5 Write result to Timer word 5

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99

ROTATE LEFT

ROTATE is one of the commands that shiftsthe individual bits of a word. In contrast to shift,ROTATE ensures that no bits are lost. The bitpushed off one end of the word is inserted atthe other end. So if a 16-bit word is rotated 16times, it returns to its original value.

In the case of ROTATE LEFT (ROL) the bitsare shifted left (in the Festo controllers all 16bits are always shifted). The most significantbit (extreme left) is inserted on the extremeright as the least significant bit.

0 1 1 1 0 1 1 0 0 1 1 0 0 1 1 1ROL

1 1 1 0 1 1 0 0 1 1 0 0 1 1 1 0

ROTATE LEFT is programmed in Ladder dia-gram as follows:

Fig. 6/44: Rotate left

Rung No. 20

ConditionROLOW4

OW4

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100

The same operation programmed with theArithmetic/Logic Box looks like this:

Fig. 6/45: Rotate left in arithmetic box

The ROTATE operation can be used for anymulti-bit operand. The result can be written toany multi-bit operand except an input word.

Rung No. 21


Arithmetic/logic


LOAD Contents of Output word 4ROL

OW4ROTATE LEFT

TO OW4 Write result to Output word 4

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101

ROTATE RIGHT

ROTATE is one of the commands that shiftsthe individual bits of a word. In contrast to shift,ROTATE ensures that no bits are lost. The bitpushed off one end of the word is inserted atthe other end. So if a 16-bit word is rotated 16times, it returns to its original value.

In the case of ROTATE RIGHT (ROR) the bitsare shifted to the right (in the Festo controllerall 16 bits are always shifted). The least sig-nificant bit (extreme right) is inserted on theextreme left as the most significant bit.

0 1 1 1 0 1 1 0 0 1 1 0 0 1 1 1ROR

1 1 1 0 1 1 0 0 1 1 0 0 1 1 1 0

ROTATE RIGHT is programmed in Ladderdiagram as follows:

Fig. 6/46: Rotate right

Rung No. 22

ConditionROROW4

OW4

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102


Fig. 6/47: Rotate right in arithmetic box

The ROTATE operation can be used for anymulti-bit operand. The result can be written toany multi-bit operand except an input word.

Rung No. 23


Arithmetic/logic


LOAD Contents of Output word 4ROR

OW4ROTATE RIGHT


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103

SHIFT LEFT

SHIFT is one of the commands that allows theindividual bits of a word to be shifted.In contrast to rotate, SHIFT shifts one bit offthe end of the word – this bit is lost. A 0 is in-serted at the other end of the word. If a 16-bitword is shifted 16 times, all bits are set to 0.In the FPC 405 the bit shifted out can be inter-rogated with the local flag FI7.

SHIFT LEFT (SHL) shifts the bits to the left (inthe Festo controller all 16 bits are alwaysshifted). The most significant bit (extreme left)is shifted out, and a 0 is inserted at the ex-treme right.

0 1 1 1 0 1 1 0 0 1 1 0 0 1 1 1SHL

1 1 1 0 1 1 0 0 1 1 0 0 1 1 1 0

In Ladder diagram SHIFT LEFT is pro-grammed as follows:

Fig. 6/48: Shift left

Rung No. 24

ConditionSHLFW2

OW0

0

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104


Fig. 6/49: Shift left in arithmetic box

The SHIFT operation can be used to changeany multi-bit operand. The result can be writtento any multi-bit operand except an inputword.

Rung No. 25


Arithmetic/logic


LOAD Load contents of Flag word 2SHL

FW2SHIFT LEFT


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105

SHIFT RIGHT

SHIFT is one of the commands that allows theindividual bits of a word to be shifted.In contrast to rotate, SHIFT shifts one bit offthe end of the word – this bit is lost. A 0 is in-serted at the other end of the word. If a 16-bitword is shifted 16 times, all bits are set to 0.In the FPC 405 the bit shifted out can be inter-rogated with the local flag FI7.

SHIFT RIGHT (SHR) shifts the bits to the right(in the Festo controller all 16 bits are alwaysshifted). The least significant bit (extremeright) is shifted out, and a 0 is inserted at theextreme left.

0 1 1 1 0 1 1 0 0 1 1 0 0 1 1 1SHR

0 0 1 1 1 0 1 1 0 0 1 1 0 0 1 1

In Ladder diagram SHIFT RIGHT is pro-grammed as follows:

Fig. 6/50: Shift right

Rung No. 26

ConditionSHRFW2

OW0

0

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106


Fig. 6/51: Shift right in arithmetic box

The SHIFT operation can be used to changeany multi-bit operand. The result can be writtento any multi-bit operand except an inputword.

Rung No. 27


Arithmetic/logic


LOAD Load contents of Flag word 2SHR

FW2SHIFT RIGHT


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107

LATCH (memory)

The LATCH is the electrician's traditionalmethod of constructing a one-bit memory witha relay. In the Festo controllers, the relay isreplaced by a flag, allowing any LATCH to beconstructed.

In programmable logic controllers, a one-bitmemory can also be implemented with set andreset commands. However, the LATCH hasnot lost its significance.

We differentiate two types of latch: dominantlyresetting and dominantly setting latches. Thedominant resetting latch has the value logic 0when switched on and off.

The logic symbol for the latch is shown by theflipflop:

Fig. 6/52: Flipflop dominant resetting latch

1

1

0S

R

A

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108

In Ladder diagram the dominantly resettinglatch looks like this:

Fig. 6/53: Dominant resetting latch

The following method is also possible andprobably more familiar to the electrician:

Fig. 6/54: Dominant resetting latch

Rung No. 2

I2.3 I1.2

F0.12Flag

SET RESETF0.12Flag

Rung No. 2

I2.3I1.2

F0.12Flag

SETRESETF0.12Flag

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109

The dominantly setting latch is logic 1 at theoutput when switched on and off. The flipflop ofthe dominantly setting latch differs only fromthe dominant resetting latch in that it has a 1 atthe output at the flipflop.

Fig. 6/55: Flipflop dominant setting latch

In Ladder diagram the resetting input is lo-cated in the latch itself in order to force domi-nant setting behaviour:

Fig. 6/56: Dominant setting latch

1

1

1S

R

A

Rung No. 2

I2.3

I1.2F0.12Flag

SET

RESET

F0.12Flag

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110

JUMPING to a label

The JUMP command is one possibility ofshortening the program cycle time by jumpingover unneeded parts of the program. In FestoFST, any number of jumps may be pro-grammed. JUMPS have a jump label as theirdestination, not a rung number. A label, that isa jump destination, is entered at the beginningof the conditional part of a rung. The jumpcommand is inserted in the executive part ofthe rung and must contain the name of a jumplabel. This jump label must be contained in theprogram, or else a syntax error will be re-ported when translating in the program.

The JUMP command in Ladder diagram lookslike this:

Fig. 6/57: Jump

Rung No. 69

Execution

DESTINATION

Condition

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111

Many texts on programming differentiate be-tween a conditional and unconditional JUMP.The jump command shown here is a condi-tional JUMP, but it can be easily convertedinto an unconditional jump:

Fig. 6/58: Unconditional jump

Important: A jump command does not re-place a contact. There must be at least oneentry in each contact. If you only require ajump as a result of a condition, you must en-ter an (otherwise) unused flag as the oper-and in the contact.

Rung No. 69

Execution

DESTINATION

NOP

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112

ENTERING A JUMP LABEL

The JUMP command is one possibility ofshortening the program cycle time by jumpingover unneeded parts of the program. In FestoFST, any number of jumps may be pro-grammed. JUMPS have a jump label as theirdestination, not a rung number. A label or jumpdestination, is entered at the beginning of theconditional part of a rung. The jump commandis inserted in the executive part of the rungand must contain the name of a jump label.This jump label must be contained in the pro-gram, or else a syntax error will be reportedwhen translating in the program.

In Ladder diagram the JUMP label is enteredas follows:

Fig. 6/59: Entering a jump label

Important: A jump command does not re-place a contact. Every rung must have atleast one contact, and a condition and ex-ecutive part must be entered.

ExecutionCondition

Rung No. 68

DESTIN

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113

Coils: RESET (cancel)

When coils are energised, basically we differ-entiate between stored and non-stored com-mands. The non-stored commands transferthe logic status of the condition (of the rung)directly to the coil. A coil reflects each changeof the logic status of the rung.

In the case of stored commands RESET andset, the command is executed precisely if (andonly if) the rung has logic status 1, i.e. thecondition is therefore fulfilled.

If the rung assumes logic 0, i.e. the conditionis not fulfilled, the coil which is programmedwith a stored command is not changed. Thestatus of the coil is only changed when therung containing the opposite command be-comes logic 1.

RESETTING of a coil is indicated by an R inthe coil symbol:

Fig. 6/60: Coil: Reset (Storing cancelled)

O0.1Condition

Rung No. 28

R

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114

Coils: SET

When coils are energised, basically we differ-entiate between stored and non-stored com-mands. The non-stored commands transferthe logic status of the condition (of the rung)directly to the coil. A coil reflects each changeof the logic status of the rung.

In the case of stored commands SET and re-set, the command is executed precisely if (andonly if) the rung has logic status 1, i.e. thecondition is therefore fulfilled.


SETTING of a coil is indicated by an S in thecoil symbol:

Fig. 6/61: Coil: Set

O0.1Condition

Rung No. 29

S

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115

Coils: ASSIGNMENT

When coils are energised, basically we differ-entiate between stored and non-stored com-mands. The non-stored commands – that isASSIGNMENT or negated assignment –transfer the logic status of the condition (of therung) directly to the coil. A coil reflects eachchange of the logic status of the rung.

In the case of stored commands set and re-set, the command is executed precisely if (andonly if) the rung has logic status 1, i.e. thecondition is therefore fulfilled.


ASSIGNMENT, that is the non-stored adop-tion of the logic status of the rung, is simplyprogrammed by using the coil symbol.

Fig. 6/62: Coil: Assignment

O3.2Condition

Rung No. 30

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116

Coils: NEGATED ASSIGNMENT

When coils are energised, basically we differ-entiate between stored and non-stored com-mands. The non-stored commands – that isassignment or NEGATED ASSIGNMENT –transfer the logic status of the condition (of therung) directly to the coil. A coil reflects eachchange of the logic status of the rung.

In the case of stored commands set and re-set, the command is executed precisely if (andonly if) the rung has logic status 1, i.e. thecondition is therefore fulfilled.


In the case of NEGATED ASSIGNMENT thenegation of the logic status of the rung istransferred to the coil (see also Logic: NOT).

NEGATED ASSIGNMENT, that is the non-stored adoption of the negated logic status ofthe rung, is programmed by using the negatedcoil symbol.

Fig. 6/63: Coil: Negated assignment

O3.2Condition

Rung No. 30

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117

Comparison: EQUAL

Comparison operations are basic to everyprogrammable logic controller. Comparisonsallow processing of simple analogue values,multiple evaluation of counters, comparison ofsize etc.

Festo controllers allow all comparison opera-tions to be programmed in Ladder diagram:

• EQUAL• Greater than• Greater than or equal• Less than• Less than or equal• Unequal

Comparison operations compare positivewhole numbers between 0 and 65,535. If anegative value (for example V-10) is entered,the positive whole binary number correspond-ing to the bit pattern (of V-10) is compared.This does not apply to the FPC 405 if process-ing has been switched previously to signednumbers (from 0 to 32,767) with CFM20.

Comparison operations are always enteredinto a box in the conditional part.

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118

The value of the upper operand is alwayscompared to the value of the lower operand. Ifthe expression evaluates to true, the rung hasthe logic status 1. If the expression evaluatesto false, the rung has the logic status 0.

The EQUAL operation is programmed as fol-lows:

Fig. 6/64: Comparison: Equal

In this example the rung evaluates to logic 1 ifcounter word 7 has a value that is exactlyequal to the value in counter preselect 12.

ExecutionCW7

Rung No. 33

=CP12

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119

Comparison: GREATER THAN



• Equal• GREATER THAN• Greater than or equal• Less than• Less than or equal• Unequal



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120


The operation GREATER THAN is pro-grammed as follows:

Fig. 6/65: Comparison: Greater than

In this example the rung evaluates to logic 1 ifcounter word 3 has a value that is greater than3467 (for example 3468 or even 22341).

ExecutionCW3

Rung No. 32

>V3467

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121

Comparison: GREATER THAN OR EQUAL



• Equal• Greater than• GREATER THAN OR EQUAL• Less than• Less than or equal• Unequal



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122


The GREATER THAN OR EQUAL operationis programmed as follows:

Fig. 6/66: Comparison: Greater than or equal

In this example the rung evaluates to logic 1 ifcounter word 3 has a value that is greater thanor equal to 34777 (for example 34777, 34778or greater).

ExecutionCW3

Rung No. 35

>=V34777

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123

Comparison: LESS THAN



• Equal• Greater than• Greater than or equal• LESS THAN• Less than or equal• Unequal



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124


The LESS THAN operation is programmed asfollows:

Fig. 6/67: Comparison: Less than

In this example the rung evaluates to logic 1 ifinput word 4 has a value that is less than thecontent of flag word 12.

ExecutionIW4

Rung No. 35

<FW12

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125

Comparison: LESS THAN OR EQUAL



• Equal• Greater than• Greater than or equal• Less than• LESS THAN OR EQUAL• Unequal



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126


The LESS THAN OR EQUAL operation isprogrammed as follows:

Fig. 6/68: Comparison: Less than or equal

In this example the rung evaluates to logic 1 iftimer word 5 has a value that is less than orequal to 332 (that is 332, 331 or less).

ExecutionTW5

Rung No. 37

<=V332

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127

Comparison: UNEQUAL



• Equal• Greater than• Greater than or equal• Less than• Less than or equal• UNEQUAL



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128


The UNEQUAL operation is programmed asfollows:

Fig. 6/69: Comparison: Unequal

In this example the rung evaluates to logic 1 ifcounter word 4 has a value that is unequal tothe value of output word 1.

ExecutionCW4

Rung No. 37

<>OW1

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129

Numbers: CONVERSION BCD to BINARY (DEB command)

When connecting coding switches to PLCs orwhen 7-segment displays are used, inputs andoutputs require BCD-coded decimal numbers.Festo controllers have commands that allowconversion to and from BCD: the BID com-mand for binary into decimal (that is, into BCDcode) and the DEB command from decimalinto binary (that is, from BCD code).

Please note that this operation always involves16-bit words. An output word in BCD codeconsists of 4 digits each of which can be 0 -9.

The DEB command has the following effect:

7667BCD

0 1 1 1 0 1 1 0 0 1 1 0 0 1 1 1

becomes 76672

0 0 0 1 1 1 0 1 1 1 1 1 0 0 1 1

The conversion commands BID and DEB canbe used in a multi-bit box or in the Arithme-tic/Logic Box.

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130

The DEB command is programmed as follows:

Fig. 6/70: Numbers: Convert BCD to binary

The following programming has exactly thesame effect:

Fig. 6/71: Numbers: Convert BCD to binary in arithmetic box

The conversion commands allow conversionof the content of all multi-bit operands. The re-sult can be written to any multi-bit operand ex-cept an input word.

In online mode you cannot display numericalvalues in BCD code. A BCD code is evaluatedin binary (as a binary decimal number, asigned decimal number or as a hexadecimalnumber depending on the display mode).

Rung No. 40

ConditionDEBIW4

R3

Rung No. 41


Arithmetic/logic


LOAD Contents of Input word 4DEB

IW4CONVERT DECIMAL (BCD) TO BINARY

TO R3 Write result to Register 3

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131

Numbers: CONVERSION BINARY to BCD (BID command)

When connecting coding switches to PLCs orwhen 7-segment displays are used, inputs andoutputs require BCD-coded decimal numbers.Festo controllers have commands that allowconversion to and from BCD: the BID com-mand for binary into decimal (that is, into BCDcode) and the DEB command from decimalinto binary (that is, from BCD code).

Please note that this operation always involves16-bit words. An output word in BCD codeconsists of 4 digits each of which can be 0 -9.

The BID command has the following effect:

303112

0 1 1 1 0 1 1 0 0 1 1 0 0 1 1 1

becomes 0311BCD (the leftmost digit is lost):

0 0 0 0 0 0 1 1 0 0 0 1 0 0 0 1

The conversion commands BID and DEB canbe used in a multi-bit box or in the Arithme-tic/Logic Box.

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132

The BID command is programmed as follows:

Fig. 6/72: Numbers: Convert digital to BCD

The following programming has exactly thesame effect:

Fig. 6/73: Numbers: Convert binary to BCD in arithmetic box

The conversion commands allow conversionof the content of all multi-bit operands. The re-sult can be written to any multi-bit operand ex-cept an input word.

In online mode you cannot display numericalvalues in BCD code. A BCD code is evaluatedin binary (as a binary decimal number, asigned decimal number or as a hexadecimalnumber depending on the display mode).

Rung No. 38

ConditionBIDFW4

OW3

Rung No. 39


Arithmetic/logic


LOAD Contents of Flag word 4BID

FW4CONVERT BINARY TO DECIMAL (BCD)


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133

Counting: INTERROGATED PRESELECT ACHIEVED?

The counters supplied in all Festo controllersare preselect counters. They consist of threeelements: the counter preselect (nominalvalue), the counter word (actual value) and thecounter bit (status of the counter).

Normally a counter counts from its initial valueto its end value.

The one-bit operand C (counter) can be inter-rogated for logic 0 or logic 1.

The counter is logic 0 as soon as

• the counter word and the counter preselect(actual and nominal value) are identical or

• the counter word (actual value) becomes 0(decremental counter) or

• the counter is not started.

C is logic 1 if – after starting a counter by aset command or the counter box or by loadinga value into the preselect – the preselect hasnot been reached (incremental counter) or theactual value has not reached 0 (decrementalcounter).

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134

Interrogating whether the preselect has beenreached (PRESELECT ACHIEVED) is there-fore the same as interrogating whether thecounter is inactive:

Compared to an electromechanical preselectcounter the counter module has a normallyclosed contact (not a normally open contact orchangeover contact) to indicate that the prese-lect has been reached.

Important: The condition of the rung shownis also fulfilled if the counter was not started.

Fig. 6/74: Counter: Interrogated preselect achieved

ExecutionC4

Rung No. 44

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135

Counting: INTERROGATED PRESELECT NOT ACHIEVED?

The counters supplied in all Festo controllersare preselect counters. They consist of threeelements: the counter preselect (nominalvalue), the counter word (actual value) and thecounter bit (status of the counter).

Normally a counter counts from its initial valueto its end value.

The one-bit operand C (counter) can be inter-rogated for logic 0 or logic 1.

The counter is logic 0 as soon as

• the counter word and the counter preselect(actual and nominal value) are identical or

• the counter word (actual value) becomes 0(decremental counter) or

• the counter is not started.

C is logic 1 if – after starting a counter by aset command or the counter box or by loadinga value into the preselect – the preselect hasnot been reached (incremental counter) or theactual value has not reached 0 (decrementalcounter).

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136

Interrogating whether the preselect has notbeen reached (PRESELECT NOTACHIEVED) is the same as interrogatingwhether the counter is active:

Compared to an electromechanical preselectcounter the counter module has a normallyclosed contact (not a normally open contact orchangeover contact) to indicate that the prese-lect has been reached.

Fig. 6/75: Counter: Interrogated preselect not achieved

ExecutionC4

Rung No. 45

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137

Counting: DECREMENT

Counters can count forwards or backwards:incrementing or decrementing. Both of thesetypes are supported by Festo Ladder diagram.

The counting commands can be used for anyword except for inputs.

The one-bit operand C can be used duringcounting. In reality, the counter word (actualvalue) is changed.

The counter command changes the value ofthe operand by 1: +1 for incrementer, -1 fordecrementer.

The counting command is only executed whenthe logic status of the rung changes from 0 to1, that is, only on a rising signal edge. Thismeans that a Ladder diagram imitates theclassical electromechanical counter whichalso counts the rising signal edge.

In Festo Ladder diagram, the counting com-mands are coil commands, not boxes.

In Ladder diagram, DECREMENT is pro-grammed as follows:

Fig. 6/76: Counting: Decrement

C4Condition

Rung No. 42

DEC

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138

Counting: INCREMENT

Counters can count forwards or backwards:incrementing or decrementing. Both of thesetypes are supported by Festo Ladder diagram.

The counting commands can be used for anyword except for inputs.

The one-bit operand C can be used duringcounting. In reality, the counter word (actualvalue) is changed.

The counter command changes the value ofthe operand by 1: +1 for incrementer, -1 fordecrementer.

The counting command is only executed whenthe logic status of the rung changes from 0 to1, that is, only on a rising signal edge. Thismeans that a Ladder diagram imitates theclassical electromechanical counter whichalso counts the rising signal edge.

In Festo Ladder diagram, the counting com-mands are coil commands, not boxes.

In Ladder diagram, INCREMENT is pro-grammed as follows:

Fig. 6/77: Counting: Increment

C5Condition

Rung No. 43

INC

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139

Numbers: SET COUNTER

With a preselect counter it must be possible toset a definite starting value. It must be estab-lished whether it is an incrementer (0 to prese-lect) or decrementer (preselect to 0). Acounter must be set at least once during theprogram and can then be reset to initial valueany number of times with a simple set com-mand.

The simplest case is the incremental counter.The nominal value is loaded into the preselectand the actual value set to 0. This can be doneas follows:

Fig. 6/78: Counting: Set incremental counter

A simple set of command now sets the counter(actual value) to this initial value. A resetcommand stops the counter, setting it to logic0.

Rung No. 46

Condition7663C4

Counter

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140

Resetting the actual value (counter word) to 0again is done with the SET command in theexecutive part of the rung, whereby thecounter bit C becomes logic 1 (the normallyclosed contact closes again).

Fig. 6/79

In the case of a decrementer, the counterword must be loaded with the initial value as itwill count from this initial value to 0:

Fig. 6/80: Counting: Set decrementer counter

For more detailed examples, please seeChapter 9, "Programming of counters".

C4Condition

Rung No. 43

S

Rung No. 46

ConditionTO

7663

CW4

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141

Time: Start pulse timer

Each processor module of a Festo controllerhas a number of timer modules. Each of thesetimer modules can be used as a pulse timer. Inaddition, the FPC 100B/AF, IPC, FEC andFPC 405 controllers enable the incorporationof a switch-on and switch-off delay similar tothe classic time relay.

A timer module consists of two elements:

• One element which is START TIMER.

• Another element which is interrogate timer.

START TIMER is an executive function, thatis, a box, which replaces a coil.

Interrogate timer is a conditional function real-ized as a contact.

STARTING of a pulse timer is programmed,for example, as follows:

Fig. 6/81: Time: Start pulse timer

For details of timer programming see Chapter8, "Programming of timers"

Rung No. 47

Condition4sT0

Timer

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142

Time: Interrogate pulse timer

Each processor module of a Festo controllerhas a number of timer modules. Each of thesetimer modules can be used as a pulse timer. Inaddition, the FPC 100B/AF, IPC, FEC andFPC 405 controllers enable the incorporationof a switch-on and switch-off delay similar tothe classic time relay.

A timer module consists of two elements:

• One element which is start timer.

• Another element which is INTERROGATETIMER.

Start timer is an executive function, that is, abox, which replaces a coil.

INTERROGATE TIMER is a conditional func-tion realized as a contact.

INTERROGATION of a pulse timer is pro-grammed, for example, as follows:

Fig. 6/82: Time: Pulse timer expired?

For details of timer programming see Chapter8, "Programming of timers"

ExecutionT0

Rung No. 48

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7. Addressing operands

143

Chapter 7

Addressing operands

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144

Contents

7.1 ABSOLUTE AND SYMBOLICADDRESSES.....................................145Absolute address ...............................145Symbolic address...............................148Mixing symbolic andabsolute addresses............................150

7.2 INFORMATION CONTENT OFTHE ABSOLUTE ADDRESS...........153

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145

When using a programmable logic controller,operands must be addressed.

7.1 ABSOLUTE AND SYMBOLIC ADDRESSES

The FST software differentiates between ab-solute and symbolic addresses.

Absolute address

Absolute addresses are the designators re-quired by the hardware and operating systemof a PLC. Generally these are addresses thatare incorporated by the manufacturer andused by the operator with the aid of LEDs, dig-its and selector switches.

An absolute operand address comprises anoperand identifier and an operand parameter.

Fig. 7.1

Operand address

Operand identifier Operand parameter

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146

The operand identifier is an abbreviation nor-mally consisting of one or two letters:

O Output

OW Output Word

CFM Function Module

CMP Program Module

I Input

IW Input Word

FU Function Unit

E Error

EW Error Word

V Value

V$ Hexadecimal Value

F Flag

FI Flag Initialization

FW Flag Word

NOP Null Operation

P Program

R Register

T Timer

TOFF Switch-off delay timer

TON Switch-on delay timer

TP Timer Preselect

C Counter

CP Counter Preselect

CW Counter Word

The absolute operand identifiers are auto-matically recognized by the FST software.

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147

Most operand identifiers require an additionaloperand parameter, a number, which allowsthe specific input to be addressed.

A few operands do not allow an additional pa-rameter:

FI Flag Initialization

E Error

NOP Null Operation

When using FST software, there must be nospace between the operand identifiers and theappropriate parameter.

The FST software automatically recognizes avalid absolute operand address and handles itappropriately.

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148

Symbolic address

During programming it is often very difficultand tedious to remember all operand ad-dresses. A whole range of operands are usedin various different applications. Commentar-ies could also help to make a program easierto read and understand.

This is the purpose of symbolic operands.These are the names given to operands by theuser.

In FST software symbolic operands may haveup to 9 characters, no spaces, no periodand a limited range of special characters.

FST software symbolic operands thereforeconsist essentially of letters and numbers.

Some examples of useful names for symbolicoperands are:

• Start• Stop• Left• Right• Motor1on• Motor1off• GRIPCLOSE• GRIPOPEN

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149

Naturally, a symbolic operand name must beunique within a project.

Unique means also that a name given to asymbolic operand cannot be given as a jumplabel.

Important: Symbolic operands must beclearly differentiated from absolute operands.The identifiers used for absolute operands(such as V, Y, F, etc.) must not be used assymbolic operand identifiers. For example,V12 or Y1 are absolute addresses. VALVE1,for example, would be permissible as a sym-bolic address.

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150

Mixing symbolic and absolute addresses

FST software allows mixing of symbolic andabsolute operand addresses. An allocation listinto which you enter all the names can becreated either before starting programming orduring programming.

You can also switch off the allocation list func-tion during programming and program withoutallocation list entry. This can be useful if youwant to program a routine that is to be valid forvarious machines for which the absolute ad-dresses are not yet known.

The following must always be taken into ac-count however:

As the FST software automatically recog-nizes absolute addresses, symbolic ad-dresses must be selected that do not conflictwith absolute addresses.

A typical conflict in Ladder diagram is the useof the symbol "V" for a coil.

As "V" is the identifier for the absolute oper-and Constant, "V12" is not interpreted by theFST software as a symbolic address but as anabsolute address.

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151

Apart from this limitation, symbolic and abso-lute addresses can be mixed in FST pro-grams. As an additional aid in Ladder diagramprogramming for FST software version 3.1and later, both absolute and symbolic ad-dresses are automatically shown where asymbolic address has been entered.

Fig. 7/2: Symbolic and absolute operands

In this example S1 was entered as a symbolicaddress for the latch, whereas in the outputthe absolute operand (O0.0) address hasbeen entered.

Rung No. 2

I0.0 I1.0

O0.0

O0.0

S1

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152

The allocation list lists all absolute and sym-bolic operands. The allocation list is sorted al-phabetically by absolute operand identifier.

Operands ofthe allocation list

Comment

Absolute Symbolic

O0.0I0.0I1.0

H1StartStop

Indicate machine startedS1: Start pushbuttonS2: Stop pushbutton

Practice has shown that only specific symbolicaddresses such as "Start" are useful. Thesymbolic address "SV1CCS3bk" for "Solenoidvalve 1 for cylinder C at station 3 back" is justas inconclusive as the absolute address"O3.2".

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153

7.2 INFORMATION CONTENT OF THE ABSOLUTE ADDRESS

The absolute address for Festo controllers al-ways has the same structure of the operandparameter (number). The absolute addresshas the following structure:

Fig. 7/3

Please note that the three parts of the oper-and parameter are separated by a period.Spaces are not permissible.

Operand address

Operand identifier Operand parameter

Number ofthe CCU

Number ofthe word

Number ofthe bit

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154

ExampleAddressing flags:

As the FPC 100B/AF, IPC and FEC have onlyone processor module in a system (single-processor system), it does not make sense toallocate a number for the processor module.Therefore, in these controllers flags can beaddressed from

F0.0 to Fn.n.

On the other hand, the FPC 405 controller canmanage several processor modules andprocessor modules can access the flag ofother CCUs. For this reason addressing isfrom

F0.0.0 to Fn.n.n.

As these flags are one-bit operands, each bitis numbered individually.

However, if you are using a flag word, it is in-correct to give a bit number. For this reasonthe flag words for FPC 100B/AF, IPC and FECare addressed from

FW0 to FWn.

In the case of the FPC 405 controller, flagwords are addressed from FW0.0 to FWn.nas 6 processor modules can be used in onesystem.

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155

The following table provides an overview of theabsolute addresses possible with the variousFesto controllers.

Operand FPC 100B/AF FEC IPC FPC 405

Output(word)OOW

O0.0 - O1.5OW0 - OW1

O0.0 - O0.7*OW0 *

O0.0 - O255.15*OW0 - OW255*

O0.0 - O15.15OW0 - OW15

FunctionmoduleCFM CFM0 CFM0 - CFM99 CFM0 - CFM99 CFM0 - CFM75

ProgrammoduleCMP CMP0 - CMP7 CMP0 - CMP99 CMP0 - CMP99 CMP0 - CMP75

Input (word)I

I1

IWIW2

I0.0 - I2.7–

IW0 - IW2

I0.0 - I1.3*–

IW0 - IW1*

I0.0 - I255.15*–

IW0 - IW255*

I0.0 - I15.15I0 - I7IW0 - IW15IW

Error (word)EEW

EEW

EEW

EEW

EEW

FunctionunitFUFU

FU0 - FU23FU32 - FU47

FU0 - FU23FU32 - FU47

FU0 - FU23FU32 - FU47

FU0 - FU23FU32 - FU47

InitializationflagFI FI FI FI FI

Flag (word)FFWFI3

F0.0 - F15.15FW0 - FW15

F0.0 - F9999.15FW0 - FW9999

F0.0 - F9999.15FW0 - FW9999

F0.0.0-F5.63.15FW0.0-FW5.63FI0 - FI7

1, 2, 3 see following page* On FEC and IPC we are using logical addresses. Value range from 0 ... 255

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156

Operand FPC 100B/AF FEC IPC FPC 405

NulloperationNOP NOP NOP NOP NOP

ProgramP P0 – P0 - P63 P0 - P63 P0 - P63

RegisterR R0 - R63 R0 - R255 R0 - R255 R0 - R127

TimerTTOFFTONTPTW

T0 - T31TOFF0-TOFF31TON0 - TON31TP0 - TP31TW0 - TW

T0 - T255TOFF0-TOFF255TON0-TON255TP0 - TP255TW0 - TW255

T0 - T255TOFF0–TOFF255TON0–TON255TP0 - TP255TW0 - TW255

T0 - T63TOFF0-TOFF63TON0 - TON63TP0 - TP63TW0 - TW63

CounterCCPCW

C0 - C15CP0 - CP15CW0 - CW

C0 - C255CP0 - CP255CW0 - CW255

C0 - C255CP0 - CP255CW0 - CW255

C0 - C63CP0 - CP63CW0 - CW63

1. These refer to the internal inputs of the interrupt processor module of the FPC 405.These inputs are local to one processor module and can be interrupted, have practicallyno input signal delay and can be addressed as I0 to I7.

2. If internal inputs of the interrupt processor module of the FPC 405 are to be processedas a word, the absolute address is IW.

3. Each FPC 405 program has local flags addressed from FI0 to FI7.

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157

Naturally this comparison table is not of greatinterest if you are programming other makesof controller. This table is more relevant if youwish to use programs written for one type ofFesto controller on another type.

Depending on which type of controller a pro-gram has been developed, it will be necessaryto modify the operand parameters.

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158

Notes

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8. Programming timers

159

Chapter 8

Programming timers

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160

Contents

8.1 GENERAL..........................................161Timers ................................................161Timer errors ......................................162Shortest and longest time .............163Components of a timer module ....164Activating timer initialization.......164

8.2 TIMER TYPES ...................................165Switch-on delay timer.....................166Switch-off delay timer ....................167Pulse timer........................................168

8.3 EXAMPLES........................................169Switch-on delay ...............................169Programming with TON......................170Programming with TOFF....................171Programming with T............................171Stairwell lighting.............................172Programming with TON......................172Programming with TOFF....................173Programming with T............................174Flashing lamp ..................................175Programming with TON......................175Programming with TOFF....................176Programming with T............................177

8.4 EVALUATING THE INDIVIDUALTIMER ELEMENTS...........................178Programming flashing lamp withcomparison.......................................180

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161

8.1 GENERAL

Timers

Timer modules are incorporated in all modernprogrammable logic controllers. All Festo con-trollers offer several timer modules for eachprocessor module. Depending on the control-ler type, the number of timer modules rangebetween 16 (FPC 100B/AF) and 64 (FPC405) per processor module.

The timer modules are counters which countan internal clock pulse. Timer modules ofFesto controllers use a clock pulse of 10 milli-seconds, that is, 0.01 seconds. This clockpulse is fully process-independent and isavailable as soon as the processor module ispowered up.

If a time is programmed, the preset counter isloaded with a number. The preset counter dec-rements by one for each clock pulse. When 0is reached the time has expired.

This time measurement technique works verywell and is widely used. The same technique isused in modern quartz clocks and watches: acounter counts clock pulses from a quartzcrystal. This is known as digital time meas-urement.

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162

Timer errors

Digital time measurement has a systematicminimum error of one clock pulse. This errorresults from the fact that the clock pulse isprocess-independent.

Fig. 8/1: Example of timer

In the above example the timer counts eachtrailing edge of the clock pulse. As the inputsignal changes to logic 1 "sometime", thismeans that if 3 pulses are programmed, itcounts approximately 2 pulses up to the end ofthe time period.This systematic error of event-driven timemeasurement has a maximum value of oneclock pulse.

Counter expired

Counter = 1sec

Start of timerCounter = 3secCounter = 2sec

Clock Start signal

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163

Shortest and longest time

The shortest time that can be measured by atimer of this type is two clock pulses. In thiscase the maximum error is 50%. (If a time ofone clock pulse were programmed, the possi-ble error would be 100%. If that were permis-sible, programming of the timer would be re-dundant.)

The longest time that can be measured with atimer of this type is dependent on the size ofthe counter. The counters in Festo controllersare all multi-bit operands of 16 bits. This typeof counter can count up to a maximum of65535. 65535 times 10 milliseconds is 655seconds or 10 minutes and 55 seconds.

A single timer module in a Festo controllercan measure a time between 0.02 secondsand approx. 10 minutes.

Longer time periods can be measured by cas-cading. Using this technique a single counterand a single timer module can be used tomeasure a period of up to 65,000 x 10 min-utes.

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164

Components of a timer module

Every timer must be started and interrogated.In Ladder diagram, timers are started in atimer box, which replaces a coil. Interrogationof the time is undertaken by a contact, just asin the circuit diagram.

Activating timer initialization

Timer initialization is a box replacing a coil inthe Ladder diagram, that is, in the executivepart of the rung (just as a coil of a time relay isthe load in a circuit diagram).

The box is activated via a signal edge unlessactivated by a rung in which the contact is aNOP, i.e. the box operates once when thecondition defined in the rung changes from 0to 1. The condition can then remain logic 1 forany length of time – the timer continues to run.If the condition switches from 1 to 0, theswitch-on delay timer module (TON) switchesto logic 0 and the switch-off delay (TOFF)timer begins time measurement.

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165

8.2 TIMER TYPES

Festo differentiates three different types oftimer module:

• switch-on delay timer (TON),• switch-off delay timer (TOFF) and• pulse timer (T).

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166

Switch-on delay timer

This timer is permanently set as long as thecondition is not fulfilled (0 level), that is, thetimer word is constantly loaded into the timerpreselect. The timer is active (TON=0).When the condition is fulfilled (level 1) it is notreset, but begins running. When the word is 0,the timer is inactive (TON=1). The timer onlybecomes active again (TON=0) when thecondition is no longer fulfilled.

Fig. 8/2: Behaviour of switch-on delay timer

The condition isfulfilled (seelevel 1)The timerremains active(TON=0) andrunning. After ashort time thecondition is nolonger fulfilled.The timer presetis reloaded intothe timer word.The timerremains active(TON=0).

Here the condi-tion is filled re-peatedly. Thetimer remainsactive (TON=0)and runs downfrom the startvalue of thetimer preselect.

At this point thetimer is expired.The timer wordnow has thevalue zero(TW=0) and thetimer is inactive.

From this pointthe timer reset ispermanently re-loaded into thetimer word. Thetimer is acticefrom this point(TE=0). It isrestarted on thenext level 1.

1

0

1

0

Status of the condition

Status od switch-on delayed timer

Preselect

t

t

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167

Switch-off delay timer

This timer reacts to level 1. This means that itis permanently set as long as the condition isfulfilled. The timer word is constantly loadedwith the timer preselect; the timer is active(TOFF=1). When the condition is no longerfulfilled this timer is not reset, but begins to run.When the timer has expired (TW=0), it be-comes inactive (TOFF=0). A timer does notbecome active again until the next level 1.

Fig. 8/3: Behaviour of switch-off delay timer

The condition isfulfilled (seelevel 1). Thetimer becomesactive (TOFF=1)and the timer ispermanentlyloaded.with TP.After a short timethe condition isno longer fulfilledand the timerruns down fromthe start value.

Here the condi-tion is fulfilled re-peatedly. Thetimer remainsactive (TOFF=1),as the timerword has not yetreached zero.Now the timerword is per-manently loadedwith the timerpreselect.

At this point thecondition is nolonger fulfilled.The timerremains activeand runs downagain from thestart value(Timerpreselect).

At this point thetimer is expired,i.e. the timer wordis zero.The timer be-comes inactive(TOFF=0). Onthe next level 1the timer word isloaded per-manently with thetimer preselect.The timerbecomes activeagain.

1

0

1

0



Preselect

t

t

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168

Pulse timer

This timer reacts to the rising edge of a condi-tion. If the condition is fulfilled, the timer runs.As long as the condition is not fulfilled, thetimer preselect is permanently loaded into thetimer word.

Fig. 8/4: Behaviour of pulse timer

The condition isfulfilled(risingedge). The pulsetimer starts (T=1)and at thismoment TW=TP.The timer wordis decrementedfrom now. Thetimer runs downfrom the startvalue of the timerpreselect.

Here the condi-tion is fulfilled re-peatedly. Thepulse timerremains active(T=1). Here onlythe timer presetis reloaded intothe timer word.The timer againruns down fromthe start value ofthe timerpreselect.

After the lastrising edge thereare no morewithin the timerpreselect that is,the timer is fullyexpired. Thetimer word iszero (TW=0)and the timeris expired.From here, thetimer is alwaysinactive.

From this pointthe descriptionunder Inputapplies.

1

0

1

0



Preselect

t

t

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169

8.3 EXAMPLES

The following examples are typical of time de-lays in control technology. All examples areshown with three solutions: with switch-on de-lay timer, switch-off delay timer and pulsetimer.

Pick the solution that you like best.

Switch-on delay

A lamp is to illuminate after a push button hasbeen pressed for 5 seconds. The lamp is notto illuminate if the push button is not pressed.

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170

Programming with TON

Fig. 8/5: Switch-on delay – programming with TON

The circuit diagram for the same function witha time relay looks like this:

Fig. 8/6: Circuit diagram

Rung No. 1

I0.1Start

TON0

TON05s

Timer

O0.1Lamp

Rung No. 2 Interrogate switch-on delay

Start switch-on delay

End of Ladder diagram

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171

Programming using TOFF

Fig. 8/7: Start and interrogate switch-off delay timer

Programming using T

Fig. 8/8: Start timer module/interrogate time, switch output

Rung No. 1

I0.1Start

TOFF0

TOFF05s

Timer

O0.1Lamp




Rung No. 1

I0.0Start

T05s

Timer

O0.1Lamp

Rung No. 2 Interrogate time, switch output

Start timer module


I0.0 T0

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172

Stairwell lighting

A lamp is to illuminate as soon as the pushbutton is pressed. When the push button isreleased, the lamp is to remain on for a further5 seconds.

Programming using TON

Fig. 8/9: Start and interrogate switch-on delay timer

Rung No. 1

I0.1Start

TON05s

Timer

O1.0Lamp




TON0

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173


Fig. 8/10: Start and interrogate switch-off delay timer

The circuit diagram for the same function butwith a timer relay looks like this:

Fig. 8/11: Circuit diagram

Rung No. 1

I0.1Start

TOFF05s

Timer

O1.0Lamp




TOFF0

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174

Programming using T

Fig. 8/12: Start time/switch lamp

Rung No. 1

I0.1Pushbutton

T05s

Timer

O1.0Lamp

Rung No. 2 Switch lamp

Start time

TOFF0

I0.1Pushbutton

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175

Flashing lamp

A lamp is to flash on and off at one secondintervals as long as the push button ispressed.

Programming using TON

Fig. 8/13: Flashing lamp – programmed with TON

Rung No. 1

I0.1Start

TON01s

Timer

O1.0Lamp

Rung No. 2 Switch on lamp as long as ON is running

Start ON time as soon as OFF expired

I0.1

I0.1Start

TON1

TON11s

Timer

TON0

Rung No. 3 Start OFF time

TON0Start

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176


Fig. 8/14: Flashing lamp – programmed with TOFF

Rung No. 1

TOFF1 TOFF01s

Timer

O1.0Lamp

Rung No. 2 Switch on lamp as long as ON is running

Start ON time when OFF expired

I0.1

I0.1Start

TOFF11s

Timer

TOFF0

Rung No. 3 Start OFF time

TOFF0Start


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177

Programming using T

Fig. 8/15: Flashing lamp – programming with T

Rung No. 1

I0.1 T05s

TimerO1.0Lamp

Switch on lamp

I0.1 T05s

O0.0

Rung No. 2 Switch off lamp

O0.0Pushbutton


O0.0Pushbutton Lamp

T0

S

T0Lamp

TimerI0.1

Pushbutton

RLamp

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178

8.4 EVALUATING THE INDIVIDUAL TIMER ELEMENTS

All of the previous examples assume that thetimer module consists of two elements: coil (tostart the time) and contact (to interrogate thetime). In practice however the structure oftimer modules offers other possibilities.

Each timer module consists of a timer word,timer preselect and timer bit.

Timer word:The time is actually counted in the timer word.The timer word is the counter that is decre-mented by 1 for each 0.01 second clock pulse.The timer word is the only multi-bit operand ina Festo PLC that cannot be used freely as amulti-bit operand, as it is always counting theclock pulses.

Timer preselect:The timer preselect is a word into which theinitial value of the timer module is stored. Ittherefore represents the period of the timermodule. The timer preselect is retentive in allFesto controllers, that is, the contents remainunchanged when the power is switched off (ifthe back-up battery is functioning). The timerpreselect can be calculated, counted, con-verted etc. like any other multi-bit operand.

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179

Timer bit:The timer bit can be interrogated for 1 and 0like any one-bit operand, but can also be setand reset.

Interrogation for logic 1 and logic 0 results inan answer as described under the pulse tim-ers, switch-on delay timer and switch-off delaytimer.

SETTING to logic 1 causes restart of the timerusing the period stored in the timer preselect.RESETTING to logic 0 stops the timer as ifthe time had expired.

A good understanding of these individual ele-ments enables very flexible and convenienttimer programming. For example, the previousexample of the flashing lamp could also be im-plemented with the aid of a comparative inter-rogation of the timer word:

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180

Programming flashing lamp with comparison

Fig. 8/16: Start timer module/evaluate timer word

Here the timer is set for 2 seconds and re-started as soon as it expires. The timer is in-terrogated to see if the timer word is "greaterthan 100", that is whether the timer word iscounting from 200 to 100 (this takes exactly 1second). As soon as the timer word reaches100, the lamp is switched off.

The possibility of directly accessing all ele-ments of a timer module allows any time con-struction to be programmed. The only limitationis your imagination.

Rung No. 1

I0.1 T02s

Timer

Start timer module

I0.1 O0.0

Rung No. 2 Evaluate timer word

TW0Start


Start

T0

Lamp

V100

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9. Programming counters

181

Chapter 9

Programming counters

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182

Contents

9.1 WHAT IS AN INCREMENTALCOUNTER?.......................................184

9.2 ELEMENTS OF THE COUNTER ....186

9.3 PROGRAMMING COUNTERS........191Programming incrementalcounters ............................................191Programming decrementalcounters ............................................193Programming a car parkingsystem................................................195

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183

Festo PLCs can all be programmed with in-cremental or decremental counters in Ladderdiagram.

In addition, each element of the counter mod-ule can be accessed directly.

Similarly, all word operands with the excep-tion of input words and the timer wordcan be used for counting. These are then notincremental counters but event counterswhose value is compared to other values.

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184

9.1 WHAT IS AN INCREMENTAL COUNTER?

Normally we speak of an incremental counterwhen we are using a counter that:

• Counts pulses and stores the result in itsown memory (actual value).

• Offers the possibility of setting the actualvalue to an initial value (reset input).

• Has its own memory for a preselect(nominal value).

• Has a result output that can be interrogatedto see whether the actual value hasreached the nominal value.

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185

In practice this could be:A machining centre which is to manufacture14,000 screws of a particular type.

The preselect (nominal value) is set to 14,000.

At the beginning of the operation, the operator(or an automatic mechanism) sets the counterto 0.

The counter is reset.

During the operation the counter is incre-mented by 1 for each screw. The result isshown on the display. The counter is reset.

The incremental counter shows the num-ber of parts manufactured.

As soon as 14,000 screws have been manu-factured, the machine is stopped. A new type,possibly with a new nominal value is entered.

A reaction takes place when nominal andactual values are equal.

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186

9.2 ELEMENTS OF THE COUNTER

In order to allow flexibility in counter program-ming, Ladder diagram for a Festo PLC offersthe following operands for counters:

The counter word is the operand in which theactual value is stored and is changed witheach counting pulse. The counter word mustbe reset at the beginning of the counting op-eration. Counter words are retentive in allFesto PLCs (as long as the buffer battery isworking).

The counter preselect is the operand in whichthe nominal value is stored.

The counter bit returns:

Logic 0:The counter has expired or reached the prese-lect or reached the value 0.

Logic 1:The counter is still counting, the preselect hasnot yet been reached.

Compared to an electromechanical counter,the counter bit is a normally closed contact(not a normally open contact or a changeovercontact), with which the count can be output.

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187

The counter bit is retentive in all Festo PLCs(as long as the back-up battery is working).This means that all counts are retained even inthe case of a power failure.

The following operations facilitate use of theoperands:

Counter initialization is called as a box insteadof a coil. The counter number is entered asthe operand and the number to which thecounter is to count. This number is automati-cally loaded into the counter preselect(nominal value), the counter bit is set to logic 1(the normally closed contact remains closed).

Fig. 9/1: Counter initialization

Counter set is a simple coil command. Whenthis command is executed, the counter word(actual value) is set to 0 and the counter bit tologic 1 (the counter is active).

Fig. 9/2: Setting a counter

Condition15C0

Counter

Counter 0

C0Counter 0

ConditionS

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188

Counter reset – like set – is a simple coilcommand. If this command is executed, thecounter bit has the value logic 0.

Fig. 9/3: Resetting a counter

Load counter word is a coil operation (in theexecutive part). The load counter word com-mand loads the counter word (actual value)with a number and sets the counter bit to logic1 (the normally closed contact opens). Thecounter bit reverts to logic 0 (the normallyclosed contact closes), when 0 is reached

(decremental counter).

Fig. 9/4: Loading a counter word

C0ConditionR

Counter 0

ConditionTO

V300

CW0

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189

The counting operation is a typical executiveoperation and is entered in the coil of a Ladderdiagram. When using INC (increment) thecounter is incremented by 1 and when usingDEC (decrement) the counter is decrementedby 1.

Important: Only the signal edge is counted,not the continuous signal.

Fig. 9/5: Counting

Interrogating the counter for 1 is a contact op-eration. This condition is fulfilled (the normallyclosed contact is closed) when the counter isstill counting, i.e. the preselect has not yetbeen reached.

Fig. 9/6: Interrogating a counter for logic 1

C0Signal Counter 0

I0.3INC

O0.1C ounter 0 Lamp

C0

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190

Interrogating a counter for 0 is the oppositecontact operation. The condition is fulfilled (thenormally closed contact is opened) if the pre-select has been reached, i.e. the counter is nolonger counting or if the counter has reachedthe value 0.

Fig. 9/7: Interrogating a counter for logic 0

Compare counter word or counter preselectare boxes which replace a contact. The actualvalue (counter word) or the nominal value(counter preselect) is compared with a number(constant) or with another word operand, in-

cluding other counter words.

Fig. 9/8: Compare counter word or counter preselect

O0.1C ounter 0 Lamp

C0

O0.1C _Word 0 Lamp

CW0>=V15

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191

9.3 PROGRAMMING COUNTERS

Programming incremental counters

The incremental counter is probably the mostcommonly used type of counter. The followingprogram counts the signals at input I0.3(symbolic name: Signal). After 10 signals, out-put O0.1 (symbolic name: Lamp) is switchedon. A signal at input I0.1 (symbolic name: Re-set) resets the current value of the counter to0 and sets the counter bit back to logic 1.

Fig. 9/9: Programming an incremental counter in LDR

Rung No. 1 Counter preset to 15 in first cycle

FI

I0.1Reset

Rung No. 2 Counter word to 0

I0.3Signal

Rung No. 3 Increment

C0Counter0

Rung No. 4 Evaluate counter status

C010

Counter

Counter

C0Counter0

S

C0Counter0

CP

O0.1Lamp


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192

Note: The first rung initializes the counterimmediately after power-up (with FI). This isnecessary because the interrogation in rung4 whether the counter is "inactive" would oth-erwise be fulfilled immediately after power-up(for the FPC 405). The counter would only beset to logic 1 (and therefore the lamp out) af-ter the first reset command (rung 2).

The circuit diagram for an electromechanicalcounter for the same function as the aboveprogram looks like this:

Fig. 9/10: Current diagram for incrementer

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193

Programming decremental counters

In the case of the decremental counter, theactual value (counter word) must not be set to0, but must start at the desired number. Thecounter bit then becomes logic 0 as soon as 0

is reached.

Fig. 9/11: Programming decremental counter in LDR

FI

Rung No. 1

I0.1Reset

Rung No. 2 set counter word (Ist) to 10

Rung No. 3 Counting

I0.3Set

Rung No. 4 Eva luate counter status

C0Counter 0

End of Ladder d iagram

start counter in first cyc le

V10TO

C_Word0

V 10TO

C_Word0

C0Counter0

DE C

O0.1Lamp

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194

Note: As the counter is a decrementalcounter, it cannot be reset by simply usingthe set command. A box (the Arithmetic/LogicBox can also be used) must be used to loadthe start value into the counter word.

Furthermore, in this example the initializationflag ensures that the counter is active imme-diately after power-up of the controller. Oth-erwise the condition in rung 4 would be metimmediately after power-up, and the lampwould be switched on.

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195

Programming a car parking system

The car park is a classic example of this typeof counter:A car park has space for 10 cars. In front ofthe car park is a traffic light. The traffic lightshows green as long as there is still space inthe car park (and the counting system isworking). The traffic light shows red as soonas the car park is full.

Fig. 9/12: Programming of car parking facility in LDR

I0 .1

Rung No. 1

I0 .5E nter

Rung No. 2 Car entering

Rung No. 3 Car exiting

I0.7Set

Rung No. 4 Switch traffic light

CW0Counter 0


Set Counter word to 0

C0Counter0

DEC

O0.2

C0C ounter0

IN C

O0.3RedV10 V0

CW0

C010

Counter

Counter0

Green

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196

Please note: The only purpose of rung 1 is toset the counter to 0 if necessary (for exam-ple, if the counter still contains a count from atest, the controller is brand-new or the batteryhas just been replaced).

As only counting commands and a comparisonare used there is no reason to use a counterhere. One could just as well use a flag word, aregister, an output word etc. (anything exceptan input word).

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10. Using registers

197

Chapter 10

Using registers

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10. Using registers

198

Chapter 10

Using Registers ...................................... 199

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10. Using registers

199

In the Festo controllers registers are 16-bitword operands. Their contents can thereforebe between 0 and 65,535 (unsigned), between0 and 32,767 (signed), between $0 and$FFFF (hexadecimal) or between 0 and 9999(BCD).

Arithmetic operators (+, -, /, *) assume un-signed numbers unless the FPC 405 isswitched to signed numbers with CFM20.

In the case of comparison operations (=, >,>=, <, <=, <>) unsigned numbers are assumedunless the FPC 405 is switched to signednumbers with CFM20.

All bit-manipulating operations (ROL, ROR,SHL, SHR, INV, CPL) manipulate all 16 bits ofthe registers.

All bit-comparison operations (AND, OR,EXOR) compare all 16 bits.

A single bit cannot be accessed directly. If, forexample, the 6th bit of a register is to be set tologic 1 it must either be OR masked or theregister must be loaded into a flag word, the bitmanipulated and the contents of the flag wordreloaded into the register.

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10. Using registers

200

All registers of Festo controllers (except forthe FEC) are retentive, as long as the back-upbattery is functioning.

For the FEC only registers 0 ... 127 are reten-tive.

Register 63 of the FPC 100B/AF cannot beused for general register applications. Thisregister serves only for setting the input signaldelay for the input of the FPC 100B/AF (seeAppendix B.8).

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11. Using flags

201

Chapter 11

Using flags

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11. Using flags

202

Contents

11.1 FLAG BIT...........................................203

11.2 FLAG WORD.....................................207

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11. Using flags

203

11.1 FLAG BIT

Flags fulfill the same function as the auxiliaryrelay in the circuit diagram: a relay that is notswitched externally but only fulfills a functionwithin the controller.

Flags can be used as outputs, except that out-puts have an external connection and an ex-ternal LED, where as flags are only presentand visible within the system.

All operations that can be used on outputs canalso be used on flags, for example assign-ment, setting, resetting, interrogating etc.

Flags are differentiated from outputs by thefollowing points:

• Every Festo controller has retentive (non-volatile) flags whose status is retained afterpower loss or power

• failure (assuming the back-up battery isfunctioning).

• The status of the flag remains unchangedeven if the appropriate processor group isswitched to stop.Outputs, on the other hand, are set to logic0 (depending on the controller type).

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11. Using flags

204

Like outputs, flags are organized as wordswith 16 bits each. For this reason an absoluteflag address always consists of an indicationof the flag word and the flag bits, for example:

Fig. 11/1

F12 . 3

Bit no. 3 (this is the fourth bit!)

Use a period to separate word and bit.Under no circumstances use a space!

Flag word no. 12

Operand identifier is F for Flag.No space allowed between F and thenumber of the flag word!

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11. Using flags

205

In the case of the multiprocessor controllerFPC 405 the processor module can be indi-cated in addition to the flag word. Each pro-gram in each processor module can accessthe global flag of other processor modules byincluding the processor module number in theabsolute address, for example:

Fig. 11/2

F3 .14

Bit no. 14 of the inicated word(this is the 15th bit)

Use a period to separate word and bit.Under no circumstances use a space!

Flag word no. 0

Operand identifier is F for Flag.No space may appeare between the Fand the following parameters.

. 0

Use a period to separate processormodule and word. Under no circumstances use a space

CCU no. 3 (this is the 4th CCU)

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11. Using flags

206

In the case of the FPC 405 there are an addi-tional 8 flags for local use within the processormodule. These flags are only available for thelocal program and are always set to logic 0when the program is started. The flags are ad-dressed as FI0 to FI7. FI0 to FI5 are freelyusable within the program.

FI6 becomes logic 1 if a mathematical opera-tion using CFM20 results in an overflow.

FI7 is used for the storage of a bit shifted outin a SHIFT operation. It can be interrogated.As this flag is a local flag it is not entered in theallocation list. The allocation list belongs to theproject and can only manage local operandsthat belong to a processor module.

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11. Using flags

207

11.2 FLAG WORD

As flags are organized in words of 16 bits,these words can also be addressed as words.In the absolute address the bit number and theperiod before it are not required. The operandidentifier is FW for flag word, for example:

Fig. 11/3

FW4

Operand identifier FW for Flag wordNo space may occur between FW andthe parameter.

Flag word no. 4 (this is the 5th word)

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11. Using flags

208

Like flag bits, flag words of remote processormodules can be manipulated when using amulti-processor system (FPC 405). In thiscase the CCU number is added to the abso-lute address, for example:

Fig. 11/4

Flag words can be manipulated with all opera-tions used for words: Interrogation operationsare comparison operations (=, >, >=, <, <=,<>); LOAD TO is an example of a word-manipulating operation; all arithmetic opera-tions (+, -, *, /); the bit-manipulating operationsAND, OR, EXOR, CPL, INV; and the counteroperations INC and DEC (increment and dec-rement).

FW . 15

This means Flag word no. 15 (this isthe 16th word!)

A period (not a space) separates wordnumber and CCU number (not for IPC / FEC)

Number of the processor module(not for IPC or FEC)

4

FW for Flag wordNo space may appear between FW andthe parameters (4.15).

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Àppendix A - Example programs

209

Appendix A

Example programs

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210

Contents

A.1 SEQUENCE PROGRAMS ...............211Sequence program with existingflag chain, with storingcommands ..........................................214Sequence program with existingflag chain and latching........................215Sequence program with resettingsequence............................................217Sequence program with counter........219

A.2 MEASURING THE CYCLE TIME ....220Number of cycles every 3 seconds ..221Absolute duration of a cyclein 0.1 ms .............................................223Measuring reaction time ....................225Measurement and display of theabsolute reaction time........................227Display of the longest cycle time.......229

A.3 STRUCTURED PROGRAMMINGIN LADDER DIAGRAM ....................233

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211

A.1 SEQUENCE PROGRAMS

Research shows that sequence programs oc-cur in 80% of all automation systems. In mostcases where programmable logic controllersare used a sequence program is likely to be atthe heart of the system.

Using a simple and very well known example itwill be demonstrated how a sequence programcan be programmed using Ladder diagram. A"bedside lamp controller" is to be programmed.Press the pushbutton → lamp on; press thebutton again → lamp off.

In your bedside lamp the problem is probablysolved mechanically. The switch has amechanism that causes the current to beswitched on and off. The electrician knows theproblem of the hall way light. There a latchingrelay is used which also solves the problemmechanically.

What does the diagram of the bedside lampcontrol look like?

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212

The function diagram in accordance with DIN40719 part 6 has the following structure:

Fig. A/1: Function diagram to DIN 40719

There are several ways in which a sequenceprogram can be programmed in Ladder dia-gram. Here, four systematic methods will bepresented. The aim is the systematic devel-opment of a sequence program, not the short-est, most elegant or most popular means. Ifyou don't have your own "preferred method",select the one that you like best. If you have towrite a sequence program, write the basicstructure, copy the rungs with which the stepsare to be constructed, for as many steps asrequired and complete the rest. That's it!

Lamp off

1

C ontinue

2

Lamp off

3

Jump

4

S Lamp on

S Continue

S Lamp on

S Continue in firs t step

P ushbutton released?

P ushbutton

P ushbutton

P ushbutton released?

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213

You should consider the counter method only ifyou have to program longer sequences. It maybe that your controller has too few flags avail-able. The FPC 100, for example, has 256flags available. If your sequence has 150steps, the number of flags required could be aproblem.

Please note that in all examples the pro-grams are such that after power-up the con-troller begins at the first step (even after apower failure). In order to ensure this evenwhen retentive flags or a retentive counterword are used, the first step in the rung is al-ways a reset with the aid of the initializationflag FI.

Please also note that the following programexamples often use operand designations.The absolute designations are automaticallyadded so that the symbolic designators actas a type of commentary in the program.

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214

Sequence program with existing flag chain, with storingcommands

This programming method assumes that eachstep requires a flag. An additional flag isswitched on (this is the reason for the name"existing flag chain", as in the last step all flagsare "existing"). The outputs are storing and di-rectly connected to the appropriate flags.

Fig. A/2: Ladder diagram

V0TOFW3

SO1.0Lamp

SF3.1

Step 1

SF3.1

Step 1

RO1.0Lamp

SF3.3

Step 3

TOFW3

V0

FI

F3.1Step1 Pushbutton

I0.1

F3.1Step 1

F3.2Step 2

I0.1Pushbutton

F3.2 F3.3Step 2 Step 3

I0.1Pushbutton

F3.3 I0.1Step 3 Pushbutton

Rung No. 1 Reset all flags

Rung No. 2 First step

Rung No. 3 Second step

Rung No. 4 Third step

Rung No. 5 Last step

End of the ladder diagram program

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215

Sequence program with existing flag chain and latching

This programming method is similar to the ex-isting flag chain with storing commands. Thedifference is that no storing commands areused but latching. This method requires theseparation of the step chain from the switchingof outputs. The entire Ladder diagram is thusseparated into a "Control part" and a "Powerpart". The control part only contains the stepchain, the outputs are switched in the powerpart.

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216


V0TOFW3

F3.2Step 2

F3.3Step 3

FI

F3.1

Step1

Step1 PushbuttonI0.1

F3.2Step 2

F3.2Step 2

I0.1Pushbutton

F3.3

F3.3

Step 3

Step 3

I0.1Pushbutton








F3.1

Step 4F3.4

Step 1F3.1

Step 2F3.2

Step 3F3.3

Rung No. 6 Lamp switching


F3.1Step 1

F3.4Step 4

O1.0Lamp

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217

Sequence program with resetting sequence

The resetting sequence is very popular in re-lay technology and has therefore beenadopted by many electricians in Ladder dia-gram programming.

Here too the "Control part" and "Power part"are separated (not entirely necessary) and (inthis programming example) programming isdone entirely with latching.

Please note in the case of the resetting se-quence that at the start of the sequence thelast step must be set (if necessary a stepwithout action). For this reason the initializa-tion flag is used in the first rung to load value16 into the flag word. This sets flag F3.4.

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218


V0TOFW3

F3.2Step 2

F3.3Step 3

FI

F3.4

Step 1

Step 4 PushbuttonI0.1

F3.1Step 1

F3.2Step 2

I0.1Pushbutton

F3.2

F3.3

Step 2

Step 3

I0.1Pushbutton








F3.1

Step 2F3.2

Step 3F3.3

Step 4F3.4

Step 1F3.3

Rung No. 6 Lamp switching


F3.1Step 1

F3.4Step 4

O1.0Lamp

F3.4Step 4

O1.0Lamp

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219

Sequence program with counter

Programming of a sequence with a counter istotally unknown in relay technology as acounter cannot be interrogated for its currentstatus. On the other hand the counter methodallows significantly more flexible programming– particularly jumps can be very elegantlysolved.


V 1TO

Step z

CPCW0Step z

SO1.0Lamp

CPCW0

Step z

CW0CP

Step z

CW0R

Lamp

TOV1

Step z

FI

V1

CW0Step z

PushbuttonI0 .1

V2 I0.1Pushbutton

V3

CW0Step z

CW0Step z

I0 .1Pushbutton

V4 I0.1

CW0

Pushbutton

End of Ladder d iagram

Rung No. 1 C ounter to 1

Rung No. 2 First S tep

Rung No. 3 Second Step

Rung No. 4 Third Step

Rung No. 5 Last S tep

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220

A.2 MEASURING THE CYCLE TIMEIt is often interesting to know the cycle time ofa processor module. Although Festo givesdata on the time requirement of individualcommands for each controller type, it is almostimpossible to calculate the cycle time of a par-ticular program. It is a lot easier to write asmall program in which the cycle time is writtento a register. With the aid of the on-line func-tion this register can then be examined.

There are only two restrictions that need to betaken into account.On the one hand the measuring program alsohas a cycle time. The cycle time is easy toevaluate by doubling the measuring programand comparing the new cycle time with theprevious cycle time.The cycle time increase caused by the meas-uring programs are given. Deduct the time re-quired for the measuring program from themeasured result.Secondly, data transfer for online mode alsoadds to the cycle time. But you need onlinemode to read the result of the cycle timemeasurement. This is also the reason why youcan set the dynamic display in online mode toslower or faster. By changing this displayspeed you can clearly see the influence on thecycle time. Select a slow display speed whendisplaying dynamically, otherwise the valueswill be totally unrealistic.

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221

Number of cycles every 3 seconds

This program counts how many cycles areexecuted within 3 seconds. The result isstored in register 1 and is updated every 3seconds.


A rithmetic/logic

Boxes in Rung No. 1

LOAD S et to 0TO

V0The counter register

TO The display register

Arithm.& Logic

T03s

Timer

FI

Rung No. 1 Reset of Registers and TimersRung No. 2Rung No. 3

Cycle countingEva luate resu lt

Rung No. 1 R eset of Reg isters and Timers

R0R1

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222

Fig. A/7: Ladder diagram – continued

This measurement program increases theactual cycle time for each processor moduleas follows:

• FPC 100B/AF by 0.1 ms• IPC by *** ms• FEC by *** ms• FPC 405 by 0.15 ms

Arithmetic/logic

Boxes in Rung No. 3

LOAD Total number a fter 3 secondsTO

R0Display in d isplay register

LOAD Reset to 0R0

R1

NOP

Rung No. 2 C ycle counting

T0

Rung No. 3 Evaluate result

R 0CP

A rithm.& Logic

T0S

TOV0

of the counter register

End of Ladder diagram program

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223

Absolute duration of a cycle in 0.1 ms

As in the first program, this program countshow many cycles are executed in 3 seconds.This value is then converted into the absolutetime per cycle. The value stored in register 2must be multiplied by 0.1 ms in order to find theduration of an individual cycle.


A rithmetic/logic

Boxes in Rung No. 1

LOAD S et to 0TO



Arithm.& Logic

T03s

Timer

FI

Rung No. 1 Reset of Registers and TimersRung No. 2Rung No. 3

Cycle countingEva luate resu lt

Rung No. 1 R eset of Reg isters and Timers

R0R1

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224


This measuring program increases the actualcycle time of a processor module by approx.1.0 ms.

Arithmetic /log ic

Boxes in Rung No. 3

LOAD 30.000 (that is 3 seconds)/

V30000Number of cyc le a fter 3 seconds

TO Disp lay cycle time per 0.1 m s

R0

R0

F15.15

Rung No. 2 C ycle counting

T0

Rung No. 3 Evaluate result

R 0CP

A rithm.& Logic

T0S

R1Reset to 0


Edge

LOADTO

V0And restart counting

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225

Measuring reaction timeOften the actual reaction time is of muchgreater interest than the cycle time. This isbecause the reaction time of a PLC includesthe input signal delay. As a result, the reactiontime is the time that expires between the pres-ence of a signal at an input and of the appro-priate signal at an output.The input signal is delayed by the input signaldelay. Depending on the controller type, updat-ing of the process image may be required inaddition.Only then can the program with the cycle timeof a processor module take affect.For this reason the following two programs donot use a flag for the edge to be counted butan input signal that is taken from the output ofthe controller.


Arithmetic/logic

Boxes in Rung No. 1

LOAD Set to 0TO



Arithm.& Logic

T03s

Timer

FI

Rung No. 1 Reset registers / start timerRung No. 2Rung No. 3

Interrogate input / switch output

Evaluate counter after 3 sec.

Rung No. 1 Reset

R0R1

Rung No. 4Counting

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226


This measuring program increases the actualcycle time of a processor module as follows:

• FPC 100B/AF by 0.2 ms• IPC ***• FEC ***• FPC 405 negligible compared to input sig-

nal delay

Arithmetic /log ic

Boxes in Rung No. 4

LOAD Actual countTO

R0Disp lay cycles per 3 sec.

LOAD Number 0R1

I0.7

Rung No. 2 Interrogate input / switch output

T0

Rung No. 3 Counting

R 0CP

A rithm.& Logic

T0S

V0Set counter register to 0


TO R0

I0.7

T0

O0.7

Rung No. 4

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227

Measurement and display of the absolute reaction time

This program measures the reaction time inthe same way as the previous program. Theresult is converted into the absolute time for areaction cycle, whereby the value in register 2must be multiplied by 0.1 ms.


A rithmetic/logic

Boxes in Rung No. 1

LOAD S et to 0TO

V0Register 0 (actual counter)

TO Register 1 (display cycles per 3 sec.)

Arithm.& Logic

T03s

Timer

FI

Rung No. 1 Reset registers / start timerRung No. 2Rung No. 3

Interrogate input / sw itch output

Eva luate counter after 3 sec.

Rung No. 1 R eset

R0R1

Rung No. 4Counting

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228


A rithmetic/logic

Boxes in Rung No. 4

LOAD Actual countTO

R0Disp lay cycles per 3 sec.

LOAD Number 0R1

I0.7

Rung No. 2 Generate flag edge for counting

T0

Rung No. 3 Counting

R 0CP

A rithm.& Logic

T0S

V0Set counter register to 0


TO R0

I0.7

T0

O0.7

Rung No. 4 Evaluate counter a fter 3 sec

LOAD V30000/TO

R1R2

30.000Divided by R1Cycle tim e in 0.1 ms

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229

This measurement program increases theactual cycle time of a processor module asfollows:

• FPC 100B/AF by 0.2 ms

• IPC ***

• FEC ***

• FPC 405 negligible compared to input sig-nal delay

Display of the longest cycle time

In many cases the cycle time varies consid-erably. For example if jump commands ormodules are used in a program, if parallel pro-gramming of the FPC 405 is used or if the in-terrupt capability of the FPC 405 is used or if aBASIC program is used for this controller forprocess visualization or operator guidance,the cycle time can fluctuate considerably. Inorder to be able to measure the cycle timeproperly in such cases a register is used forthe maximum value. This allows cycle timemeasurement to run in the background whilethe machine executes all possible programvariants. Later the longest cycle time can beread from the registers.

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230


A rithmetic/logic

Boxes in Rung No. 1

LOAD Set to 0TO

V0count reg ister

LOAD Theoretical max. value

Arithm.& Logic

T03s

Timer

FI

Rung No. 1 Reset registers and timerRung No. 2Rung No. 3

Counting cycles

Eva luate resu lt

Rung No. 1 R eset

R0V10000

Rung No. 4Eva luate resu lt

TO R1 Memory for smallest value

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231

Fig. A/15: Ladder diagram – continued 1


Rung No. 2 Counting cycles

NOPCPR0

R0<R2

T0 Arithm.& logic

ST0

Rung No. 3 Evaluate resu lt

Boxes in Rung No. 3

LOAD R0TO R1LOAD V0TO R0

Current number of cyclesSmallest number of cyclesNumber 0Start counting aga in

Arithmetic / logic

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232


Use of this measurement program increasesthe actual cycle time for a processor moduleas follows:

• FPC 100B/AF by 0.24 ms• IPC by *** ms• FEC by *** ms• FPC 405 by 0.30 ms

Rung No. 4

LOAD V0TO R0

Value 0Start counting aga in

Arithm.& logic

T0 R0

R2

ST0

New counter status is larger

Boxes in Rung No. 4

Arithmetic / logic

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233

A.3 STRUCTURED PROGRAMMING IN LADDER DIAGRAM

Commonly used control programs for automa-tion technology are very similar in their struc-ture. For this reason a structure for a Ladderdiagram program is shown here. This structureis not standardized and is not particularly ele-gant but helps to make a program easy to writeand read. For this reason we suggest:

1st Rung


This rung carries out all settings that need tobe carried out once when the controller ispowered up. Often this means that retentiveflags, counters etc. need to be reset, and anoutput with a ready lamp has to be switched onand that possibly a READY MESSAGE needsto be displayed on a text display.

Boxes in Rung No. 1

Rung No. 1 Reset at start

Arithm.& logic

FI

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234

2nd Rung


The first entry here is the flag "Begin". Thisserves as a jump destination from any point inthe program.

The second entry is interrogation of theEMERGENCY OFF, the most important errormonitoring function. EMERGENCY OFF nor-mally requires (in addition to hardware monitor-ing of EMERGENCY OFF in accordance withDIN VDE 57 113 part 1, IEC 204-1 orEN 60204 part 1) switching off of nearly alloutputs, possibly switching on of a displaylamp for EMERGENCY OFF etc. In addition, inthis example, the program jumps back to"Begin". Nothing else needs to be done in theevent of an EMERGENCY OFF.

Boxes in Rung N o. 2

BEGIN Arithm.& logic

BEGIN

Rung No. 2 EMERGENCY OFF

EMERGENCY OFF

LI0.0

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235

Next group of rungs


This part of the program allows selection ofthe automatic/manual mode.If necessary, further error messages aremonitored here. It is important that operatingmode selection takes place in such a way thatcontrol can pass immediately to the rung con-taining the selected operating mode.

Rung No. 3 Call AUTO mode

I0 .1AUTO

O1.0

AUTO

O1.1

MANUAL

I0.2MANUALRung No. 4 Call MANUAL mode

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236

Group: automatics


Automatic operation is programmed in thisrung group. This is normally a sequence pro-gram, for which reason a step counter is used.At the end of this section, control returns to the"Begin" flag.

Boxes in Rung No. 6

Rung No. 5 F irst rung of AUTO mode

I1 .0

NOP CFM0Module

BEGIN

Rung No. 6 Last rung of AUTO modeStep z

TOV1AUTO

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237

Group: manual


This rung group has a similar structure to"automatic", except that there is no stepcounter as the manual mode is normally im-plemented as a parallel logic program.

The last rung of this group also passes controlback to the "Begin" flag.

The more clearly a program is structured, theeasier it is to find and eliminate errors. Only awell structured program is a help whensearching for a defective sensor, a defectivevalve or a sticking relay.

Boxes in Rung No 8

Rung No. 7 F irst rung of MANUAL mode

I1 .1Manual mode

NOP CFM0Module

BEGIN

O0.1Motor

Rung No. 8 Last rung of MANUAL mode

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238

Notes

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Appendix B - Differences in program execution

239

Appendix B

Differences in program execution

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240

Contents

B.1 PROCESS IMAGE.............................241Safety routines ...................................242Cycle time...........................................243

B.2 MULTITASKING................................244

B.3 MULTIPROCESSING........................246

B.4 INTERRUPT CAPABILITY...............247

B.5 INTERNAL INPUTS AND FLAGS...248Internal inputs of the FPC 405...........248FPC 405 local flags............................249Local and global allocation list ...........250

B.6 SERIAL DATA PORT.......................251Hardware ............................................251Active/passive interface ....................252

B.7 BEHAVIOUR AFTER BATTERYFAILURE............................................253

B.8 INPUT SIGNAL DELAY....................255FPC 100B/AF.....................................255FPC 405 .............................................257IPC ......................................................257FEC.....................................................257

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241

This appendix examines the differences be-tween the controllers offered by Festo. The listdoes not claim to be complete and is not anystrict order. Nonetheless it should provide auseful source of information.

B.1 PROCESS IMAGE

The FPC 100B/AF, IPC and FEC controllerswork with a process image of the inputs andoutputs. The FPC 405 controller writes andreads directly to the appropriate input or outputin each program line.

In practice this means that before processingthe entire Ladder diagram, the FPC 100B/AFreads the status of all inputs into a memoryarea and the status of all outputs is read froma memory area to outputs.

This updating of the process image also oc-curs after each backward jump, so that thereare no programs in which the process imageis not updated.

If updating of a process image is required at aparticular point in the program, a backwardjump is inserted.

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242

Safety routines

With the FPC 100B/AF, IPC and FEC (that is,with process image) an output is not switcheddirectly as a result of a rung but only prior tothe next execution of the program. For thisreason it is both possible and useful to writemonitoring routines at the end of the pro-gram which eliminate problems caused by aprogramming error earlier in the program. It isnormal practice to first program rungs thatprevent "the worst" from happening: a cylindermay only extend if another one has alreadyretracted; a motor may only be switche on if itis disengaged; the direction of rotation of amotor must be unambiguous etc.

All further rungs are written before these lastmonitoring rungs. If a similar safety routine isto be used with a multiprocessor system (FPC405), flags are programmed first instead ofoutputs. At the end of the program the flagsare then transferred to the outputs taking thesafety routines into account.

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243

Cycle time

The example programs show several pro-grams that measure cycle time. Where thesedo not measure reaction time but the pure cy-cle time, the time taken to execute a completeprogram is measured. In the case of control-lers with process image the reaction time iscalculated from the input signal delay, the(comparatively short) output signal delay andtwice the cycle time. In the case of controllerswithout process image the single cycle time issufficient.

The reason for this is that the change of a sig-nal at an input can take place immediately af-ter updating of the process image. The follow-ing cycle works with the old logic status. Theprocess image is then updated (after onecomplet cycle) and the program continuesexecuting with the new logic status and writesthe new update to the output during the nextcycle (the second cycle is complete).

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244

B.2 MULTITASKING

The FPC 100B/AF, FEC, IPC and FPC 405can store several programs (with differentprogram numbers) in their program memory.Of these stored programs, several programscan be identified as a task and processed si-multaneously (quasi-parallel processing).

The controllers support multitasking as follows:

• FPC 100B/AF: 1program and 8 programmodules

• IPC: up to 64 programs

• FEC: up to 64 programs

• FPC 405: up to 64 programs can bestored. Of these up to 8 Ladder diagramprograms can be processed simultane-ously. If only 1 Ladder diagram program isprocessed, an additional 48 Statement listprograms can be processed. For furthercombinations see the FPC 405 manual.

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245

All Festo controllers can process programmodules, that is subroutines, created by theuser. The controllers support program mod-ules as follows:

• FPC 100B/AF: 8 modules

• IPC: 100 modules

• FEC: 100 modules• FPC 405: 32 modules (can only be written

in Assembler if they are to be called from aLadder diagram program)

All processor modules contain function mod-ules provided by Festo as follows:

• FPC 100B/AF: CMP0 - CMP7• IPC: CMP0 - CMP99• FEC: CMP0 - CMP99• FPC 405: CMP0 - CMP31

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246

B.3 MULTIPROCESSING

The FPC 405 allows several processor mod-ules to work together via a system bus. Com-munication takes place with the aid of flags.

If a program is to be imported from an FPC405 into FPC 100,FEC or IPC, absoluteadddressing of flags must be adapted accord-ingly (in addition to other changes). This is be-cause in the FPC 405 the flag addressescontain the processor module number.

Each processor module can access the globalinputs and outputs and global flags via thesystem bus. The Festo multiprocessor operat-ing system manages bus access to the proc-essor modules.

If two processor modules access the bus si-multaneously, the operating system allows ac-cess in the order of priority: processor modulenumber 0 (highest priority) to processor mod-ule number 5 (lowest priority).

Processor module 0 also tests the system buson power-up. For this reason, each configura-tion must contain a CCU number 0. The re-maining CCUs can then each be given aunique number in the range of 1 to 5.

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247

B.4 INTERRUPT CAPABILITY

In order to allow rapid reaction to external sig-nals, Festo controllers have inputs that allowan interrupt program to be called. This reactionis considerably faster than would be possiblewith other inputs and normal program execu-tion.

The controllers have interrupt inputs as fol-lows:

• FPC 100B/AF: 1 input with max. 3 kHz

• IPC: Input module

• • FEC: 2 inputs with max. 4 kHz

• FPC 405: 8 interrupt inputs on the interruptprocessor module

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248

B.5 INTERNAL INPUTS AND FLAGS

The FPC 405 has so-called internal inputs andinternal flags.

Internal inputs of the FPC 405

The interrupt processor module of the FPC405 has 8 inputs directly on the CCU module.

These 8 inputs are called internal inputs, asthey are only available to the local processormodule. In contrast to these internal inputs, allother inputs can be addressed by any proces-sor module (if they are working together viathe system bus).

The internal inputs are fast inputs with an inputsignal delay of approx. 60 µs (in contrast toapprox. 5 ms for "normal" inputs).

The absolute addresses of these inputs are I0to I7 or IW.

When using these 8 inputs for "normal' pur-poses, take into account that there is practi-cally no input signal delay available. For thisreason, these inputs must be connected via ashielded cable or an input signal delay must beprogrammed with a timer module.

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249

FPC 405 local flags

The FPC 405 processor modules offer 640local flags and 384 global flags. The local flagscan only be addressed within the local proces-sor module. The global flags can be ad-dressed by any processor module via thesystem bus.

Addressing of FPC 405 flags is as follows:F0.0.0 to F.23.15 are global flags.F24.0 to F63.15 are local flags.

In this context, local means that these flagscan only be addressed within the local proces-sor module.In addition there are 8 flags that are program-internal and are addressed as FI0 to FI7.These 8 flags always have the status logic 0when the program is started. The first 6 ofthese flags are available for use within theprogram. Flags FI6 and FI7 have the followingfunctions:

• FI6 becomes logic 1 in the event of anoverflow when using a mathematical opera-tion with CFM20.

• FI7 is used to store the bit shifted out dur-ing a SHIFT operation.

Only absolute addressing can be used forthese 8 program-internal flags. They are notentered into the allocation list.

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250

Local and global allocation list

Because of these inputs and flags (and other"local" operands such as the registers) FSTsoftware for the FPC 405 differentiates be-tween the global allocation list that containsoperands accessible to all processor modulesand the local allocation list, containing oper-ands for the local processor modules.

Note: If you exchange programs betweendifferent systems (file import), then the differ-ent types of addressing of local operandsmust be observed.

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251

B.6 SERIAL DATA PORT

Hardware

All Festo PLCs are equipped with a port forserial data transmission, the command inter-preter port. The port types are as follows:

• FPC 100B/AF: RS232C data port

• IPC: RS232C data port

• FPC 405: RS232C data port

• FEC: RS232C data port

These data ports (the IPC and FPC 405 alsohave serial data ports) allow connection of theprogramming and test device to the controller(industry-standard personal computer).

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252

Active/passive interface

All Festo PLCs have a common command setfor the serial data interface. This means thatexternal addressing of all Festo PLCs isidentical.

Festo also offers PLC modules to drive vari-ous text displays. These allow Festo PLCs todrive text displays, printers etc. directly from aLadder diagram program with the aid of theserial interface.

In addition, the FPC 405 controller allows ac-tive control of the interface from the program.This controller can send data to or requestdata from another computer system. This canbe done using Festo BASIC and the serial portbelonging to the BASIC equipment of the con-troller. This is done by calling a simultaneouslyexecuting BASIC program from Ladder dia-gram. For details see the BASIC manual.

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253

B.7 BEHAVIOUR AFTER BATTERY FAILURE

The FPC 100B/AF and the FPC 405 can beequipped with lithium batteries. The batteriesback up the contents of the Random AccessMemory of the processor module when thecontroller is switched off or following a powerfailure.

In practice this means that the battery is re-quired to:

• back up the user program loaded in RAM(when you are not using an EPROM orEEPROM) and

• back up the status of flags, timer prese-lects, counters and registers.

When the controller is powered up the chargestatus of the battery is checked. An errormessage is generated in the event of the bat-tery failure. In the case of the FPC 103 andFPC 405 controllers, a message is generatedif the battery is "weak" and must be replacedas soon as possible.

Depending on the condition of the battery andthe duration of a battery failure, a power failurecan lead to a change or loss of contents of theRAM. The degree of change is random. Con-tents of memory are unreliable after a batteryfailure. However, as soon as the controller ispowered up again, change of RAM contents isshown by means of a system error message.

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254

For this reason application programs must bewritten to set all internal operands (flags,counters, timers and registers) to a definedstate following a voltage and battery failure. Amodule that sets all internal operands to 0 isenabled for each controller.

In the case of the IPC, the user programs canbe stored in a flash memory. The variable data(R, CW etc.) are written to a RAM memorysafe against power failure. Because of thesemeasures, the IPC does not require a battery.

In the case of the FEC, the user programs arestored in a flash memory. The variable data(R, CW etc.) are also written to the flashmemory safe against power failure. Becauseof these measures, the FEC does not requirea battery.

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255

B.8 INPUT SIGNAL DELAY

Input signal delay is implemented for all FestoPLCs in order to prevent the user from havingto take extensive interference protectionmeasures for all the input signal ports.

FPC 100B/AF

In the case of the FPC 100B/AF input signaldelay is software-implemented. The delay pro-gram is integrated into the operating system.Software implementation means that the inputsignal delay can be changed. The value for theinput signal delay is stored in register 63.Changing the value of this register changesthe delay for all inputs of the FPC 100B/AF.

In this instance only the low byte, i.e. the 8 low-order bits of the register, are evaluated. Thismeans that the value can be set to between 1and 255, with 1 as the shortest delay and 255as the longest delay. The contents of the highbyte are ignored.

R 63 Delay

0110

255

Longest delay (as 255), approx. 25 msShortest delay, less than 1 msDefault delay (sets automatically after poweron and battery failure), approx. 1 ms

Longest delay (as 0!), approx. 25 ms

Important: Increasing the input signal delayalso increases the cycle time for the proces-sor module. If a particular input really doeshave to be considerably delayed, program-ming of a timer is recommended rather thanthe use of register 63.

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256

FPC 405

In the case of the FPC 405 input signal delayfor the normal I/O modules is hardware-implemented (see FPC405 manual).

IPC

In the case of the IPC input signal delay issoftware-implemented (debounce time accord-ing to the cycel time can be switched ON/OFFby software).

FEC

In the case of the FEC input signal delay issoftware-implemented (5ms, additional de-bounce time according to the cycle time canbe set by software).

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Appendix C - Subroutines

257

Appendix C

Subroutines, Multitasking and

Multiprocessing

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258

Contents

C.1 MODULES .........................................265Which controller uses modules? .......265What are modules?............................266

C.2 MULTITASKING................................267Which controller supportsmultitasking?.......................................267What is multitasking? .........................267

C.3 MULTIPROCESSING........................272What is multiprocessing?...................272

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259

The possible applications of programmablelogic controllers are countless. Cleaning ma-chines for turned parts, baking machines forbread rolls, grinding machines for a coal-firedpower station, burner controller for a gas-heated power station, handling equipment fortubs of margarine, automatic welding ma-chines for hermetic compressors, automatictesting devices for heat exchangers.

The majority of these machines have featuresin common. If you examine the hardware andsoftware of such systems, you will find similarstructures – even if one system bakes breadrolls and the other manufactures pneumaticcylinders. Similarly there are common featuresin the operation of the systems. To some ex-tent operation is based on national and inter-national standards and to some extent onsimple generally recognized principles forsensible operator interfaces.

In most cases automated machines havecontrol elements such as

• EMERGENCY OFF• Start• Stop• Automatic• Manual• Acknowledge fault• Select type

(large or small rolls, large or small valves)

etc.

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260

In most cases these automated systems havedevices that assist the operators. Examplesare displays and signals (lamps, acoustic sig-nals, text displays, screens, flasher lamps,flashing lights, sirens etc.) that indicate

• Ready• Machine error• Controller error• Manual mode• Automatic mode• Type being produced

etc.

A program for a programmable logic controllercan be regarded as a series of rungs that aretranslated in a programming device to a seriesof program lines. Let us assume that your pro-gram for the bread making machine is 2000rungs long. The machine works well with yourprogram, the customer is happy, the rolls arewonderfully golden brown and taste delicious.

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261

A baker must also get up early in the morningto start work. After producing many thousandrolls there is a fault: when the first batch ofdough is to be processed a fault indicator illu-minates, the machine stops and has to be re-paired. It is 5.15 a.m.

What is to be done?

Our master baker fetches the printout of yourprogram to find out why the fault indicator ison. Somewhere in the 2000-rung programmust be an output called "Error" ...

We can leave the rest to your imagination.

Of course it would be helpful to give the masterbaker a list of all possible errors which wouldassist in providing a solution to our example.But even when the operating instruction anderror list are written with greatest care and at-tention, at some stage it will be necessary torefer to the program to find the fault.

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262

When this is necessary, it would be useful tohave a program that is easy to read and un-derstand, in which rungs which might be asso-ciated with the error can be located quickly.FST software offers several aids in this re-spect.

• You can enter a short comment for eachrung. A list of all rungs with these commentsis printed out at the beginning of your pro-gram forming a sort of table of contents forthe program.

Rung number 1Reset registers/start time

Rung number 2Generate flag edge for counting

Rung number 3Count

Rung number 4Interrogate counter after 3 seconds

• You can print out a cross-reference list ofall operands. This indicates which operandsare used in which rungs of the program.

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263

FST cross-reference list

FPC CCU P/B REF TYPE AbsoluteOperand

Symbol.Operand

Line/Rung/Comment

100 0 P00 5 LDR F15.15 EDGE 2 2 3

100 0 P00 5 LDR FI 1

100 0 P00 5 LDR R0 1 3 4 4 4

5 5 5

100 0 P00 5 LDR R1 1 4 5

100 0 P00 5 LDR R2 1 4 4 5

100 0 P00 5 LDR T0 1 3 4 4 5

5

• You can set jump labels in your program toindicate the beginning of a section. For ex-ample, the label "AUTO" is set at the be-ginning of the section for automatic se-quencing. "MANUAL" indicates the begin-ning of the manual program section,

"ERROR" the error messages etc.

Fig. C/1: Manual operation

• You can use modules, which can be calledup as subroutines at any point in your pro-gram.

Manual I1.1 O0.1Motor

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264

• Within a project you can use various pro-gram numbers and program names (assymbolic addresses for a program), andcall this as required.

• You can have several processor modulesworking together in one PLC as part of aproject.

• A large system can be divided up into sev-eral individual projects interconnected withthe aid of a network.

The use of subroutines is described in thesection modules.

Structuring a project using several programs isdescribed under the heading "Multitasking".

The use of several processor modules withina project is described under the heading"Multiprocessing".

The use of a network is described in a sepa-rate hand book.

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265

C.1 MODULES

Which controller uses modules?

Modules can be used in all Festo PLCs. Thenumber, selection and type of module is de-pendent on the type of controller:

Controller Program module Function module

FPC 100 B/AF 8 in any programming language CFM0

IPC 100 in any programmig language

FEC 100 in any programming language

FPC 405 32 written in LDR or Assembler CFM0 to CFM75

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266

What are modules?

Modules are subroutines. This means thatmodules are programs that can be called fromanother program. When a processor modulecalls a module, control passes from the callingprogram to the module and returns to the call-ing program after processing of the module.Nesting of modules – calling one module fromanother module – is not allowed with the FestoPLCs. However, the FPC 405 does allow call-ing of the same module from simultaneouslyexecuting programs.

Modules are created, edited, tested andloaded independently to great advantage.Various versions of a module can be createdand loaded as required.

Note that the use of JUMP commands withina module1 can result in control never beingpassed back to the calling program. Particu-lar care must be taken when using backwardjumps within a module.

1 and with the aid of a Step command or the PW commandwithin a module written in Statement list.

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267

C.2 MULTITASKING

Which controller supports multitasking?

Multitasking is the execution of several pro-grams in parallel within a project. Multitaskingis supported by the following controllers:

• FPC 100B/AF: 1 program 8 program modules

• IPC: 64 programs

• FEC: 64 programs• FPC 405: Up to 8 programs simultaneously

out of 64 stored programs

What is multitasking?

A conveyer system is to be operable in twomodes "Manual" and "Automatic". A selectorswitch on the control console allows the op-erating mode to be selected.

Within a FST project we give the programs forthese two operating modes two different num-bers, for example program number 1 forautomatic mode and program number 2 formanual mode.

Program number 0 is the organization pro-gram: dependent on the position of the selec-tion switch and of the machine it manageswhich operating mode is active. For example,it must only be possible to switch the machineto automatic mode when it is in its initial posi-tion.

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268

Therefore we have three programs:

Fig. C/2: Programs

The two programs for automatic and manualmode are typical of programs that are mutuallyexclusive. A machine must never operate inboth manual and automatic mode – the resultwould be chaotic.

The organization program must monitor theselector switch to see if the operating modesetting has been changed. This means that theorganization program must be executing con-tinuously, in parallel to either the manual orautomatic mode program.

Program No. 0: Organization

Program No. 2Manual

Program No. 1Automatic

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269

Additional Ladder diagram programs are al-ways started from program 0. For this reasonprogram 0 is generally the organization pro-

gram.

Fig. C/3: Organization program

The automatic program with the address P1(absolute address) can be used like any otherone-bit operand. It can be set, reset, or inter-rogated for logic 1 or logic 0.

Please note that control of the program in theabove rung is signal-edge controlled. In theabove rung the program is set from logic 0 tologic 1 the first time the condition changes.Switching on again – for example after havingbeen switched off from somewhere else –only takes place when the condition changesto logic 0 and then changes back to logic 1.

Condition P1AUTO

S

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270

When program P1 is set, programs P1 and P0execute simultaneously. Switchover occursafter each complete cycle through the Ladderdiagram program. In reality, the processor firstexecutes one program completely, then thesimultaneous program, then the first again etc.

In practice the most common case is a Ladderdiagram program working in parallel with aBASIC program either for data transmission toa host computer or for driving a terminal foroperator control.

FPC 405This controller allows 64 programs to bestored in the processor module. Up to 8 Lad-der diagram programs can be executed simul-taneously. The FPC 405 manual contains amatrix indicating how many of which programsin which language mix can be executed simul-taneously.

In practice it is likely there would be severalLadder diagram programs executing simulta-neously with a BASIC program for operatorguidance or a network.

FPC 100B/AF

This controller allows 1 program and 8 pro-gram modules can be stored in the processormodule. Up to 1 Ladder diagram programs and8 Ladder diagram program modules can beexecuted simultaneously.

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271

IPC

This controller allows 64 programs to bestored in the processor module. Up to 64 Lad-der diagram programs can be executed simul-taneously.

FECThis controller allows 64 programs to bestored in the processor module. Up to 64 Lad-der diagram programs can be executed simul-taneously.

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272

C.3 MULTIPROCESSING

The following controller supports multiproces-sing, that is the operation of multiple processormodules within a system (connected via asystem bus):

FPC 405 up to 6 processor modules on onebus

What is multiprocessing?

Each processor module of a programmablelogic controller consists basically of a micro-processor system. This includes the micro-processor itself and storage and peripheralmodules. In addition there are the connectionsto inputs and outputs, to the programmer etc.

This then represents a system with a singleprocessor. This processor executes eachprogram line in turn in the order prescribed bythe program. In addition the processor musthandle administrative tasks, counting forcounter modules, reacting to requests fromprogrammers and test equipment etc. All thistakes time.

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273

The result: the processor module needs timeto cycle through a program once. Severalmeasuring programs to measure the cycletime of a processor module are shown in Ap-pendix B, "Example programs".

Depending on the program size and CCUtype, this time problem can be significant. Theproblem can be alleviated by allowing severalprocessor modules to work in parallel.

In computer technology this method is used inparallel processors. But in the case of parallelprocessors, a single program is compiled insuch way that it is automatically distributed tothe various processors. The Festo PLCs offeryou the possibility of allowing several proces-sor modules to work within a common system.

Distribution of tasks and programs to the vari-ous processor modules is undertaken by theapplication program, that is by you.

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274

Fig. C/4: Example

Processor module No. 0Program No. 0Program No. 1

General tasksOrganizationOperator guidance with screen controlConnection of other CCU

Program 0:Program 1:Program 2:Program 3:

Processor module No. 1 ControlOrganizationManualAutomatic Type AAutomatic Type B

Processor module No. 2 PositioningDriving of 2 NC axes with servo motors

Processor module No. 3 FieldbusFieldbus control and addition control tasks

Processor module No. 4 Statistics / Collection of operating dataEvaluation and compression of operating data, data transfer to thehost computer

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275

Of course it is necessary for the variousprocessor modules to be able to "talk to eachother" – in other words exchange information.

This information exchange takes place in theFesto PLC with the aid of flags. The FPC 405operand parameter consists of:

Fig. C/5: Operand parameters

Each processor module can access all flagsof all processor modules (with the exception ofthe local flags of the FPC 405 processormodule). This allows quick and easy data ex-change.

F3 .12

Number of bit

. 4

Point separating bit and word

Number of word

Point separating processormodule and word(not for FPC100B/AF, IPCand FEC)

Number of CCU(not for FPC100B/AF, IPCand FEC)

Operand identifier(here F for flag)

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276

In addition, the FPC 405 allows each proces-sor module to start and stop programs execut-ing on other processor modules directly (thatis without the use of flags).

This represents a simple and convenient wayof dividing a machine project into varioussubtasks and distributing these to variousprocessor modules, all of which can accessthe same inputs and outputs.

With the FPC 405 you can select a certaintype of processor module to fit the task (e.g.field bus connection, additional serial inter-face, networking etc.).

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Appendix D - Binary and hexadecimal numbers

277

Appendix D

The binary and hexadecimal number system

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278

Contents

D.1 THE STRUCTURE OF NUMBERSYSTEMS ..........................................279

D.2 THE BINARY NUMBER SYSTEM ..282BCD code ...........................................284The hexadecimal number system......286Signed numbers..................................288

D.3 DIFFERENTIATION IN LADDERDIAGRAM ..........................................289

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279

D.1 THE STRUCTURE OF NUMBER SYSTEMS

The history of numbers and mathematics hasresulted in a wide range of number systems.The oldest known written number is supposedto be 30,000 years old. A general characteris-tic of the most widespread system – the deci-mal system – is the structure of places and thesignificance of these places. For example thenumber 4344 has the following structure:

4 x 1000 plus 3 x 100 plus 4 x 10 plus 4 x 1

This means that the digit "4" on the left has acompletely different meaning to the digit "4" onthe right (9301 is significantly more than1309). This is not the only type of numberstructure. The Roman number system workedin a completely different way. In the Romansystem, a new symbol was used as soon asthe number became too large. For exampleCXXI = 121. On the other hand, IXXC is incor-rect as the sequence does not coincide withthe meaning of the symbol.

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280

Back to the decimal number system.

The basis for the decimal number system isthe presence of 10 different digits (for thisreason decimal, decimum (Latin) = 10). It fol-lows that we can use 10 different symbols tocount from 0 to 9. As soon as we want to gopast 9, we carry over to the next position. Thisnext position has the significance 10 (=101). Inthis next position we can again count up to 9(that is 9 x 101 = 90). Then we need to carryover again to the next position with the signifi-cance 100 (=102).

If we take the number 71718711 as an exam-ple:

107

= 10 Mil106

= 1 Mil105

= 100000104

= 10000103

= 1000102

= 100101

= 10100

= 1

7 1 7 1 8 7 1 1

The table makes it clear that the 7 "on the left"means 7 times 10 million = 70 million, while the7 in the third position from the right means 7times 100 = 700.

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281

The position on the extreme right is called theleast significant position (because its value isleast significant) and the position on the ex-treme left is called the most significant position(because its value is most significant).

Using the 8 positions as in our example thehighest number we can create is 999999999,that is nearly 100 million. If we want to see themaximum number that can be represented witha given number of positions, we can simplytake the value of the next highest position,subtract 1 and that is the answer.

Example:The maximum number that can be representedby a 6-digit decimal number is 106-1 =1000000-1 = 999999. (106 is the seventhposition as 100 not the 101 is the first position).

What does this mean for the Festo PLC?Each word (for example, a register) can storea 4-digit decimal number with the aid of BCDcode. A 4-digit decimal number enables yourepresenting numbers up to 104-1 = 10000-1 =9999.

We could use this same pattern to developany amount of number systems. The basicstructure of the decimal number system canbe transferred to number systems with anynumber of digits. So it follows that all arithmeticoperations and methods that we use for deci-mal number systems can be also used forother number systems.

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282

D.2 THE BINARY NUMBER SYSTEM

Back in 1679 G. W. von Leibnitz fulfilled one ofthe basic conditions for the development of thecomputer by transferring the characteristics ofthe decimal number system to a form of calcu-lation using only two digits. This is because thecomputer only operates with two digits:"current on", "current off". These two statescan be represented as numbers: "1" and "0".Unless analogue signals are used, no othernumbers can be represented.

If we limit ourselves to two digits (0 and 1) thenumber system has the following structure:

27

= 12826

= 6425

= 3224

= 1623

= 822

= 421

= 220

= 1

1 0 1 1 0 0 0 1

The principle is the same as for the decimalnumber. But as only two digits are available,the significance of a position is not calculatedby 10x but by 2x. The least significant digit(extreme right) has the value 1 (exactly as inthe decimal system), the next position has thevalue 21 = 2 as opposed to 101 = 10 in thedecimal system.

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283

Using 8 positions (as in our decimal numberexample) we can represent a number of up toa maximum of 28-1 = 255. This would be rep-resented by the number 111111112.

Each position of the binary number can be oc-cupied by the digit 0 or 1. The smallest unit ofthe binary system is a bit.

In the above example a number has beencreated from 8 bits, that is, the bits have beenjoined together to form a byte (represented inthe computer as 8 electrical signals, each ofwhich denotes "current on" or "current off").

In the Festo PLCs, words generally have awidth of 16 bits, meaning that they can countfrom 00000000000000002 to11111111111111112. The highest possiblenumber that can be represented with 16 bits inthe binary system is 216-1 = 6553610-1 =6553510.

This is the reason why a timer can only meas-ure a time of up to 65535 times 10 millisec-onds = 655.35 seconds = 10 minutes and55.35 seconds. This is also the reason why anindividual counter can only count from 0 to65536 (or from 65535 to 0).

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284

BCD code

Normally, binary numbers are displayed to youas decimal numbers. The easiest method forthis is to use the BCD code. In BCD code,each individual digit of the decimal numbersystem is represented by the correspondingbinary number:

010 = 02

110 = 12

210 = 102

310 = 112

410 = 1002

510 = 1012

610 = 1102

710 = 1112

810 = 10002

910 = 10012

It follows that 4 positions of the binary numbersystem are required for the 9 digits of thedecimal number system. This wastes spaceas 4 positions in the binary number system al-low numbers up to 24-1 = 1510 to be repre-sented. However, this is acceptable to achievegreater clarity.

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285

The number 713310 is represented in BCDcode as:

0111 0001 0011 0011BCD.

This 4-digit decimal number therefore requires16 bits for representation in BCD code. BCD-coded numbers of this type are often used in7-segment displays or in encoding switcheswhich pass numbers to the control system. Forthis reason the command set of the FestoPLCs contains the conversion commandsDEB and BID. BID converts from binary todecimal and DEB converts from decimal to bi-nary. Please note that only 16 bits are avail-able in each case. This allows the representa-tion of a 4-digit decimal number in BCD code,i.e. a maximum of

999910 = 1001 1001 1001 1001BCD.

If you convert a larger number into BCD code,the most significant positions that don't fit willbe lost without a warning and without an errormessage.

Example:

DEB converts2400010

to BCD code0100 0000 0000 0000BCD,

which represents the last 4 decimal digits of24000, namely 400010.

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286

In FPC on-line mode this number

0100 0000 0000 0000BCD

is still understood as a binary number (onlydecimal and hexadecimal numbers can bedisplayed, not BCD), and this is therefore in-terpreted as

1638410.

If we convert this back with DEB (decimal tobinary) the number 400010 is written as a bi-nary number, namely

00001111101000002.

This is also displayed in FPC on-line mode as400010.

The hexadecimal number system

Reading binary numbers is very difficult for theinexperienced user. Reading numbers in BCDcode is much simpler but wastes a lot ofspace. For this reason the octal and hexa-decimal number system were developed. Inthe octal number system, 3 bits are joined to-gether. 3 bits allow representation of numbersfrom 010 to 710, 8 different digits. In the hexa-decimal number system, 4 bits are joined to-gether. 4 bits allow the representation of num-bers from 010 to 1510. This requires 16 differ-ent digits. The well known digits 0 to 9 areused, followed by the letters A, B, C, D, E andF.

F16 = 1510 = 11112 = 0001 0110BCD.

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287

In the same way as the decimal and binarysystem, a hexadecimal number is read as:

163

= 4096162

= 256161

= 16160

= 1

8 7 B C

which means:

8 · 163 + 7 · 162 + 11 · 161 + 12 · 160 = 3474810

As each hexadecimal digit consists of 4 bits,the 16 bits of a word of the Festo PLC canrepresent the hexadecimal number of up to 4positions. Therefore the highest number thatcan be represented with 16 bits is

FFFF16 = 6553510 = 11111111111111112.

In order to differentiate between decimal andhexadecimal numbers, hexadecimal numbersare prefixed with a $ when programming theFesto PLC.

Example:

V$1A2 = V418 = 00000001101000102

= 0000 0100 00011000BCD

or

V$2210 = V8720 = 00100010000100002

= 1000 0111 0010 0000BCD

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288

Signed numbers

Up to now we have assumed positive wholenumbers. We haven't taken into account thatthere is such a thing as negative numbers.

In order to work with negative numbers there isa convention that the most significant bit of abinary number is used to indicate the sign:1 corresponds to -0 corresponds to +.

As the most significant bit is used for the sign,signed numbers consist of one bit less, in ourcase maximum of 15 bits. It follows that thelargest number that can be represented in aFesto PLC with a signed number is±215 = +32767... -32768.

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289

D.3 DIFFERENTIATION IN LADDER DIAGRAM

Ladder diagram for Festo PLCs has the follow-ing conventions for differentiation of numbersystems:

1. In comparison operations (>, <, =, >=, <=,<>) an unsigned positive binary numberbetween 0 and 65535 is assumed. Nega-tive numbers must be converted for com-parison, unless the FPC 405 is switched tosigned numbers with CFM20.

2. All arithmetic operators (+, -, /, *) assumesigned binary numbers between 0 and±32767.

3. All bit-manipulating operations (BID, DEB,INV, CPL, AND, OR, EXOR) take all 16 bitsof a word into account. They do not treatthe most significant bit as a sign, but as abit.

4. Hexadecimal numbers are only unsigned,as only positive numbers are possible.

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290

Notes

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291

Index

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292

!

0-1 signal edge.....................................164 ; 1897-segment display .......................129 ; 131 ; 285

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293

A

Active serial port ...........................................252Address

Absolute ..................21 ; 145 ; 147 ; 153 ; 248Absolute (list of all possible) ......................155Absolute operands (rules for).....................147Counter .....................................................157Error (word)...............................................155Flag (word) ................................................156Function module ........................................155Function unit..............................................155Initialization flag.........................................155Input (word) ...............................................155Mixing absolute and symbolic ....................150Null operation ............................................157Output (word).............................................155Program ....................................................157Program module ........................................155Register ....................................................157Representation in printout..........................150Rules for symbolic addresses....................148Symbolic....................................21 ; 145 ; 148Timer.........................................................157

Allocation list ...................9 ; 15 ; 150 ; 152 ; 250AND, see Logic ...............................................86Application program.......................................273Arithmetic

Adding .........................................................91Dividing .......................................................93Functions ..................................................208Multiplying....................................................95Operators..................................23 ; 199 ; 289Subtracting ..................................................97

Arithmetic/Logic Box........................................62Assembler .......................................................11Automatic ......................................................233Auxiliary relay................................................203

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294

B

BASIC ....................................................11 ; 252Battery

Buffering......................................................33Failure.......................................33 ; 213 ; 253

BCD code ............................................199 ; 281Binary number .............................129 ; 131 ; 282Bit ........................................................153 ; 283

Manipulation ..............................................289Operand, see one-bit operand .....................24

Boolean operation...........................................37Boxes................................................34 ; 36 ; 62

Maximum number.........................................34Bus access ...................................................246Byte ..............................................................283

C

CCU................................................................10Central control unit ..........................................16Check routine.........................................44 ; 242Circuit diagram.....34 ; 37 ; 170 ; 172 ; 192 ; 203Coding switches....................................129; 131Coil .........................................................33; 177

Assignment................................................115Negated assignment..................................116Resetting...................................................113Setting.......................................................114

Command interpreter port..............................251Comment.........................................17 ; 64 ; 262Comparison...................................................208

Equal.........................................................117Greater than..............................................119Greater than or equal ................................121

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295

Less than ..................................................123Less than or equal.....................................125Operations .......................................199 ; 289Unequal .....................................................127

Complement ....................................................73Conditional part ...............................................37Contact ..................................................33 ; 177Control part ..........................................215 ; 216Counter .........................................23 ; 183 ; 283

Actual value......................................185 ; 186Bit .............................................................186Compare ...................................................185Counting....................................................189Decremental............23 ; 183 ; 188 ; 193 ; 195Event.........................................................183Incremental.......................23 ; 183 ; 191 ; 195Initialize .....................................................187Interrogate.................................................190Load counter word.....................................188Nominal value............................................185Possible operands.....................................187Preselect...................................31 ; 185 ; 186Programming ....................................191 ; 193Pulse.........................................................186Reset ...............................................185 ; 188Set ............................................................187Setting preselect .......................................139Word ................................. 23 ; 31 ; 186 ; 190Zero actual value.......................................187

CountingInterrogate.................................................189

Cross-reference list...................................9; 262Cycle time ............45 ; 46 ; 218 ; 221 ; 243 ; 273Cycle time measurement .................................46

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296

D

Decimal number...............................................23Decrementing................................................137Direct access

Advantages .................................................45Disadvantages ............................................44

Documentation ...........................................9 ; 18Double-word....................................................21

E

EEPROM ......................................................253EMERGENCY OFF .......................................232Encoding switch ............................................285EPROM.........................................................253Error.......................................................24 ; 147

List .........................................................9 ; 18Word ....................................................23 ; 27

Executive part .................................................37Existing flag chain .........................................214

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297

F

FI ................23 ; 39 ; 192 ; 194 ; 213 ; 216 ; 231Flag.............................................203 ; 213 ; 275

Bit ....................................................203 ; 204Word ................................................204 ; 207

Flashing outputs ..............................................42Function

Chart ...........................................................15Diagram.....................................................212Key .............................................................18

<F1>..................................................................... 17<F10> ................................................................... 18<F9>..................................................................... 18

Key allocation..............................................18Module ...............................69 ; 70 ; 245 ; 265Unit..............................................................27

G

Global allocation list ......................................250

H

Help key ..........................................................18Hexadecimal.........................29 ; 199 ; 286 ; 289

Number........................................................23High byte.........................................................67

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298

I

Import of data...........................................9 ; 246Incrementing.........................................137 ; 138Initialization flag.............23 ; 39 ; 213 ; 216 ; 231Input signal delay................200 ; 223 ; 248 ; 255Input word ................................................23 ; 27Internal

Flags .........................................................248Inputs ........................................................248Operands ..................................................248

Interrupt................................................227 ; 247Capability ..................................................247

Inverting ..........................................................71

J

Jump .............................................46 ; 110 ; 227Backward ..................................................241Label ..............................110 ; 112 ; 149 ; 263

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299

L

Ladder diagram ...............................11 ; 33 ; 270Editor ..........................................................18Program ......................................................16

Latch.............................................................107Dominant resetting ....................................108Dominant setting........................................109

Latching ...............................................215 ; 216Least significant position......................281 ; 282Line crossing...................................................33Lithium battery...............................................253Load............................................................9; 37

LOAD command ..........................................64LOAD TO.....................................................75

LocalAllocation list .............................................250Input ..........................................................248

LogicAND.............................................................86AND with words ...........................................88Exclusive OR...............................................76EXOR..........................................................76EXOR with three inputs ...............................77EXOR with words ........................................79Identity ........................................................81Identity with words, see "LOAD TO".............81Negation......................................................82Negation with words .............................71 ; 82NOT (at input)..............................................83NOT (at output)............................................82NOT with words ...........................................71Operation .............................................23 ; 37OR ..............................................................83OR with words............................................ 85

Long-word .......................................................21Low byte .........................................................67

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300

M

Machine code..................................................38Manual ..........................................................233Masking....................................................85 ; 88Matrix programming .........................................11Module .......................9 ; 23 ; 65 ; 69 ; 263 ; 265

/Program .....................................................16Nesting......................................................266Number........................................................16

Most significant bit ........................................288MS-DOS..........................................................15Multi-bit operand, see Word operand.............183Multiprocessing ...........................205 ; 246 ; 272Multiprocessor system ....................................45Multitasking .................................227 ; 244 ; 267

N

NegationOf words..................................................... 71

Network.........................................................264NOP................................................................90NOT, see Logic ...............................................82Null operation ..................................................90Numbering .......................................................38Numbers

Conversion BCD to digital .........................129Conversion digital to BCD .........................131Interrogation preselect achieved ...............133

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301

O

Octal .............................................................286One-bit operand ..............................................21On-line mode..........................................18 ; 218Operand .................................................10 ; 186

Address............................................145 ; 153Enter ...........................................................36Identifier ..................................145 ; 147 ; 153Missing........................................................36Parameter ........................................145 ; 153Retentive.....................................................39

Operating mode.............................................267Operation ........................................................36OR, see Logic.................................................83Organization program ....................................267Output .............................................................24

Word ....................................................23 ; 27

P

Page header ...................................................15Parallel

Branch...........................................33 ; 35 ; 84Coil.......................................................33 ; 35Connection..................................................37Maximum number.........................................33Processor .................................................273Programs...................................................267

Parameter .......................................................69PC.................................................................251Power

Failure.......................................33 ; 213 ; 253Part ..................................................215 ; 216Up ......................................................38 ; 246

Preselect, see Counter ...................................31Print ..................................................................9Printer drive ..................................................252

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302

Priority for bus access ..................................246Procedure .......................................................69Process image .......................38 ; 40 ; 223 ; 241

Advantages .................................................44Disadvantages ............................................45Method ........................................................44

Processor module10 ; 205 ; 218 ; 246 ; 248 ; 264Program ...................................9 ; 23 ; 244 ; 264

Load............................................................18Module .............................65 ; 245 ; 263 ; 265Number........................................................16Save ...........................................................18Structure ...................................................231

Programming and test device ........................251Project ...................................9 ; 149 ; 264 ; 267

Name...........................................................15Pulse timer, see Time....................................168

Q

Quasi-parallel processing ..............................244

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303

R

Reaction time................................................223Absolute in 0.1 ms .....................................225Longest possible time................................227Measuring ..........................................46 ; 223

Register ..........................................23 ; 29 ; 199Register 63 (FPC 100)..................................255Resetting sequence ......................................216Retentiveness....33 ; 177 ; 186 ; 200 ; 203 ; 213ROL ................................................................99ROR..............................................................101Rotate

Left..............................................................99Right..........................................................101

RS232C interface .........................................251Run/Stop switch .....................................38 ; 203Rung ........................................................33 ; 34

Number........................................................38Section........................................................33

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304

S

Safety routine.........................................44 ; 242Sequence

Program .............................................15 ; 211Program with counter.................................217Program with jump .....................................217

Sequencer.....................................................216Serial data transmission................................251Series connection ....................................37 ; 87Shift

Left (SHL)..................................................103Register ...........................................103 ; 105Right (SHR) ...............................................105

Sign........................................................73 ; 288Signal-edge recognition.................................164Signed....................................................23 ; 199Significance .........................................280 ; 282Simultaneous.................................................244

Execution, see Multitasking .......................267Standing 1................................................39 ; 43Start/Stop switch....................................38 ; 203Statement list ..................................................11Structure chart ................................................15Subdirectory....................................................15Subroutine...................................245 ; 263 ; 265

Nesting......................................................266Subroutines..............................................65 ; 69SWAP .............................................................67Switch-off delay, see Time ............................165Switch-on delay, see Time ............................165Symbolic address, see address..............21 ; 145Syntax test ......................................................18System bus ...................................................246

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305

T

Task..............................................................244Text display...................................................252Time..............................................................283

Box............................................................164Clock pulse................................................162Compare timer word ..................................178Digital time measurement ..........................162Error in measurement ................................162Flashing lamp ............................................174Initialization ...............................................164Longest time..............................................163Module ......................................................177Preselect...................................................177Pulse timer .......................................165 ; 168Quartz .......................................................161Requirement for operations .......................218Shortest time.............................................163Start .................................................141 ; 142Switch-off delay..............164 ; 165 ; 167 ; 172Switch-on delay.....164 ; 165 ; 166 ; 169 ; 171Word .........................................................177

Timer...............................................................23Bit .............................................................178Preselect.....................................................29Word ...........................................................31

Timer, see Time ..........................141 ; 142 ; 161Title page ........................................................15TO...................................................................64Twos complement............................................73

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306

U

Unsigned .......................................................199

V

Version..............................................................9Number........................................................17

W

Word......................................................23 ; 283Operand .............................21 ; 27 ; 183 ; 199Operation ....................................................62

Y

Yes function ....................................................81

Documents

FST Manual LDR.pdf