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Home » Source Code » rouiter design using
verilog » fsm_router.v
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From： rouiter design using verilog
Description：design router using verilog.design a 1x3 router
using verilog.
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/************************************************************************
MAVEN SILICON CONFIDENTIAL ‐ This is an unpublished,
proprietary work
of Maven Silicon Softech Pvt. Ltd., Bangalore, and is fully
protected
under copyright and trade secret laws. You may not view, use,
disclose,
copy, or distribute this file or any information contained
herein except
pursuant to a valid written license from Maven Silicon
Softech Pvt. Ltd.,
Bangalore
Design Name : router_1x3
Module Name : fsm_router
Date : 19/09/2009
Author : P R SIVAKUMAR
Email : [email protected] Company : Maven
Silicon, Bangalore www.vlsitraining.com
Version : 1.0 revision 0.0
************************************************************************/
//‐‐‐‐‐‐‐‐‐‐‐‐‐ STATE DEFINITIONS ‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐
`define DECODE_ADDRESS 4'd0
`define LOAD_FIRST_DATA 4'd1
`define LOAD_DATA 4'd2
`define LOAD_PARITY 4'd3
`define FIFO_FULL_STATE 4'd4
`define LOAD_AFTER_FULL 4'd5
`define WAIT_TILL_EMPTY 4'd6
`define CHECK_PARITY_ERROR 4'd7
//‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐ ‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐ ‐‐‐
module fsm_router ( clock,
busy,
fifo_empty,
fifo_full,
packet_valid,
data_in,
parity_done,
low_packet_valid,
detect_add,
write_enb_reg,
resetn,
lp_state,
ld_state, laf_state,
lfd_state,
full_state,
reset_int_reg
);
input clock;
input fifo_empty;
input fifo_full;
input packet_valid;
input [1:0] data_in;
input parity_done;
input low_packet_valid;
input resetn;
output busy;output detect_add;
output write_enb_reg;
output lp_state;
output ld_state;
output laf_state;
output lfd_state;
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output full_state;
output reset_int_reg;
// Port Signals
wire clock;
wire busy;
wire fifo_empty;
wire fifo_full;
wire packet_valid;
wire [1:0] data_in;
wire parity_done;
wire low_packet_valid;
wire resetn; wire write_enb_reg;
wire detect_add; // This signal stimulates the sampling
of address
wire lp_state; // indicates current_state is LOAD_PARITY
wire ld_state; // indicates cur_state is LOAD_DATA
wire laf_state; // indicates cur_state is
LOAD_AFTER_FULL
wire lfd_state; // indicates cur_state is
LOAD_FIRST_DATA
wire reset_int_reg; // resets internal registers to
initial zero value
wire full_state; // indicates cur_stateis FULL_STATE;
//internal signals
reg [2:0] cur_state;
reg [2:0] next_state;
always@(posedge clock) begin
if (resetn == 1'b0)
cur_state
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ff_sync.v
router_reg.vfsm_router.v
router_1x3.v
fifo_rtl.v
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next_state = `LOAD_DATA;
end
`WAIT_TILL_EMPTY : begin
if (fifo_empty == 1'b0)
next_state = `WAIT_TILL_EMPTY;
else
next_state = `LOAD_FIRST_DATA;
end
`CHECK_PARITY_ERROR : begin
next_state = `DECODE_ADDRESS;
end
default : next_state = `DECODE_ADDRESS;
endcase end
//Output Logic
assign detect_add = (cur_state==`DECODE_ADDRESS) ? 1'b1 :
1'b0;
assign ld_state = (cur_state==`LOAD_DATA) ? 1'b1 :
1'b0;
assign lp_state = (cur_state==`LOAD_PARITY) ? 1'b1 :
1'b0;
assign lfd_state = (cur_state==`LOAD_FIRST_DATA) ? 1'b1 :
1'b0;
assign reset_int_reg = (cur_state==`CHECK_PARITY_ERROR) ?
1'b1 : 1'b0;
assign laf_state = (cur_state==`LOAD_AFTER_FULL) ? 1'b1 :
1'b0;
assign full_state =(cur_state==`FIFO_FULL_STATE);
assign write_enb_reg = ((cur_state == `LOAD_DATA) ||
(cur_state == `LOAD_AFTER_FULL) ||
(cur_state == `LOAD_PARITY)) ? 1'b1 : 1'b0;
assign busy = ((cur_state == `FIFO_FULL_STATE) ||
(cur_state == `LOAD_FIRST_DATA) ||(cur_state ==
`LOAD_AFTER_FULL) ||
(cur_state == `LOAD_PARITY) ||
(cur_state == `CHECK_PARITY_ERROR) ||
(cur_state == `WAIT_TILL_EMPTY)) ? 1'b1 : 1'b0;
endmodule
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