FSM Word Problems

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FSM Word ProblemsFSM Word Problems

Notes: Review for Test #2 – Monday

Studio #8: Reading assignment is due next week

Today:• First Hour: Finite string recognizer, Complex counter

– Section 8.5 of Katz’s Textbook

– In-class Activity #1

• Second Hour: Traffic signal controller, Digital combination lock

• Section 8.5 of Katz’s Textbook

– In-class Activity #2

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Katz Material not CoveredKatz Material not Covered

CoCO doesn't cover everything in Katz.CoCO doesn't cover everything in Katz.

Omitted material includes:

ASM charts

The ABEL language

all of Chapter 9 is skipped

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Word ProblemsWord Problems• One of the most difficult problems is making an

imprecise description of a finite state machine into a precise one.

• Have you covered all the states?

• Omissions can cause failures, crashes, death and destruction, etc.

• This is the Hardware equivalent of a Software programming error.

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Finite String RecognizerFinite String Recognizer

• One input: X

• One output: Z

• Description:

– Z is 1 if the 3 previous input bits are 010, and 100 has never been seen.

• Unstated assumptions:

– RESET starts the FSM at the "reset" state

– Z is asserted when the following bit is seen.A Moore Machine implementation.

Serial Finite State MachineSerial Finite State Machine

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ExampleExample

• X: 0 0 1 0 1 0 1 0 0 1 0

• Z: - 0 0 0 1 0 1 0 1 0 0 0

• Z is 0 even though the three previous inputs are Z is 0 even though the three previous inputs are 010, 010, because 100 was seen earlier.because 100 was seen earlier.

Serial BehaviorSerial Behavior

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S0 [0]

S1 [0]

S2 [0]

S3 [1]

S4 [0]

S5 [0]

S6 [0]

Reset

0 1

1 0

0 00,1

Formal DesignFormal Design

• Create sequences of states for the strings that the machine recognizes:

010 010 andand 100 100.

• Note we reset to S0S0.

• Consider the unlabelled transitions.

State Transition DiagramState Transition Diagram

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S0 [0]

S1 [0]

S2 [0]

S3 [1]

S4[0]

S5 [0]

S6 [0]

Reset

01?01?

100100

010010

1

0

State S3State S3

• Where do we go from S3S3?

• A 1 means the last 3 bits are 101101, so go to S2S2.

• A 0 means we’ve seen 100100, so go to S6S6.

0 1

1 0

0 0 0,1

Diagram DevelopmentDiagram Development

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S0 [0]

S1 [0]

S2 [0]

S3 [1]

S4 [0]

S5 [0]

S6 [0]

Reset

0 1

100

0,10

0

01

10?0?

States S1 and S4States S1 and S4

• Loop in S1S1 until we see our first 11.

• Loop in S4S4 until we see our first 00.

01?01?

100100010010

1?1?


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States S2 and S5States S2 and S5

• S2S2 means the last 2 bits are 0101, which may be a prefix of 010010.

• If the next bit is 1, the last 2 bits are now 1111, maybe a prefix of 100100. That’s S4S4.

• S5S5: Last 2 bits are 1010. If next bit is 1, maybe that’s a prefix for 010010. Go to S2S2.

S0 [0]

S1 [0]

S2 [0]

S3 [1]

S4 [0]

S5 [0]

S6 [0]

Reset

00 1

1

0

0,1

00

0 1 10?10?

1

11

1?1?

0?0?

01?01?

100100010010


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Review of Design StepsReview of Design Steps

• Write sample inputs and outputs to understand it.

• Write sequences of states and transitions for the strings that the FSM is to recognize.

• Add missing transitions, using existing states when possible.

• Verify that the state diagram matches the FSM.

Katz's MethodKatz's Method

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Complex CounterComplex Counter

• Design a 3-bit counter, with one input bit, a mode, MM.

• If M = 0M = 0, step to the next binary number in the sequence 000, 001, 010, 011, 100, 101, 110, 111, …

• If M = 1M = 1, step to the next Gray code number in the sequence 000, 001, 011, 010, 110, 111, 101, 100, ...

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Try Some Sample InputsTry Some Sample Inputs

• Note that we can switch modes at any time.

Mode Input M0011100

CurrentState

0 0 00 0 10 1 01 1 01 1 11 0 11 1 0

Next State(Z2 Z1 Z0)

0 0 10 1 01 1 01 1 11 0 11 1 01 1 1

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ResetS0

[000]

S1 [001]

S2 [010]

S3 [011]

S4 [100]

S5 [101]

S6 [110]

S7 [111]

0

0

0

1

1

0

0

01

1

11

1

1

10

0

Formal Formal RepresentationRepresentation

• One state for each output combination

• Add appropriate arcs for the mode control

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Do Activity #1 NowDo Activity #1 Now

S0 [0]

S1 [0]

S2 [0]

S3 [1]

S4 [0]

S5 [0]

S6 [0]

Reset

00 1

1

0

0,1

00

0 1 10?10?

1

11

1?1?

0?0?

01?01?

100100010010

ResetS0

[000]

S1 [001]

S2 [010]

S3 [011]

S4 [100]

S5 [101]

S6 [110]

S7 [111]

0

0

0

1

1

0

0

01

1

11

1

1

10

0FSM String RecognizerComplex Counter

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Traffic Light ControllerTraffic Light Controller• A busy highway is intersected by a little used farmroad.

• Detectors CC sense the presence of cars waiting on the farmroad.

• With no car is on farmroad, the lights remain GreenGreen in the highway direction.

• If vehicle is on the farmroad, highway lights go from GreenGreen to YellowYellow to RedRed, allowing the farmroad lights to become GreenGreen.

• These stay GreenGreen only as long as a farmroad car is detected but never longer than a set interval.

• When these are met, farm lights transition from GreenGreen to YellowYellow to RedRed, allowing highway to return to GreenGreen.

• Even if farmroad vehicles are waiting, the highway gets at least a set interval as GreenGreen.

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Diagram of IntersectionDiagram of Intersection

Highway

Highway

Farmroad

Farmroad

HL

HL

FL

FL

CC

CC

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Available TimersAvailable Timers

• Assume you have an interval timer that generates a short time pulse (TSTS) and a long time pulse (TLTL) in response to a start timer (STST) signal.

• TSTS is to be used for timing YellowYellow lights and TLTL for GreenGreen lights

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Tabulate Inputs & OutputsTabulate Inputs & Outputs

Input SignalresetresetCCTSTSTLTL

Output SignalHGHG, , HYHY, , HRHRFGFG, , FYFY, , FRFRSTST

Descriptionplace FSM in initial statedetect vehicle on farmroadshort time interval expiredlong time interval expired

Descriptionassert green/yellow/red highway lightsassert green/yellow/red farmroad lightsstart timing a short or long interval

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Tabulate Unique StatesTabulate Unique States

• Some light configurations imply others.

StateS0S1S2S3

DescriptionHighway green (farmroad red)Highway yellowyellow (farmroad red)Farmroad green (highway red)Farmroad yellowyellow (highway red)

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List AssumptionsList Assumptions

• Reset places timer in S0, highway green and farmroad red.

• Reset also starts the timer.

• Stay in S0 as long as no one is on the farmroad.

• Even if there is a farmroad vehicle, the highway stays green at least long as the long time interval.

• (Unstated in Katz) There will never be a bicycle or pedestrian on the farmroad.

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Traffic Signal State DiagramTraffic Signal State Diagram

Reset

TL + C

S0TL•C/ST

S1 S3

S2

S0: HG

S1: HYHY

S2: FG

S3: FYFY

TL: long time interval expired

C: detect vehicle on farmroad

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Reset

TL + C

S0TL•C/ST

TS

S1 S3

S2

TS/ST

S0: HG

S1: HYHY

S2: FG

S3: FYFY

TS: short time interval expired

ST: start timing a short or long interval

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Reset

TL + C

S0TL•C/ST

TS

S1 S3

S2

TS/ST

TL + C/ST

TL • C

S0: HG

S1: HYHY

S2: FG

S3: FYFY

TL: long time interval expired

C: detect vehicle on farmroadST: start timing a short or long interval

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Reset

TL + C

S0TL•C/ST

TS

S1 S3

S2

TS/ST

TS/ST

TL + C/ST

TS

TL • C

S0: HG

S1: HYHY

S2: FG

S3: FYFY

TS: short time interval expiredST: start timing a short or long interval

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Combination LockCombination Lock• 3 bit serial lock controls entry to locked room.

• Inputs are RESET, ENTER, 2 position switch for bit of KEY data.

• Locks generates an UNLOCK signal when KEY matches internal combination.

• ERROR light illuminated if KEY does not match combination.

• Sequence is:

– (1) Press RESET,

– (2) enter KEY bit,

– (3) Press ENTER,

– (4) repeat (2) & (3) two more times.

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Incomplete SpecificationIncomplete Specification

• Problem specification is incomplete:

– how do you set the internal combination?

– exactly when is the ERROR light asserted?

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Why is it just possibly a bad idea to indicate an error immediately on seeing the first bad bit ?

Why is it just possibly a bad idea to indicate an error immediately on seeing the first bad bit ?

Make AssumptionsMake Assumptions• Make reasonable assumptions, decide whether

– combination is hardwired into logic or stored in a register?

– error is asserted as soon as an error is detected or waits until the full combination has been entered?

Our design: combination is stored in a register and error is asserted after the full combinationhas been entered

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Block Diagram of LockBlock Diagram of Lock

Inputs: Reset Enter Key-In L0, L1, L2

Outputs: Unlock Error

UNLOCK

ERROR

RESET

ENTER

KEY -IN

L 0

L 1

L 2

Combination Lock FSM

Operator DataOperator Data

InternalCombination

InternalCombination

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Enumerate the StatesEnumerate the States

• What sequences lead to opening the door?

• Do error conditions on a second pass …

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State State Diagram of Diagram of

LockLock

EnterEnter

Comp1 Error1

KI L1KI = L1

EnterEnter

EnterEnter

Idle1 Idle1'

Comp2 Error2

KI L2KI = L2

Done

[Unlock]

Error3

[Error]

Reset

ResetReset

Reset

StartStart

Reset

Reset + Enter

Reset • Enter

Start

Comp0

KI = L0 KI L0

EnterEnter

Idle0 Idle0'

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Do Activity #2 NowDo Activity #2 NowDue: End of Class Today.

RETAIN THE LAST PAGE(S) (#3 onwards)!!

For Next Class:• Bring Randy Katz Textbook, & TTL Data Book

• Required Reading:– Sec 11.1-11.3, skim 11.2 of Katz, omit the ABEL and

ASM descriptions

• This reading is necessary for getting points in the Studio Activity!

Documents

FSM Word Problems