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Young Won Lim11/6/15
FSM Examples
Young Won Lim11/6/15
Copyright (c) 2011 – 2015 Young W. Lim.
Permission is granted to copy, distribute and/or modify this document under the terms of the GNU Free Documentation License, Version 1.2 or any later version published by the Free Software Foundation; with no Invariant Sections, no Front-Cover Texts, and no Back-Cover Texts. A copy of the license is included in the section entitled "GNU Free Documentation License".
Please send corrections (or suggestions) to [email protected].
This document was produced by using OpenOffice and Octave.
FSMExamples
3 Young Won Lim11/6/15
Latches and FF's
FSMExamples
4 Young Won Lim11/6/15
FSM Inputs and Outputs
LA
LA
LB
LB
TB
TB
TA
TA
Traffic Lights - Outputs
LA
LB
Sensor - Inputs
TB
TA
FSMExamples
5 Young Won Lim11/6/15
States
LA
LA
LB
LB
LA
LA
LB
LB
LA
LA
LB
LB
LA
LA
LB
LB
TB
TA
=0
=0
TA =1
TB =1
FSMExamples
6 Young Won Lim11/6/15
Moore FSM State Transition Table
1
1
0
0
0
1
0 X 0
1 X X
0 1 X
0 0 X
1 X X
0 X 1
S0
TA
TB
S'1
1
0
0
0
1
1
S1
1
0
0
1
0
0
S'0
1
1
0
0
0
1
0 X 0
1 X X
0 1 X
0 0 X
1 X X
0 X 1
S0
TA
TB
S'1
1
0
0
0
1
1
S1
S1 S0
S1 S0T B
S1 S0T B
S '1 = S1 S0 + S1S0
= S1 + S0
0 X 0
1 X X
0 1 X
0 0 X
1 X X
0 X 1
S0
TA
TB
1
0
0
0
1
1
S1
1
0
0
1
0
0
S'0
S1 S0T A
S1 S0T B
S '0 = S1S0T A + S1 S0T B
FSMExamples
7 Young Won Lim11/6/15
States
000110
0
0
1
1
1 1 0
0 1 0
1 0 1
0 0 0
S2L
A1L
A0L
B1
1
1
0
0
S1
1
0
0
0
LB0
1 1
0 1
1 0
0 0
S2L
A1
1
1
0
0
S1
LA1=S1
1 0
0 0
1 1
0 0
S2
LA0
1
1
0
0
S1
LA0=S1S0
0
0
1
1
1
0
1
0
S2
LB1
1
1
0
0
S1
1
0
1
0
S2
1
1
0
0
S1
1
0
0
0
LB0
LB1=S1 LA0=S1S0
FSMExamples
8 Young Won Lim11/6/15
Moore FSM (1)
D Q
D Q
S'1
S'0
S1
S0
TA
TB
LA1
LA0
LB1
LB0
S1
S0
clk
Current State
Next State
inputs
outputs
states00: S001: S110: S211: S3
outputs (LA/LB)00: Green01: Yellow10: Red11: X
NextSt
CurrSt
Compute NextSt from CurrSt, Ta, Tb
This NextSt becomes a new CurrSt
Compute NextSt
CurrSt <= NextSt
FSMExamples
9 Young Won Lim11/6/15
Moore FSM
D Q
D Q
S'1
S'0
S1
S0
TA
TB
S'1 = S1 + S0
S '0 = S1S0T A + S1 S0T B
LA1
LA0
LB1
LB0
LA1=S1
LA0=S1S0
LB1=S1
LB0=S1S0
Next States
Outputs
S'0 = S1S0T A
+ S1 S0T B
S'1 = S1 + S0
Inputs TA
TB
Current State S1
S0
S1
S0
Current State S1
S0
LA1=S1
LA0=S1S0
LB1=S1
LB0=S1S0
clk
Current State
Next State
inputs
outputs
states00: S001: S110: S211: S3
outputs (LA/LB)00: Green01: Yellow10: Red11: X
FSMExamples
10 Young Won Lim11/6/15
Verilog Gate Level Design - testbench
`timescale 1ns/100ps
module traffic_controller_testbench;
parameter cycle = 40;
reg clock;
always begin #(cycle/2) clock=~clock; end
traffic_controller DUT (.clock(clock), .reset(reset), .TA(TA), .TB(TB), .LA(LA), .LB(LB) );
reg reset; reg TA, TB; wire [1:0] LA, LB;
initial begin clock = 1; reset = 1; TA = 1; TB = 0;
#1; #(cycle) reset = 0;
#(cycle) TB = 1; #(cycle) TA = 0; #(cycle*3) TA = 1; TB = 0; #(cycle*3) TA = 0; end
initial begin $dumpfile("traffic.vcd"); $dumpvars(0, DUT); #(cycle * 10); $finish; end
endmodule
FSMExamples
11 Young Won Lim11/6/15
module traffic_controller(clock, reset, TA, TB, LA, LB); input clock, reset; input TA, TB; output [1:0] LA, LB;
reg [1:0] S; wire [1:0] NextS;
always @(posedge clock) begin: SEQ if (reset) #8 S = 2'b00; else
#8 S = NextS; end
not #8 (S1b, S[1]); not #8 (S0b, S[0]); not #8 (TAb, TA); not #8 (TBb, TB);
xor #8 (NextS[1], S[1], S[0]); or #8 (NextS[0], NS1, NS2); and #8 (NS1, S1b, S0b, TAb); and #8 (NS2, S[1], S0b, TBb);
buf #8 (LA[1], S[1]); and #8 (LA[0], S1b, S[0]); not #8 (LB[1], S[1]); and #8 (LB[0], S[1], S[0]);
endmodule
Verilog Gate Level Design – traffic_gate.v
FSMExamples
12 Young Won Lim11/6/15
VCD Output with zero delay
FSMExamples
13 Young Won Lim11/6/15
VCD Output with gate delays
FSMExamples
14 Young Won Lim11/6/15
VCD Output with gate delays
Output Delay
FSMExamples
15 Young Won Lim11/6/15
Divide By N Counter FSM
S0 S1
S2
Y=1 Y=0
Y=0
reset Input: none
S1Output: Y=1 every 3 cycles
S2
S1
S0
Curr St
S0
S2
S1
Next St
S2
S1
S0
Curr St
0
0
1
Output
State Transition Table Output Table
FSMExamples
16 Young Won Lim11/6/15
Encoding States
S2
S1
S0
Curr St
S0
S2
S1
Next St
S2
S1
S0
Curr St
0
0
1
Output
State Transition Table Output Table
0
1
0
1 0
0 1
0 0
0
0
1
1 0
0 1
0 0
0
0
1
S0
S'1
S1
S'0
S0 YS
1
S '1=S1S0
S '0=S1 S0
Y=S1S0
S2
S1
S0
Curr St
S0
S2
S1
Next St
S2
S1
S0
Curr St
0
0
1
Output
State Transition Table Output Table
0
1
0
1 0 0
0 1 0
0 0 1
0
0
1
1
0
0
1 0 0
0 1 0
0 0 1
0
0
1
S0
S'2
S2
S'0
S0 YS
2
S '2=S2 S1 S0 Y=S2 S1S0
S1
S1
S'1
S '1=S2 S1 S0
S '0=S2 S1 S0
⇒ S1
⇒ S0
⇒ S2
⇒ S0
FSMExamples
17 Young Won Lim11/6/15
Resolution Time
FSMExamples
18 Young Won Lim11/6/15
FF Timing (Ideal)
D Q
D Q
D Q
D Q
D3
D2
D1
D0
Q3
Q2
Q1
Q0
D3:0
Q3:0
Inputs to FFs
Outputs of FFs
Q3
Q2
Q1
Q0
D3
D2
D1
D0
CLK
Register
Inpu
ts to
FF
s
Out
puts
of F
Fs
FSMExamples
19 Young Won Lim11/6/15
Sequence of States
Q(t+1) Q(t+2) Q(t+3) Q(t+4) Q(t+5)Q(t)
D3:0
Q3:0
(t+1)th edge
(t+2)th edge
(t+3)th edge
(t+4)th edge
(t+5)th edge
(t)th edge
Inputs to FFs
Outputs of FFs
? ? ? ? ? ?
Q(t+1) Q(t+2) Q(t+3) Q(t+4) Q(t+5)Q(t)
D3:0
Q3:0
Find inputs to FFs
which will make outputs in this sequence
(t+1)th edge
(t+2)th edge
(t+3)th edge
(t+4)th edge
(t+5)th edge
(t)th edge
FSMExamples
20 Young Won Lim11/6/15
When NextSt becomes CurrSt
NextSt
CurrSt
Compute NextSt from CurrSt, Ta, Tb
This NextSt becomes a new CurrSt
Compute NextSt
CurrSt <= NextSt
FSMExamples
21 Young Won Lim11/6/15
Finding FF Inputs
? ? ? ? ? ?
Q(t+1) Q(t+2) Q(t+3) Q(t+4) Q(t+5)Q(t)
D Q
D Q
D Q
D Q
D3:0
Q3:0
D3
D2
D1
D0
Q3
Q2
Q1
Q0
Inputs
Inputs to FFs
Outputs of FFs
During the tth clock edge period,
Compute the next state Q(t+1) using the current state Q(t) and other external inputs
Place it to FF inputs
After the next clock edge, (t+1)th, the computed next state Q(t+1) becomes the current state
FSMExamples
22 Young Won Lim11/6/15
Method of Finding FF Inputs
Q(t+1) Q(t+2) Q(t+3) Q(t+4) Q(t+5) Q(t+6)
Q(t+1) Q(t+2) Q(t+3) Q(t+4) Q(t+5)Q(t)
D Q
D Q
D Q
D Q
D3:0
Q3:0
D3
D2
D1
D0
Q3
Q2
Q1
Q0
Inputs
Q3
Q2
Q1
Q0
I D3
Q3
Q2
Q1
Q0
I D3
Q3
Q2
Q1
Q0
I D3
Q3
Q2
Q1
Q0
I D3
Find the boolean functions D3, D2, D1, D0in terms of Q3, Q2, Q1, Q0, and external inputsfor all possible cases.
FSMExamples
23 Young Won Lim11/6/15
State Transition
Q(t+1)
Q(t+1)Q(t)
D3:0
Q3:0
Q(t
)
Q(t
+1)
Inputs
Q(t+1)
Q(t+1)Q(t)
Inputs
Compute the next stateusing the current state and external inputsin the current clock cycle
After the next clock edge, the computed next state (FF Inputs) becomes the current state (FF Outputs)
FSMExamples
24 Young Won Lim11/6/15
Moore FSM
1
clock
INPUT StateRegister
Next StateCombinational
Logic
Output Combinational
Logic
OUTPUT
D Q D Q D Q
D Q D Q D Q
FSMExamples
25 Young Won Lim11/6/15
Mealy Machine
1
clock
INPUT StateRegister
Next StateCombinational
Logic
Output Combinational
Logic
OUTPUT
D Q D Q D Q
D Q D Q D Q
Young Won Lim11/6/15
References
[1] http://en.wikipedia.org/[2] M. M. Mano, C. R. Kime, “Logic and Computer Design Fundamentals”, 4th ed.[3] J. Stephenson, Understanding Metastability in FPGAs. Altera Corporation white paper. July 2009.