Front Matter 7675

8/6/2019 Front Matter 7675

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CMOS PLLs and VCOs for 4G Wireless


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CMOS PLLs AND VCOs

FOR 4G WIRELESS

ADEM AKTASAnalog VLSI LabThe Ohio State UniversityColumbus Ohio USA

MOHAMMED ISMAIL

CTO and Co-FounderSpirea AB Stockholm* on leave from the Analog VLSI LabThe Ohio State UniversityColumbus USA

KLUWER ACADEMIC PUBLISHERS

NEW YORK, BOSTON, DORDRECHT, LONDON, MOSCOW


3/19

eBook ISBN: 1-4020-8060-3Print ISBN: 1-4020-8059-X

Print 2004 Kluwer Academic Publishers

All rights reserved

No part of this eBook may be reproduced or transmitted in any form or by any means, electronic,mechanical, recording, or otherwise, without written consent from the Publisher

Created in the United States of America

Boston

2004 Springer Science + Business Media, Inc.

Visit Springer's eBookstore at: http://www.ebooks.kluweronline.comand the Springer Global Website Online at: http://www.springeronline.com


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This book is dedicated to

Gulin & Fatih

and

Sameha Ismail Sr. Tuula

IsmailJr. and Omar


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Contents

Dedication

List of Figures

List of Tables

Preface

List of Acronyms

v

xi

xvii

xix

xxiii

1. INTRODUCTION

1

2

3

4

5

4G Wireless Terminals

4G PLL/VCO Design Challenges

Objectives

Organization of This book

Summary

1

1

4

6

7

8

92. OVERVIEW OF VCO/PLL FOR WIRELESS COMMUNICATION

1

2

3

4

Oscillator Overview

PLL Frequency Synthesis

Phase Noise Specification

Summary

3. PLL PHASE NOISE ANALYSIS

1

23

4

Phase Noise Definition

Oscillator Noise CharacteristicsPLL Noise Analysis

Summary

10

12

17

20

21

21

2527

40


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viii CMOS PLLs AND VCOs FOR 4G WIRELESS

4. BROADBAND VCOs: SYSTEM DESIGN CONSIDERATIONS

1

2

3

Radio Architecture and Frequency Planning Considerations

CMOS System Integration

Summary

5. BROADBAND VCOs: CIRCUIT DESIGN CONSIDERATIONS

1

2

34

5

Broadband VCO with Subbands

Switching Techniques for Broadband Operation

Broadband VCO Implementation

Resonator Tank Design

Summary

6. BROADBAND VCOs: PRACTICAL DESIGN ISSUES

1

2

3

45

6

7

PVT Variation Effects on VCO Tuning

Tuning Range Calibration (Trimming)

External Trimming

Auto Calibration (or Self Trimming)Proposed Auto Calibration Technique

VCO Pulling In the Integrated Enviroment

Summary

7. 4GHz BROADBAND VCO: A CASE STUDY

1

2

3

4

5

Design Objectives

Circuit Topologies

VCO Tuning

Characterization and Measurement Results

Summary

8. A PLL FOR GSM/WCDMA

1

2

34

5

Frequency Plan and System architecture

Dual band VCO Design for Dual Mode Operation

Integer-N ArchitectureImplementation of the Integer-N Architecture

Summary

9. PLLs FOR IEEE 802.11 a/b/g WLANs

1

2

Why Multi-band Tri-mode WLANs?

Frequency Plan Radio Architecture and PLL Specifications

41

42

44

50

51

51

52

61

67

74

77

79

80

80

8082

85

91

93

93

94

96

98

106

107

107

109

113115

117

119

119

120


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Contents

3

4

5

6

7

8

Phase Noise Optimization and Trade-offs

Loop Filter Design

The RF (LO1) Synthesizer Implementation

The IF (LO2) Synthesizer Implementation

Measured Results

Summary

10. RF CMOS COMPONENT CHARACTERIZATION

1

2

3

4

5

6

7

8

Calibration and Measurement Techniques

Pad De-embedding

Pad De-embedding Considerations for RF CMOS

Probe Pad Layout Techniques

Measurement Environment Setups

RF CMOS Test Chip

Measurement Results and Technology Evaluation

Summary11. CONCLUSIONS

Appendices

A S-parameters to Y-parameters Transformation

References

Index

ix

123

126

130

139

145

145

149

150

151

152

152

154

158

159

163

165

167

167

169

175


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List of Figures

1.1

1.2

1.3

1.4

1.5

2.1

2.2

2.3

2.4

2.5

2.6

2.7

3.1

3.2

3.3

3.4

3.5

3.6

4G wireless terminals.

4G wireless: convergence and mobility/bit rate trade-off.

Proliferation of short distance wireless within 4G.

A multi-standard device architecture is depicted in a

multi-standard wireless network. A single chip SoC is

assumed for the baseband/MAC parts. Different radios

are used for different standards.

Reverse interconnect scaling in deep sub-micron CMOS [12].

A typical heterodyne receiver architecture.

Definition of VCO gain or sensitivity.

A typical phase-locked loop architecture.

PLL as a negative feedback model.

(a) PLL linear model (b) Three element passive loop filter.

PLL Bode plots.

LO phase noise specification

The oscillator output spectrum of an ideal oscillator (a)

and a practical oscillator (b).

Phase noise definition.

Sidebands around carrier due to (a) AM (b) PM.

VCO phase noise characteristics (a) low-Q case (b)

high-Q.

Noise characteristics of a MOS transistor at a fixed bias

condition.

PLL noise model.

2

3

4

6

7

10

11

13

13

14

16

19

22

23

25

26

26

28


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xii CMOS PLLs AND VCOs FOR 4G WIRELESS

3.7

3.8

3.9

3.10

3.11

3.12

3.13

3.14

3.15

3.16

3.17

3.18

4.1

4.2

4.3

4.4

4.5

5.1

5.2

5.3

5.4

(a) transfer function for reference divider PFD and CP

noises (b) transfer function for the VCO and the controlline noises.

PLL bandwidth selection (a) optimum (b) too large (c)

too narrow.

Typical PLL output phase noise.

Developed linear PLL model for noise calculation

(a) Divider noise simulation setup (b) Simulated SSB

noise of divide-by-8 prescaler circuit.

PFD with charge pump.

The intended open-loop behavior of the PLL.

The actual open-loop behavior of the PLL due to high

VCO gain.

Comparison of simulated and measured output phase

noise of 4GHz PLL at 3.84GHz for

The simulated total phase noise of 4GHz PLL at 3.84GHz

along with noise contributions from the PLL blocks.Comparison of simulated and measured output phase

noise of 4GHz PLL at 3.84GHz for

The open-loop behavior of the PLL for

Receiver architecture for multi-band and multi-standard

cellular applications.

Receiver architectures for WLAN applications at the

2.4GHz ISM band.

An integer-N PLL frequency synthesizer architecture.

(a) VCO and CP connections through loop filter (b)

Desired operation region for VCO tuning curve (c) CP

output current as a function of output voltage.

(a) single continiuos tuning curve (b) tuning curve di-vided into sub-bands.

Different approaches for broadband VCO with subbands

(a) switching inside the LC-tank (b) switching between

LC-tanks (c) switching between VCOs.

NMOS transistor as an RF switch (a) VSW is low the

OFF state (b)VSW is highthe ON state.

Differential capacitance switching.

Differential capacitance switching (a) with resistor bi-

asing (b) with MOS biasing.

30

30

31

32

34

34

37

37

38

38

39

39

42

43

43

48

49

53

55

55

56


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List of Figures xiii

5.5

5.6

5.7

5.8

5.9

5.10

5.11

5.12

5.13

5.14

5.15

5.16

5.17

6.1

6.2

6.3

6.4

6.5

6.6

6.7

6.8

Band switching circuit (a) simplified schematic (b) Tun-

ing curves.

Band switching circuit (a) simplified schematic (b) Tun-

ing curves.

Inductor switching (a) Single ended inductor switch-

ing reported in [51] (b) Differential inductor switching

reported in [52].

VCO topologies (a) NMOS only (b) PMOS only (c)

NMOS and PMOS complementary.

(a) amplitude correction circuit with detector (b) am-plitude correction based on tuning curve selection (c)

programmable bias circuit.

Bias filtering (a) conventional low-pass bias filter (b)

proposed bias filter.

Bias filtering speed-up (a) power-up delay circuit (b)

dynamic delay circuit.

Integrated spiral inductor geometries (a) square (b) oc-

tagonal (c) circular

Narrow band inductor SPICE model in ASITIC.

Integrated differential spiral inductor geometries (a) square

(b) octagonal (c) circular.

(a) two single-ended inductors used for differential op-

eration (b) a single differential center-tapped inductor.

Varactor structures in CMOS technology and C-V char-

acteristics (a) p+ to n-well junction varactor (b) NMOS

varactor (c) Accumulation mode MOS varactor (d) PMOSvaractor.

(a) test bench for simulation (b) simulated C-V curves

for different AC signal amplitudes.

(a) VCO with control inputs. (b) VCO tuning curves di-

vided into subbands. (c) CP output current as a function

of output voltage.

Conventional auto calibration architecture.

The calibration frequency and control voltage.

Proposed auto calibration architecture.

Flow chart of operation in the proposed calibration architecture.

The reference voltage circuit.

A typical simplified TDD radio architecture.

VCO with its inputs and outputs

58

60

61

63

66

67

67

68

69

70

71

73

75

78

81

82

83

84

84

86

87


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xiv CMOS PLLs AND VCOs FOR 4G WIRELESS

6.9

7.1

7.2

7.3

7.4

7.5

7.6

7.7

7.8

7.9

7.107.11

7.12

7.13

7.14

8.1

8.2

8.3

8.4

8.5

8.6

8.7

8.8

9.19.2

9.3

9.4

(a) RF Transmitter (b) ramped power-up timing scheme.

Simplified complementary NMOS and PMOS VCO cir-

cuit schematic.

Simplified PMOS VCO circuit schematic.

PMOS capacitance switching circuit (a) simplified schematic

(b) layout.

MIM capacitance switching circuit.

Accumulation mode MOS varactor (a) physical cross-

sectional layout (b) C-V characteristic (c) schematic symbol.

Simulated characteristics of accumulation mode varac-

tor (a) C-V characteristics (b) Series resistance versus

tune voltage (c) Q versus tune voltage.

(a) test structure of the differential inductor (b)comparison

of measured and simulated Q of inductor.

Current density on the differential inductor at 4GHz.

Measured tuning curve of VCO1 for different trim inputs.

Measured tuning curve of VCO2 for different trim inputs.Comparison of tuning curves for VCO1 and VCO2.

Measured and simulated phase noises (a) VCO1 (b) VCO2.

Measured supply sensitivities of (a) VCO1 (b) VCO2.

Die photo of the 4GHz VCO in the PLL test prototype.

Proposed GSM/WCDMA frequency synthesizer plan

for wide band IF double conversion operation.

Frequency synthesizer architecture.

Simulation result of the VCO control voltage transientresponse.

The simplified dual-band VCO schematic view.

The simulated phase noise of the VCO.

Tuning versus control voltage simulated results for each mode.

System block diagram of the Integer-N divider.

Layout view of the whole synthesizer.

Wireless LAN growth [75].Frequency plan for multi-band and multi-mode opera-

tion WLAN applications.

Wideband-IF radio transceiver architecture.

Quadrature LO generation in a zero-IF (or low-IF) re-

ceiver using LO1 and LO2. LO1 is fixed while LO2 is

used for frequency synthesis (or vice versa).

90

94

95

97

97

98

99

100

100

101

102102

104

105

106

108

109

110

111

112

113

114

117

120

122

122

124


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List of Figures xv

9.5

9.6

9.7

9.8

9.9

9.109.11

9.12

9.13

9.14

9.15

9.16

9.179.18

9.19

9.20

9.21

9.22

9.23

9.24

10.1

10.2

10.3

10.4

10.5

A typical PLL SSB phase noise profile.

Phase noise requirements for VCO and PLL close-in

noises for a constant integrated noise value of

for different values ofB.

Loop filter architecture (a) conventional loop filter ar-

chitecture (b) proposed loop filter architecture.

The RF (LO1) Frequency synthesizer architecture.

Simplified schematic of 4GHz VCO.

Equivalent circuit model used to represent mixers LO input.Simplified VCO buffer schematic.

VCO buffer trimming capacitance schematic.

(a) differential line structure (b) simulation model.

RF prescaler architecture.

(a) divide-by-2 schematic (b) CML latch.

(a) divide-by-4 schematic (b) medium speed latch.

The IF (LO2) Frequency synthesizer architecture.2-stage PPF schematic.

IQ phase error due to 2nd and 3rd harmonic levels at

PPF output.

Dual-modulus prescaler architecture.

Composite phase noise plot of the PLLs at the 2.4GHz

transmitter output.

Die photo of (a) LO1 (b) LO2.

2.4GHz transmitter performance with 64-QAM signal.

5GHz transmitter performance with 64-QAM signal.

2-port network analyzer measurement.

Device and dummy layout.

a) A conventional G-S-G probe pad layout (top view)

and a simple equivalent model b) Ground shielded G-

S-G probe pad layout and a simple equivalent model.

A cross sectional view of the lossy 2-port structure andcoupling path between ports through substrate.

a) One port G-S-G top view of the conventional probe

pad layout (for 3 metal CMOS process M1 M2 and M3are metal layers). b) side view of the layout. c) A simpleequivalent circuit for S to G path. d) parameter plot

on the Z-smith chart.

125

127

129

131

132

134135

136

136

137

138

139

140142

143

144

145

146

147

147

150

151

154

154

155


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xvi CMOS PLLs AND VCOs FOR 4G WIRELESS

10.6

10.7

10.8

10.9

10.10

10.11

10.12

10.13

10.14

10.15

a) One port G-S-G top view of the ground shielded probe

pad layout (for 3 metal CMOS process M1 M2 and M3are metal layers). b) side view of the layout. c) A simple

equivalent circuit for S to G path. d) parameter plot

on theZ-smith chart.

2-port and 1-port inductor measurement setup on die.

Differential varactor measurement setup.

RF MOS device measurement setup.

The layout floor plan for the test chip.

of the open structure.

Q of the open structure.

of the test inductor structure IND2.

Q of the test inductor structure IND2.

Q of the test inductor structure IND3.

156

157

158

159

160

161

161

162

162

163


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List of Tables

1.1

7.1

8.1

8.28.3

8.4

8.5

9.1

9.2

9.3

9.4

9.5

Table of short range wireless standards.

Comparison of VCO1 and VCO2 performance parameters.

Specifications of interest in GSM and CWDMA stan-

dards for synthesizer frequency planning.

Summary of the dual-mode synthesizer configuration.Required tuning range specifications.

Summary of VCO performance.

State transition table for 4-bit counter.

Summary of the RF (LO1) and IF (LO2) PLL specifications.

PLL close-in noise VCO noise at 1MHz offset and

PLL noise floor for different values of loop bandwidth.

Simulated characteristics of LO1 VCO.

Simulated characteristics of the IF (LO2) VCO.

Comparison of this work with published works.

5

103

109

110112

112

116

123

126

133

141

147


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Preface

As we move to the next millennium the telecommunication needs of tomor-

row are not very clear. Present day telecommunication services are dominated

by voice. Broadband access to the Internet and web browsing are growing

rapidly. If the past decade is any indication wireless communication will con-

tinue to grow as the demand for mobility continues to surpass all expectations.

Most forecasts predict that the number of mobile phones worldwide will exceed

one billion by 2005!

At the time of writing this book mobile operators in many countries start

to provide third generation (3G) Wireless Wide Area Network (WWAN) ser-

vices (e.g Swedish operators http://www.tre.se telia.se and tele2.se) adding

video and multimedia applications. Beyond 3G comes 4G where there is no

agreed upon definition for 4G mobile systems. However beyond 3G wireless

systems will consist of a combination of different access technologies namely

cellular systems (existing 2G and 3G for WWAN) Wireless Local Area Net-works (WLANs802.11 a/b/g) and Wireless Personal Area Networks (WPANs

Bluetooth).

These access systems will be connected via a common IP-based core net-

work that will also handle network convergence providing seamless handover

among these different networks. As a result mobile terminals must be able to

work across different standards supporting both convergence as well as migra-

tion from existing to emerging higher data rate systems whether cellular or

WLAN.Currently and with the emergence of WLAN for higher data rates at shorter

distances for hot-spots a debate is ensued as to whether cellular and WLAN

technologies are competing or complementary. WLANs are growing very

rapidly and provide the potential for carrying voice over the Internet (VoIP)

with voice over WLAN (VoWLAN) technology at much cheaper rates as un-

like cellular they are based on the unlicensed ISM and UNII bands.


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xx CMOS PLLs AND VCOs FOR 4G WIRELESS

Central to this debate however is the success or lack thereof of developing

low power cost effective multi-standard multi-band chip-set solutions partic-ularly the radio part of the solution catering for either or both technologies.

This is particularly true for WLAN as it moves from being PC-centric into be-

ing handheld-centric. Higher levels of integration in deep sub-micron CMOS

technologies promise to propel us beyond 3G with many new wireless prod-

ucts and innovative applications. Over the past few years researchers in the

field of wireless semiconductor began to report chip design solutions for multi

band multi standard wireless applications. Also engineers at industry have suc-

ceeded with development of CMOS single chip multi-standard radio transceiver

and digital baseband chips.

This book is devoted to the subject of CMOS phase lock loops (PLLs) and

voltage controlled oscillators (VCOs) design for future broadband 4G wireless

devices. These devices will be handheld-centric requiring very low power con-

sumption and small footprint. They will be able to work across multiple bands

and multiple standards covering WWAN (GSM,WCDMA) WLAN (802.11

a/b/g) and WPAN(Bluetooth) with different modulations channel bandwidths

phase noise requirements etc. As such the book wil l discuss design modeling

and optimization techniques for low power fully integrated broadband PLLsand VCOs in deep sub-micron CMOS. To our knowledge this is the first book

on the subject.

First the PLL and VCO performances are studied in the context of the chosen

multi-band multi-standard radio architecture and the adopted frequency plan.

Next a thorough study of the design requirements for broadband PLL/VCO

design is conducted together with modeling techniques for noise sources in a

PLL and VCO focusing on optimization of integrated phase noise for multi-

carrier OFDM 64-QAM type applications. Design examples for multi standard

802.11 a/b/g as well as for GSM/WCDMA are fully described and experimental

results from CMOS test chips have demonstrated the validity of the

proposed design and optimization techniques. Equally important the work

describes techniques for robust high volume production of RF radios in general

and for integrated PLL/VCO design in particular including issues such as supply

sensitivity ground bounce and calibration mechanisms.

This book is intended for use by graduate students in electrical and computer

engineering as well as RFIC design engineers in both the wireless and the

semiconductor industries. It will also be useful for design managers projectleaders and individuals in the wireless semiconductor marketing and business

development.

Chapter 1 provides introduction material and discusses the objectives as well

as the organization of different chapters.

Chapter 2 provides an overview of VCO and PLL design for fully integrated

single chip radio solutions.


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PREFACE xxi

Chapters 3 addresses phase noise in broadband PLLs.

Chapters 4 5 and 6 discuss different aspects of broadband VCO designstarting with system level considerations in Chapter 4 circuit design issues in

Chapter 5 and practical design considerations in Chapter 6.

Chapter 7 presents a case study of a CMOS 4GHz VCO and discusses its

applications.

Chapter 8 deals with a case study for PLL/VCO design for cellular multi-

standard applications while Chapter 9 presents a case study for designing PLLs

and VCOs for a multi band multi standard CMOS radio transceiver fully com-

pliant to the 802.11a/b/g WLANs.

Chapter 10 discusses RF CMOS characterization and measurements tech-

niques used throughout this work including pad-dembedding and device char-

acterization. Chapter 11 provides a summary of the contributions of this work.

This book has its roots in the Ph.D thesis of the first author. We would like

to thank all those who assisted us at different phases of this work including our

colleagues at the Analog VLSI Lab The Ohio State University and at Spirea

AB Stockholm and Spirea Microelectronics Dublin Ohio. We would like to

specially thank Yiwu Tang Fredrik Johnsson Rami Ahola Laurent Nouger

Martin Sanden Peter Olofsson James Wilson Kishore Rama Rao. We certainlylike to thank our families for their understanding and encouragement during the

development of this work. We would not have completed this book withouttheir support.

ADEM AKTAS AND MOHAMMED ISMAIL

ColumbusOhio


18/19

List of Acronyms

2G

3G

4G

ADC

AFC

AGCAM

BB

BER

BFSK

BPSK

CDMA

CML

CPdBc

DCR

DFF

DMP

DSB

DSP

EM

EVM

FDDFM

GFSK

GMSK

GPS

GSM

IF

2nd generation

3rd generation

4rd generation

Analog-to-Digital Converter

Automatic Frequency Control

Automatic Gain ControlAmplitude Modulation

baseband

Bit Error Rate

Binary Frequency Shift keying

Binary Phase- Shift Keying

Code Division Multiple Access

Current Mode Logic

Charge PumpdB with respect to the carrier

Direct conversion Receiver

D-type Flip-flop

Dual Modulus Prescaler

Double Sideband

Digital signal processing

Electromagnetic

Error vector Magnitude

Frequency-division duplexingFrequencyModulation

Gaussian Frequency Shift Keying

Gaussian Minimum Shift Keying

Global Positioning System

Global System for Mobile communications

Intermediate Frequency


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xxiv CMOS PLLs AND VCOs FOR 4G WIRELESS

IP

ISI

LNA

LO

LPF

MAC

MIM

OFDM

PFD

PLLPM

PPF

PVT

QAM

QPSK

RF

rms

RX

SAWSNR

SSB

TDD

TX

VCO

VoIP

VoWLAN

WAN

WCDMA

WLAN

WPAN

Internet Protocol

Intersymbol InterferenceLow-Noise Amplifier

Local Oscillator

Low-Pass Filter

Medium Access Control

Metal-insulator-metal

Orthogonal Frequency Division Multiplexing

Phase-Frequency Detector

Phase-locked LoopPhase Modulation

Poly-Phase Filter

Process supply voltage and temperature

Quadrature Amplitude Modulation

Quadrature Phase Shift Keying

Radio Frequency

Root-Mean Square

Receiver

surface acoustic waveSignal-to-Noise Ratio

Single Sideband

Time-division duplexing

Transmitter

Voltage-Controlled Oscillator

Voice over IP

Voice over WLAN

Wireless Area Network

Wideband CDMA

Wireless Local Area Network

Wireless Personal Area Network

Documents

Front Matter 7675