Free Powerpoint Templates Page 1 Free Powerpoint Templates Low Power VLSI Design Dr Elwin Chandra Monie RMK Engineering College

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Low Power VLSI Design

Dr Elwin Chandra Monie RMK Engineering College

http://www.powerpointstyles.com/




Page 2

Topics for discussion

• Need for low power design• Sources of power dissipation• Levels of power optimization• Design for low power• Estimation of power• Advanced techniques in power reduction• Software design for low power

Text Book:Practical low power Digital VLSI Design,Gary YepKluwer Academic Publications, 1998



Page 3

NEED FOR LOW POWER DESIGN



Page 4

IC Generation

First Planner IC 19612 transistors

Pentium 4 - 2001 42 Million Transistors



Page 5

Gallery - Current Processors

Intel Core 2 Duo “Conroe” 291M transistors / 2.67GHz / 65W

L=65nm Area=143mm2 Image courtesy Intel Corporations All Rights Reserved



Page 6

45nm 4 Cores 2.67-3.3 GHz L3 8MB 0.8-1.35V 130W 1.4 Billion22nm 4 cores 3.4GHz L3 8MB 65W



Page 7

Moore’s Law 1965

• Number of transistors will double in 18 to 24 months• Still valid and trends show it will be valid for a few

years

Gordon E. MooreFairchild



Page 8

Moore’s Law - Processors

Expected to reach Tera capability in 2010

2x Growth in 1.96 years



Page 9

Technology Trend



Page 10



Page 11

Integrated Circuit Complexity



Page 12

Clock Frequency

P6

Pentium ® proc486

38628680868085

8080

80084004

0.1

1

10

100

1000

10000

1970 1980 1990 2000 2010

Year

Fre

qu

ency

(M

hz)

2X every 2 years

Courtesy, Intel

Lead microprocessors frequency doubles every 2 years



Page 13

Chip Power Density

• 4004• 8008• 8080

• 8085

• 8086

• 286• 386

• 486• Pentium®

• P6

• 1

• 10

• 100

• 1000

• 10000

• 1970 • 1980 • 1990 • 2000 • 2010• Year

•P

ow

er D

ensi

ty (

W/c

m2)

Nuclear

Reactor

Hot Plate



Page 14

5KW 18KW

1.5KW 500W

40048008

80808085

8086286

386486

Pentium® proc

0.1

1

10

100

1000

10000

100000

1971 1974 1978 1985 1992 2000 2004 2008Year

Po

wer

(W

atts

)

Power delivery and dissipation will be prohibitivePower delivery and dissipation will be prohibitive

Courtesy, Intel



Page 15

Power factor



Page 16

Battery

Portable consumer electronics powered by battery Battery is heavy and big Energy density barely doubles in several years Safety concern: the energy density is approaching that of explosive chemicals.

The battery technology alone will not solve the low power problem



Page 17

Reliability and Cooling Costs • High power dissipation high temperature malfunction • High performance microprocessors: ~50 Watts (a hand-held soldering iron)• Packaging cost and cooling cost: fans• Power supply rails: high transient current (e.g. 3A).



Page 18

Environmental Concerns• Office automation equipment

– 5% of total US commercial energy in 1993– 10% of total US commercial energy in 2000

• Electricity generation air pollution and consumption of energy sources• Trends towards GREEN Chip



Page 19

Sources of Power dissipation in CMOS Circuits



Page 20

Sources of Power Dissipation in CMOS

• Dynamic Power Consumption• charge and discharge capacitors

• Short Circuit Current• short-circuit current path between supply rails

during switching• Glitch power dissipation

• Leakage• Leaking diodes and transistor



Page 21

Dynamic Power Dissipation

• Dynamic power is required to charge and discharge load capacitances when transistors switch.

• One cycle involves a rising and falling output.

• On rising output, charge Q = CΔV = CLVDD is required.

• On falling output, charge is dumped to GND.

VIN

VDD

GND

S

G

VOUT

D

S

G

D

CL

VDD

VOUT

RP

CL

IDD

VDD

VOUT

RN CL



Page 22

Dynamic Power Dissipation..

VDD

VOUT

RP

CL

IDD

VDD

VOUT

RN CL

T

CLK

VIN

VOUT

Do not depend on RN and RP Not a function of transistor size

Assume that one cycle of charge-discharge completes in one clock peroid TCLK i.e. VIN is the CLK:



Page 23

Power drawn from source

clk

DD

L

cV

c

LT

TDDcd

clk

DD

L

DDL

c

V

c

L

T

c

Lc

T

DDccap

clkDDL

DDL

DD

LDD

T

L

DD

T

DDDDs

fV

C

tdvtvT

Cdttitv

TP

fV

CV

T

Ctdvtv

T

C

dtdt

tdvCtv

Tdttitv

TP

fVC

VCT

V

tdvT

CVdt

dt

tdvC

T

V

dtVtiT

P

DD

DD

DDV

2

)()()()(1

22)()(

)()(

1)()(

1

)()(

)(1

2

0

2

22

0

2

0

2

0

2

0

2

0

2

0



Page 24

Lowering Dynamic Power

Pdyn = CL VDD2 P01 f

Capacitance:Function of fan-out, wire length, transistor sizes

Supply Voltage:Has been dropping with successive generations

Clock frequency:Increasing…

Activity factor:How often, on average, do wires switch?



Page 25

Example: A typical CMOS inverter in clocked at f = 250 MHZ has CL = 50 fF and use VDD = 1.8V

P = αCV2f = (50fF)(1.8)2(250MHZ) = 40.5 µW

Example: 20 M logic transistors chip, average width: 12λ VDD=1.2 V , use 0.1 µm process Cg = 2 fF/mm, activity factor = 0.1

Z

dynamic

L

mW/MH.

ffnFP

nFmfFmC

453

1045.3)2.1)(24)(1.0(

24)/2)(/05.0)(12)(1020(92

6



Page 26

Short Circuit Power Consumption

Finite slope of the input signal causes a direct current path between VDD and GND for a short period of time during switching when both the NMOS and PMOS transistors are conducting.

Vin Vout

CL

Isc



Page 27

Short Circuit current



Page 28

Short Circuit Currents Determinates

• Duration and slope of the input signal, tsc

• Ipeak determined by – the saturation current of the P and N transistors

which depend on their sizes, process technology, temperature, etc.

– strong function of the ratio between input and output slopes• a function of CL

Esc = tsc VDD Ipeak P01

Psc = tsc VDD Ipeak f01



Page 29

Impact of CL on Psc

Vin Vout

CL

Isc 0

Vin Vout

CL

Isc Imax

Large capacitive load

Output fall time significantly larger than input rise time.

Small capacitive load

Output fall time substantially smaller than the input rise

time.



Page 30

Ipeak as a Function of CL

-0.5

0

0.5

1

1.5

2

2.5

0 2 4 6

I pea

k (A

)

time (sec)

x 10-10

x 10-4

CL = 20 fF

CL = 100 fF

CL = 500 fF

500 psec input slope

Short circuit dissipation is minimized by matching the rise/fall times of the input and output signals - slope engineering.

When load capacitance is small, Ipeak is large.



Page 31

Psc as a Function of Rise/Fall Times

0

1

2

3

4

5

6

7

8

0 2 4

P n

orm

aliz

ed

tsin/tsout

VDD= 3.3 V

VDD = 2.5 V

VDD = 1.5V

normalized wrt zero input rise-time dissipation

When load capacitance is small (tsin/tsout > 2 for VDD > 2V) the power is dominated by Psc

If VDD < VTn + |VTp| then Psc is eliminated since both devices are never on at the same time.

W/Lp = 1.125 m/0.25 mW/Ln = 0.375 m/0.25 mCL = 30 fF



Page 32

Glitch Power Dissipation

• Glitches are temporary changes in the value of the output – unnecessary transitions

• They are caused due to the skew in the input signals to a gate

• Glitch power dissipation accounts for 15% – 20 % of the global power



Page 33


• P = 1/2 .CL.Vdd . (Vdd – Vmin) ;

Vmin : min voltage swing at the output • Glitch power dissipation is dependent on

– Output load– Input pattern– Input slope



Page 34


• Hazard generation can be reduced by gate sizing and path balancing techniques

• Hazard propagation can be reduced by using less number of inverters which tend to amplify and propagate glitches



Page 35

Leakage (Static) Power Consumption

Sub-threshold current is the dominant factor.

All increase exponentially with temperature!

VDD Ileakage

Vout

Drain junction leakage

Sub-threshold currentGate leakage



Page 3636

Source of Leakage Current

Keshavarzi,Roy,Hawkins(ITC1997)



Page 37

Leakage as a Function of VT

0 0.2 0.4 0.6 0.8 1

VGS (V)

ID (A

)

VT=0.4VVT=0.1V

10-2

10-12

10-7

Continued scaling of supply voltage and the subsequent scaling of threshold voltage will make subthreshold conduction a dominate component of power dissipation.

An 90mV/decade VT roll-off - so each 255mV increase in VT gives 3 orders of magnitude reduction in leakage (but adversely affects performance)



Page 38

Leakage and VT

80

0.25 V

13,000

920/400

0.08 m

24 Å

1.2 V

CL013 HS

52

0.29 V

1,800

860/370

0.11 m

29 Å

1.5 V

CL015 HS

42 Å42 Å42 Å42 ÅTox (effective)

43142230FET Perf. (GHz)

0.40 V0.73 V0.63 V0.42 VVTn

3000.151.6020Ioff (leakage) (A/m)

780/360320/130500/180600/260IDSat (n/p) (A/m)

0.13 m 0.18 m 0.16 m 0.16 m Lgate

2 V1.8 V1.8 V1.8 VVdd

CL018 HS

CL018 ULP

CL018 LP

CL018 G



Page 39

Reference

Kaushik Roy, Saibal Mukhopadhyay and Hamid Mahmoodi-Meimand,

“Leakage Current Mechanisms and Leakage Reduction Techniques in Deep-Submicrometer CMOS Circuits”, Proceedings of the IEEE, vol. 91, no. 2, February 2003



Page 40

Power Dissipation in CMOS Circuits

Ptotal = Pswitching + Pshort-circuit + Pleakage

Due to charging and discharging capacitors (dynamic power consumption)

Due to direct paths

Due to leaking diodes and transistors

%75 %5%20



Page 41

Power Equations

P = CL VDD2 f01 + tscVDD Ipeak f01 + VDD Ileakage

Dynamic power(decreasing relatively)

Short-circuit power

( decreasing absolutely)

Leakage power

( increasing)

f01 = P01 * fclock P01 Probability of transition from 0 -> 1



Page 42

Basic principle of Low Power Design

• Reducing P = C Vdd2 f

Reduce-Gate capacitance-Overlap capacitance- arise fromlateral diffusion of thedrain and source impurities-Diffusion capacitance-Interconnect capacitance Reduce Vdd

Quadratic relationReduce Threshold voltage -will increase leakage current and reduce noise immunity-Dynamic voltage scaling

Reduce switching frequency-reduce unnecessary switching-use alternate logic implementation-use coding to reduce switching


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Free Powerpoint Templates Page 1 Free Powerpoint Templates Low Power VLSI Design Dr Elwin Chandra Monie RMK Engineering College