CHANNEL  TRACKER  &  DDC  MODULE  

RESULT  

SCALABLE  EMULATO

R  

- A virtual platform to simulate radio environment to test and verify wireless system in laboratory

MOTIVATION  -­‐  CHANNEL  EMULATOR   SYSTEM  OVERVIEW  

HIGH THROUGHPUT CHANNEL TRACKING FOR JTRS WIRELESS CHANNEL EMULATOR

SYSTEM  SPECIFICATION  - PENTEK Cobalt board : Xilinx Vertex 6 series FPGA(XC6VSX315TFF1156- 2) : two 500 MHz ADCs & DDCs : two 800 MHz DACs & DUCs : PCI Express Interface to communicate to a host PC - Xilinx Vivado HLS 2012.3 - Xilinx ISE 12.4

Wireless Channel Emulator

RF Front End ADC/DAC

RF Front End ADC/DAC

…

One FPGA channel emulator system One FPGA channel emulator system

Latency (cycles)

Input buffering 19 Module a 10 Module b 18 Module c 19

Output buffering 19 Throughput 19 Total latency 71

Area usage (%)

SLICE 940 (2%) LUTs 2104 (1%) FFs 2338 (0.5%)

DSPs 112 (8.3%) BRAMS 3 (0.2%)

Module throughputs

Resource usage

*DAJUNG LEE, JANARBEK MATAI, BRAD WEALS, RYAN KASTNER *The Department of Electronic and Computer Engineering, The Department of Computer Science and Engineering

Toyon Research Cooperation

Channel emulator signal flow

ADC data acquisition DAC data stream generation

RF Front End ADC DDC

RF Front End DAC DUC

Channel Effect Core

Base-band signal

Base-band signal

Digital signals Analog signals

Radio signal

Radio signal

250MHz

2M - 30MHz

FPGA Channel Emulator RF front end ADC/DAC

Channel Tracker

100#

150#

200#

250#

300#

10# 20# 30# 40# 50#

Throughp

ut##(Msps)#

The#size#of#input#samples#

Pattern of throughput

Performance in different designs

93600%

952.65%313.5% 284%0.534% 1.05%

31.9%

263.16%

0.1%

1%

10%

100%

1000%

100%

1000%

10000%

100000%

MATLAB% Baseline%HLS% Latency%Op>miza>on%

Throughput%Op>miza>on%

Througpu

t%(Msps)%

Latency%(ns)%

FPGA ASSY

RF Front End

ADC/DAC

Radio under test

Radio under test

Multiple channel emulators

Radio under test

FPGA ASSY

RF Front End

ADC/DAC

FPGA ASSY

RF Front End

ADC/DAC

Radio under test

Radio under test

Upload and control

scenarios from PC

Multiple channel emulator network

Channel tracker module

Streaming output (pulse & index)

Complex number multiplication for correlation

Complex number multiplication for power calculation

X Constant

Find tuning frequency

Adder tree Adder tree

CORDIC

Accumulate power

Thresholding

Streaming input (I&Q complex number)

FIFO FIFO copy

Channel tracker module

a

b c

FIFO index FIFO copy pulse

LUT

TRACKING  FREQ

UEN

CY  HOPPIN

G  

HLS  OPTIMIZATION  STRATEGY    -­‐  LATENCY  VS  THROUGHPUT  Latency optimization - Single threaded implementation - if conditions and parameters nested - Strong data dependency

Throughput optimization - Concurrent functional modules - Minimum functional dependency

Control signals (tuning frequency, etc.)

I&Q Inputs (from ADC)

Delay buffer

DDC control registers

16b

Multi-band DDC

Channel tracker

Tuning frequency & enable

Channel  tracker  

250 MHz

Carrier Frequency

DDC  

- Tracking intermediate frequency signals in 250MHz - Detecting the carrier signal of 51 frequency slots - Analyzing signal spectrum based on linear prediction - Generating a programmable DDC module control signal

Channel Effects

Field Test ü  Cost ü  Energy ü  Human power ü  Unrepeatable

Channel Emulator

RF input RF output

Channel Emulator ü  Channel effect ü  Digital Signal

Processing

- Performance & Scalability - Unknown frequency hopping techniques over a range of 250 MHz bandwidth

PROBLEMS  

2MHz 2GHz

CONTRIBUTIONS  - Highly scalable JTRS channel emulator network (up to 1000) - Real-time channel tracker spanning frequency hopping - HLS optimization methodologies