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FPGA Run-time Reconfigurable Placement Presentation by Brian Leonard Clemson University 2003 SURE REU Program Advisor: Ron Sass

FPGA Run-time Reconfigurable Placement

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FPGA Run-time Reconfigurable Placement. Presentation by Brian Leonard Clemson University 2003 SURE REU Program Advisor: Ron Sass. Outline. Background Placement Package Online Placement Offline Placement Conclusion. Outline. Background Placement Package Online Placement - PowerPoint PPT Presentation

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Page 1: FPGA Run-time Reconfigurable Placement

FPGA Run-time Reconfigurable

PlacementPresentation by Brian Leonard

Clemson University

2003 SURE REU Program

Advisor: Ron Sass

Page 2: FPGA Run-time Reconfigurable Placement

Outline

Background Placement Package Online Placement Offline Placement Conclusion

Page 3: FPGA Run-time Reconfigurable Placement

Outline

Background Placement Package Online Placement Offline Placement Conclusion

Page 4: FPGA Run-time Reconfigurable Placement

Background - FPGAs

Field Programmable Gate Array Reconfigurable RTR Architectures

Page 5: FPGA Run-time Reconfigurable Placement

Background - Definitions

Modules Configuration Affinity

Page 6: FPGA Run-time Reconfigurable Placement

Background – Example

Page 7: FPGA Run-time Reconfigurable Placement

Background – Example

Cover

This

Up now

Page 8: FPGA Run-time Reconfigurable Placement

Background – Example

Page 9: FPGA Run-time Reconfigurable Placement

Outline

Background Placement Package Online Placement Offline Placement Conclusion

Page 10: FPGA Run-time Reconfigurable Placement

Placement Package - Representation List of modules

currently on chip List of empty

rectangles

Page 11: FPGA Run-time Reconfigurable Placement

Placement Package - Representation List of modules

currently on chip List of empty

rectangles

Page 12: FPGA Run-time Reconfigurable Placement

Placement Package - Representation List of modules

currently on chip List of empty

rectangles

Page 13: FPGA Run-time Reconfigurable Placement

Placement Package - Representation

Page 14: FPGA Run-time Reconfigurable Placement

Placement Package - Algorithms Class PlacementAlgorithm Algorithms

First Fit Best Fit Worst Fit Location Aspect Ratio

Page 15: FPGA Run-time Reconfigurable Placement

Outline

Background Placement Package Online Placement Offline Placement Conclusion

Page 16: FPGA Run-time Reconfigurable Placement

Online Placement - Problem

Java RTR-JVM Multiple Classes and Methods Online Placement

Speed No affinity considerations

Page 17: FPGA Run-time Reconfigurable Placement

Online Placement - Solution

Test Placement Algorithms Chip Utilization Fragmentation Program Speed

Consensus

Page 18: FPGA Run-time Reconfigurable Placement

Outline

Background Placement Package Online Placement Offline Placement Conclusion

Page 19: FPGA Run-time Reconfigurable Placement

Offline Placement - Problem

Large, Fully-Implemented Program More Computation Time Considerations

Affinity Reconfiguration time

Page 20: FPGA Run-time Reconfigurable Placement

Offline Placement - Lattice

Page 21: FPGA Run-time Reconfigurable Placement

Offline Placement - LatticeChip Size = 5

A = 4 B = 1

C = 2 D = 1

Page 22: FPGA Run-time Reconfigurable Placement

Offline Placement - Solution

Place Frontier Configurations Transition Table How to Place

For Reconfiguration For Affinity (run-time speed) Compromise

Page 23: FPGA Run-time Reconfigurable Placement

Outline

Background Placement Package Online Placement Offline Placement Conclusion

Page 24: FPGA Run-time Reconfigurable Placement

Conclusion

Summary Placement Package Online Placement Offline Placement

Future Work Conclusion

Page 25: FPGA Run-time Reconfigurable Placement

Thank you.

Page 26: FPGA Run-time Reconfigurable Placement

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