- B Y K U S H A L K U N I G A L U N D E R G U I D A N C E O F

D R . K . R . R A O .

S P R I N G 2 0 1 1 ,

E L E C T R I C A L E N G I N E E R I N G D E P A R T M E N T , U N I V E R S I T Y O F T E X A S A T A R L I N G T O N

FPGA Implementation of H.264 Video Encoder

Proposal

This project is based on the implementation of H.264 Video encoder and the Algorithms for evaluating the Transform and quantization Suitable for high speed implementation on FPGA/ASIC.

Modified Encoder Hardware Design:

Fig 1: Modified encoder hardware design [3].

Description of Test Data

The encoder will be used to encode a frame from a video sequence:

30 frames/second.

Each frame is 176 x 144 pixels (QCIF Resolution, very typical for low bit-rate video contents in cell phones).

Description of Test Data

Reference Frame

Fig 2: Reference frame 1 [4].

Description of Test Data

Current Frame

Fig 3: Current frame 2 [4].

Residual Frame

Fig 4: Residual of current frame [4].

Different Stages in designing H.264 Encoder

Motion Estimation

Motion Compensation

Discrete Cosine Transform

Quantization

Motion Estimation

Fig 5: The principle of block matching motion estimation algorithm is finding the best matching block in the searching area of a reference frame for each macroblock in the original frame.

four-step search

Step 1: A macro block that is the “best match” is found from a nine-checking-points pattern on a 5x5 window located at the center of the 15 x 15 search area (Figure 5a).

Decision: If the “best matched” macro block is found at the center of the search window, go to Step 3 otherwise go to Step 2.

Four-step search

Step 2: The search-window size is maintained at 5 x 5. However, the search patter will depend on the position of the previous “best matched” macro block location.

a. If the previous “best matched” macro block is located at the corner of the search window, five

additional checking points (Figure 5b) are used.

Four-step search

b. If the previous “best matched” macro block is located at the middle of the horizontal or vertical axis of the previous search window, three additional checking points (Figure 5c) are used.

Decision: If the “best matched” macro block is found at the center of the search window, go to Step 3; otherwise go to Step 2.

Step 3,4: The search window is reduced to 3 x 3 (Figure 5d) and the direction of the overall motion vector is considered as the “best matched” macro block is among these nine macro blocks.

4-Step Search

Check points for motion estimation 4x4 macroblock

A 20x20 pixel search range divided up by 4x4 pixel search

Fig 6a: A 20x20 pixel search range divided up by 4x4 pixel search [5].

4-step search

Step 2

Fig 6b: A 20x20 pixel search range with 5 additional checkpoints during step 2 of the four-step search algorithm [5].

4-step search

Step 3

Fig 6c: A 20x20 pixel search range with 3 additional checkpoints during step 3 of the four-step search algorithm [5].

4-step search

Step 4

Fig 6d: A 20x20 pixel search range with 5x5 search window, now reduced to 3x3 during step 4 of the four-step search algorithm [5].

Motion Vector Description

Fig 7. Motion vector description.

Pseudo code

Fig 8: Psuedo code for obtaining predicted frame [6].

Overall view of operations in encoder module

Fig 9: Overall view of operations in encoder module [6].

Motion Compensation

Fig 10: Generating predicted frame using reference frame and motion vectors. [7].

Motion compensation

Figure 11: The residual frame formed by subtracting the predicted frame from the actual current frame.

Discrete cosine transform

Figure 12: Real DCT factor.

Where: X denotes the original macroblock a = 0.5 b = sqrt(2/5) denotes array multiplication

Results

Platform: ModelSim: Version XE III 6.0d. Quartus II: Version 10.1 -sp1 Web Edition (64-Bit). The hardware description language used was VHDL (Very high speed integrated circuit Hardware Description language). Figure 14 shows the list of code segments used.

Code segments

Figure 13: List of code segments used to design the H.264 Video encoder.

List of tasks

Figure 14: List of tasks performed.

Resource usage

Figure 15: Resource usage summary.

RTL Schematic

Figure 16: generated register transfer logic for the H.264 video encoder.

Conclusion

The FPGA implementation algorithms along with the complexities involved in the mapping of H.264 video encoder transforms onto the hardware were discussed. A complete analysis of the motion estimation algorithm, motion compensation, DCT and quantization was made. VHDL code was written to implement the H.264 video encoder. The code was compiled and synthesized using ModelSim and Quartus ii sofwares. The Register transfer schematic for the code was generated.

Websites and References

[1] T. Wiegand, G. J. Sullivan, G. Bjøntegaard, and A. Luthra “Overview of the H.264/AVC Video Coding Standard”, IEEE Trans. on Circuits and Systems for Video Technology vol. 13, no. 7, pp.560–576, July 2003.

[2]Data locality description:

http://www.eetimes.com/design/embedded/4007043/How-to-map-the-H-264-AVC-video-standard-onto-an-FPGA-fabric.

[3] N. Keshaveni, S. Ramachandran, K. S. Gurumurthy “Design and FPGA

Implementation of Integer Transform and Quantization Processor and Their Inverses for H.264 Video Encoder”, Advances in Computing, Control, & Telecommunication Technologies, 2009. ACT 2009. International Conference on, pp. 646-649, July 2009

[4] I. Richardson, “The H.264 advanced video compression standard”,

Wiley, 2nd edition, 2010.

[5] L. Po, W. C. Ma, “A novel four-step search algorithm for fast block motion estimation”, Circuits and Systems for Video Technology, IEEE Transactions on , vol. 6, no. 3, pp. 313-317, August 1996.

[6] W. I. Choi, B. Jeon, J. Jeong, “Fast motion estimation with modified diamond search for variable motion block sizes”, Image Processing, 2003. ICIP 2003. Proceedings. 2003 International Conference on, vol. 2, no. 2, pp. 11, Sept 2003.

[7] How to map the H.264/AVC video standard onto an FPGA fabric - http://www.eetimes.com/design/embedded/4007043/How-to-map-the-H-264-AVC-video-standard-onto-an-FPGA-fabric.

[8]CODEC Architecture for modules- http://www.drtonygeorge.com/Video/h264/comp_architecture.htm

Websites and References

[9] Q. Peng and J. Jing, “H.264 System on Chip Design and Verification”, The IEEE 2003 Workshop on Signal Processing Systems(SIPS’03), 2003.

[10] DSP-Enabled efficient motion estimation for Mobile MPEG-4 video encoding- http://www.techonline.com/community/21066.

[11] T. Wiegand, Gary J. Sullivan, G. Bjontegaard, and A. Luthra, "Overview of the H.264/AVC Video Coding Standard", IEEE Transactions on Circuits and Systems for Video Technology, Vol. 13, No. 7, pp. 560-576, July 2003.

[12] T. Wedi, H. G. Musmann, "Motion- and aliasing-compensated prediction for hybrid video coding," IEEE Transactions on Circuits and Systems for Video Technology, Vol. 13, No. 7, pp. 577- 586, July 2003.

Websites and References

Websites and references

[13] H. S. Malvar, A. Hallapuro, M. Karczewicz, L. Kerofsky, "Low-complexity transform and quantization in H.264/AVC," IEEE Transactions on Circuits and Systems for Video Technology, Vol. 13, No. 7, pp. 598- 603, July 2003.

[14] S. Yeping, S. Ting, "Fast Multiple Reference Frame Motion Estimation for H.264/AVC," IEEE Transactions on Circuits and Systems for Video Technology, Vol. 16, no. 3, pp 447 – 452, June 2006.

[15] ModelSim simulation software: http://model.com/content/modelsim-pe-student-edition-hdl-simulation .

THANK YOU!!!!