FPGA Implementation of Flexible Interpolators and Decimators

Institutionen för systemteknikDepartment of Electrical Engineering

Examensarbete

FPGA Implementation of Flexible Interpolatorsand Decimators

Examensarbete utfört i Elektroniksystemvid Tekniska högskolan vid Linköpings universitet

av

Venkatavikram Dabbugottu

LiTH-ISY-EX--13/4654--SE

Linköping 2013

Department of Electrical Engineering Linköpings tekniska högskolaLinköpings universitet Linköpings universitetSE-581 83 Linköping, Sweden 581 83 Linköping

FPGA Implementation of Flexible Interpolatorsand Decimators

Examensarbete utfört i Elektroniksystemvid Tekniska högskolan i Linköping

av


LiTH-ISY-EX--13/4654--SE

Handledare: Amir Eghbaliisy, Linköpings universitet

Examinator: Håkan Johanssonisy, Linköpings universitet

Linköping, 21 February, 2013

Avdelning, InstitutionDivision, Department

Division of Electronic systemDepartment of Electrical EngineeringLinköpings universitetSE-581 83 Linköping, Sweden

DatumDate

2013-002-21

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� Svenska/Swedish� Engelska/English

�

�

RapporttypReport category

� Licentiatavhandling� Examensarbete� C-uppsats� D-uppsats� Övrig rapport�

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URL för elektronisk versionhttp://www.es.isy.liu.se

http://www.ep.liu.se

ISBN—

ISRNLiTH-ISY-EX--13/4654--SE

Serietitel och serienummerTitle of series, numbering

ISSN—

TitelTitle

Svensk titelFPGA Implementation of Flexible Interpolators and Decimators

FörfattareAuthor


SammanfattningAbstract

The aim of this thesis is to implement flexible interpolators and decimators onField Programmable Gate Array (FPGA). Interpolators and decimators of differ-ent wordlengths (WL) are implemented in VHDL. The Farrow structure is usedfor the realization of the polyphase components of the interpolation/decimationfilters. A fixed set of subfilters and adjustable fractional-delay multiplier valuesof the Farrow structure give different linear-phase finite-length impulse response(FIR) lowpass filters. An FIR filter is designed in such a way that it can be imple-mented for different wordlengths (8-bit, 12-bit, 16-bit). Fixed-point representationis used for representing the fractional-delay multiplier values in the Farrow struc-ture. To perform the fixed-point operations in VHDL, a package called fixed pointpackage [1] is used.

A 8-bit, 12-bit, and 16-bit interpolator are implemented and their performancesare verified. The designs are compiled in Quartus-II CAD tool for timing analysisand for logical registers usage. The designs are synthesised by selecting Cyclone IVGX family and EP4X30CF23C6 device. The wordlength issues while implementingthe interpolators and decimators are discussed. Truncation of bits is required inorder to reduce the output wordlength of the interpolator and decimator.

NyckelordKeywords Interpolation, Decimation, Linear-phase FIR interpolation, VHDL implementation

of interpolators and decimators

AbstractThe aim of this thesis is to implement flexible interpolators and decimators onField Programmable Gate Array (FPGA). Interpolators and decimators of differ-ent wordlengths (WL) are implemented in VHDL. The Farrow structure is usedfor the realization of the polyphase components of the interpolation/decimationfilters. A fixed set of subfilters and adjustable fractional-delay multiplier valuesof the Farrow structure give different linear-phase finite-length impulse response(FIR) lowpass filters. An FIR filter is designed in such a way that it can be imple-mented for different wordlengths (8-bit, 12-bit, 16-bit). Fixed-point representationis used for representing the fractional-delay multiplier values in the Farrow struc-ture. To perform the fixed-point operations in VHDL, a package called fixed pointpackage [1] is used.

A 8-bit, 12-bit, and 16-bit interpolator are implemented and their performancesare verified. The designs are compiled in Quartus-II CAD tool for timing analysisand for logical registers usage. The designs are synthesised by selecting Cyclone IVGX family and EP4X30CF23C6 device. The wordlength issues while implementingthe interpolators and decimators are discussed. Truncation of bits is required inorder to reduce the output wordlength of the interpolator and decimator.

v

Acknowledgments

I would like to thank my examiner Prof. Håkan Johansson and my supervisor Dr.Amir Eghbali for giving the opportunity to do my master thesis and for their helpand guidance throughout the thesis period. I would also like to thank Dr. KentPalmkvist for his valuable suggestions and help.

vii

Contents

0.1 List of Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 2

1 Introduction 31.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31.2 Background . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31.3 Purpose of the Thesis . . . . . . . . . . . . . . . . . . . . . . . . . 41.4 Thesis Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

2 Interpolation and Decimation 52.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52.2 Interpolation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52.3 Decimation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62.4 Sampling Rate Conversion by a Rational

Factor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72.5 Polyphase Interpolation and Decimation

Structures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102.5.1 Polyphase Representation . . . . . . . . . . . . . . . . . . . 102.5.2 Noble Identities . . . . . . . . . . . . . . . . . . . . . . . . . 10

2.6 Converters with Time-Varying Coefficients . . . . . . . . . . . . . . 12

3 Flexible Interpolators and Decimators 153.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153.2 Farrow Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153.3 Farrow Structure for SRC . . . . . . . . . . . . . . . . . . . . . . . 163.4 Linear-Phase FIR Interpolation and Decimation Utilizing the Far-

row Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163.4.1 Interpolator and Decimator structures . . . . . . . . . . . . 18

3.5 Filter Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

4 VHDL Implementation 234.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234.2 Fixed Point Package . . . . . . . . . . . . . . . . . . . . . . . . . . 234.3 VHDL Implementation of the Interpolator . . . . . . . . . . . . . . 24

4.3.1 VHDL Implementation of the Filter H0(z) . . . . . . . . . 244.3.2 VHDL Implementation of the Subfilters Gk(z) . . . . . . . 274.3.3 VHDL Implementation of the Delay Block dkm . . . . . . . . 29

ix

x Contents

4.4 Wordlength Issues in Interpolator . . . . . . . . . . . . . . . . . . . 344.5 VHDL Implementation of the Decimator . . . . . . . . . . . . . . . 34

4.5.1 VHDL Implementation of the Delay Block dkm . . . . . . . . 344.5.2 VHDL Implementation of Subfilters . . . . . . . . . . . . . 35

5 Testbench and Simulation Results 395.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 395.2 Design Flow for Testing Interpolator . . . . . . . . . . . . . . . . . 39

5.2.1 Generating a Sine Wave . . . . . . . . . . . . . . . . . . . . 395.2.2 VHDL Testbench . . . . . . . . . . . . . . . . . . . . . . . . 405.2.3 Simulation results . . . . . . . . . . . . . . . . . . . . . . . 40

5.3 Testbench for the Decimator . . . . . . . . . . . . . . . . . . . . . 435.4 Synthesis and Timing Analysis . . . . . . . . . . . . . . . . . . . . 45

5.4.1 Synthesis and Time Quest Analyzer Reports . . . . . . . . 45

6 Conclusion and Future Work 516.1 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 516.2 Future Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

A Appendix 53A.1 VHDL Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

A.1.1 VHDL Code for Subfilter . . . . . . . . . . . . . . . . . . . 53A.1.2 VHDL Code for Delay Block of Decimator . . . . . . . . . . 54A.1.3 VHDL Code for Farrow Structure of Decimator . . . . . . . 55A.1.4 User Package . . . . . . . . . . . . . . . . . . . . . . . . . . 56

Bibliography 58

List of Figures2.1 Interpolation by a factor of L. . . . . . . . . . . . . . . . . . . . . . 62.2 Original sequence and the upsampled sequence by a factor of 3. . . 72.3 Spectra of the original, intermediate, and output sequences. . . . . 82.4 Decimation by a factor of M . . . . . . . . . . . . . . . . . . . . . . 82.5 Spectra of the filtered x1(m) and the decimated sequence. . . . . . 92.6 Sampling rate converter for conversion by a rational factor L/M . . 92.7 Deriving a polyphase interpolator . . . . . . . . . . . . . . . . . . . 112.8 Deriving a Polyphase Decimator . . . . . . . . . . . . . . . . . . . 122.9 Noble identities. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132.10 Polyphase interpolator. . . . . . . . . . . . . . . . . . . . . . . . . . 132.11 Polyphase decimator. . . . . . . . . . . . . . . . . . . . . . . . . . . 132.12 Interpolator realization using time-varying coefficients, m = nM+ i

and ki is the largest integer smaller than or equal to (N − i)/M . . 14

3.1 Farrow structure. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163.2 Modified Farrow structure . . . . . . . . . . . . . . . . . . . . . . . 173.3 Realization of the polyphase components Hm(z) and HM−m(z) in

the interpolator structure. . . . . . . . . . . . . . . . . . . . . . . . 183.4 Flexible intepolator structure. . . . . . . . . . . . . . . . . . . . . . 193.5 Flexible decimator structure. . . . . . . . . . . . . . . . . . . . . . 19

4.1 Flowchart for implementing the interpolator. . . . . . . . . . . . . 254.2 RTL representation of FIR filter. . . . . . . . . . . . . . . . . . . . 264.3 The Gk(z) block with six subfilters. . . . . . . . . . . . . . . . . . . 274.4 Block diagram for VHDL implementation of the interpolator. . . . 294.5 Subfilters and delay multiplier chain block. . . . . . . . . . . . . . 314.6 Delay multiplier chain block with truncation. . . . . . . . . . . . . 324.7 Block diagram for VHDL implementitation of the decimator. . . . 344.8 A 16-bit delay multiplier chain block with truncation’s. . . . . . . 354.9 Block diagram of Decimator. . . . . . . . . . . . . . . . . . . . . . 36

5.1 Design flow for testing interpolator. . . . . . . . . . . . . . . . . . . 405.2 output of interpolator in Modelsim. . . . . . . . . . . . . . . . . . . 415.3 Testbench for the Interpolator. . . . . . . . . . . . . . . . . . . . . 425.4 sinusoidal signal and the interpolated sinusoidal signal (M=3). . . 435.5 Frequency response for the interpolator output. . . . . . . . . . . . 445.6 Frequency response for the interpolator output. . . . . . . . . . . . 445.7 Frequency response for the interpolator output. . . . . . . . . . . . 455.8 Output of the decimator in Modelsim. . . . . . . . . . . . . . . . . 465.9 Frequency response for the decimator output. . . . . . . . . . . . . 475.10 Frequency response for the decimator output. . . . . . . . . . . . . 475.11 Frequency response for the decimator output. . . . . . . . . . . . . 48

2 Contents

List of Tables3.1 Impulse response of The filter H0(z) . . . . . . . . . . . . . . . . . 203.2 Impulse response of subfilters G0(z), G1(z), G2(z) . . . . . . . . . . 213.3 Impulse response of subfilters G3(z), G4(z), G5(z) . . . . . . . . . . 21

4.1 Table of specification. . . . . . . . . . . . . . . . . . . . . . . . . . 244.2 Table for operation sizing rules. . . . . . . . . . . . . . . . . . . . . 244.3 Fractional-delay multiplier values for M = 8 and M = 5. . . . . . . 30

5.1 Table for resource utilization and performance. . . . . . . . . . . . 45

0.1 List of AbbreviationsSRC-Sampling ratio conversionWL-Word lengthFPGA- Field programming gate arrayFIR- Finite impulse responseVHDL- VHSIC Hardware description languageASIC - Application specific integrated circuitsCPLD - Complex programmable logic deviceDSP - Digital signal processingCD - Compact discDAT - Digital audio tape

Chapter 1

Introduction

1.1 IntroductionNowadays, the modern digital systems are more complex. They consist of sev-eral DSP (Digital Signal Processing) processors that operate at different samplingfrequencies. For example, in smart mobile phones we can find separate DSP proces-sors for video, photo-camera, music, video-voice recording and communication [2].Furthermore, there are three common sample rates utilized in the audio commu-nity. They are 32 KHz stream rate for broadcast industry, 44.1 KHz stream ratefor compact disc and 48 KHz for digital audio tape (DAT) [3]. A common samplerate should be employed for these signals to combine/mix the three environmentsdigitally. The stream at lower sample rate is interpolated to increase the samplerate in-order to match the higher sample rate signal.

Interpolators can be found in mixed-signal processing systems, digital receiversand in sigma-delta modulators [2]. In the sigma-delta modulators, the interpola-tion operation, i.e. oversampling, moves the signal frequency and quantizationnoise apart from each other. Decimators are used to reduce the higher sample rateto lower sample rate.

1.2 BackgroundFor high interpolation factors most of the sample values are zero, so there is anunnecessary additional computation. The computational workload can be reducedby using the polyphase interpolators and decimators. The polyphase interpola-tion and decimation are efficient when compared with straightforward realizationof interpolation and decimation. The disadvantages of the polyphase interpolator(decimator) structure are that they require new filters if the sample rate conversion(SRC) ratio changes. This limits the flexibility of interpolation (decimation) withdifferent SRC ratios. More memory is required to store the coefficient if the inter-polation factor is high. These problems can be solved elegantly by the linear-phaseFIR interpolation (decimation) utilizing the Farrow structure. This structure is

3

4 Introduction

flexible to the conversion factors, and also for an arbitrary set of integer factors,including prime numbers.

1.3 Purpose of the ThesisIn this thesis work, an interpolator and decimator FPGA prototype is designed.For many applications, FPGA implementation brings advantages that include: lowcost, higher precision processing, design flexibility, and low power. The main objec-tive of this thesis work is to implement the flexible interpolators and decimators onFPGA. The implementation is done in VHDL. In this thesis the interpolation/dec-imation factor can be varied from 2 to 20.

1.4 Thesis OutlineThis thesis report has five chapters. Chapter 2 provides the basics of interpolationand decimation, SRC and polyphase interpolation and decimation. It also includesthe basics of SRC by rational factors.

Chapter 3 gives a brief introduction to the Farrow structure, interpolationand decimation filters, SCR utilizing the Farrow structure and linear-phase FIRinterpolation and decimation utilizing the Farrow structure.

Chapter 4 is about the VHDL implementation of the interpolators and deci-mators. This chapter discusses how the FIR filter and subfilters are implemented.The wordlength issues and the truncation in the design are mentioned in thischapter.

Chapter 5 gives the testbench for the interpolator and decimator. The fre-quency response of the interpolators and decimators with different interpolationand decimation factors are plotted.

Chapter 6 gives the conclusion and future work.

Chapter 2

Interpolation andDecimation

2.1 Introduction

There are many systems where the sampling rate of a signal needs to be convertedinto an equivalent signal with a different sampling rate [4]. Multiple samplingfrequencies are used in many applications, in order to reduce and simplify thecomputational workload [5]. For example, in digital audio, three different samplingrates are used, 32 KHz in broadcasting, 44.1 KHz in digital compact disc, and 48KHz in DAT.

This chapter begins with the basics of interpolation and decimation, and abrief overview of SRC. The concepts of polyphase interpolation and decimationstructures are discussed.

2.2 Interpolation

Interpolation is a process of increasing the sampling rate and the system whichperforms it is called interpolator [5]. The aim of the interpolation is to get a newsequence with higher sampling rate without losing the information. Interpolationis a two-stage process, first the input signal is upsampled and then the upsampledsignal is filtered. In the first stage, L-1 zero-valued samples are inserted in betweenconsecutive samples of the original sequence, where L is the interpolation factor.Figure 2.1 shows the block diagram of the interpolator. Figure 2.2 illustratesthe original sequence x(n) and the upsampled sequence x1(m). The new signal,generated after the upsampler is [5]

x1(m) ={x(mL ) for m = 0,±L,±2L..

0 otherwise. (2.1)

5

6 Interpolation and Decimation

The Fourier transform of x1(m) can be expressed as [5]

x1(ejωT1) =∞∑

n=−∞x(n)e−jnωT = X(ejLωT1). (2.2)

In the z-domain, we have [5]

X1(z) = X(zL). (2.3)

Figure 2.1. Interpolation by a factor of L.

The sampling period of the new sequence x1(m) is T1 = TL . As the sampling

rate of the new sequence is increased by L, the spectrum of the sequence x1(m)contains not only the original signal but also repeated images of the original signal.A lowpass filter is used to remove the images and the stopband edge must be atωsT = π

L [5]. Figure 2.3 shows the spectra of the original sequence, the upsampledsequence x1(m), and the signal after filtering y(m).

2.3 DecimationDecimation is the process of reducing the sampling rate and the system whichperforms this task is called decimator [5]. Decimation of a signal with a factorM is a two-stage process. The first stage contains an anti-aliasing filter and inthe next stage, a downsampler. By extracting every Mth value of a signal, thesampling rate of the signal is reduced by a factor of M . This process is done by adownsampler. Figure 2.4 shows the block diagram of the decimator. The outputy(n) is [5]

y(n) = x1(nM). (2.4)The Fourier transform of y(n) can be expressed as [5]

Y (ejωT ) = 1M

M−1∑k=0

X1(ej(ωT1−2πk/M)). (2.5)

The sampling period of y(n) is T = MT1 with T1 being the sampling period forx1(m). Figure 2.5 shows the intermediate sequence and the output sequence ofthe signal. The output sequence consists of a sum of shifted, expanded replicas ofthe original signal. The stopband attenuation of the filter should be in such a waythat the signal x1(m) is not attenuated and high enough to prevent the aliasedcomponents. The signal x1(m) must be band limited to π

M [5].

2.4 Sampling Rate Conversion by a RationalFactor 7

Figure 2.2. Original sequence and the upsampled sequence by a factor of 3.

2.4 Sampling Rate Conversion by a RationalFactor

Sections 2.2 and 2.3 discussed the increasing or decreasing the sampling rate by aninteger factor. This section gives a brief introduction on increasing the samplingrate by a rational factor.

The sampling rate can be increased by a factor of LM with L > M , where L

and M are integers [5]. This sampling rate is achieved first by interpolating witha factor of L and then decimating by a factor of M , as shown in Fig. 2.6. Thestopband edge of the filter H(z) should be at ωsT = min(π/L, π/M).

Example 2.1: SRC by a rational number

Consider a signal with sampling frequency of 500 Hz where the new samplingrate has to be increased to 1600 Hz. First interpolating it with a factor 16, gives16 ∗ 500 = 8000 and then decimating it by a factor of 5 (8000/5=1600 Hz), resultsin an increase of the sampling frequency by a factor of 3.2 [6].

In Fig. 2.6, the upsampler and the filter perform the same task as discussed inSection 2.2. After the sampling rate is increased, we discard the samples we do notneed and keep the ones required. In this process, many of the samples computed viainterpolation are discarded, which is an inefficient process. To implement fractional


Figure 2.3. Spectra of the original, intermediate, and output sequences.

Figure 2.4. Decimation by a factor of M .

2.4 Sampling Rate Conversion by a RationalFactor 9

Figure 2.5. Spectra of the filtered x1(m) and the decimated sequence.

Figure 2.6. Sampling rate converter for conversion by a rational factor L/M .


interpolation and decimation effectively, there are many advanced techniques [5].One efficient way is the polyphase interpolation and decimation.

2.5 Polyphase Interpolation and DecimationStructures

2.5.1 Polyphase RepresentationThis is a three-step process. First, M signals are formed from h(n), where h(n) isa sum of M partial signals [5]

hi(n) = h(nM + i), i = 0, 1, 2.....,M − 1. (2.6)

Second, the hi(n) are upsampled by M , i.e.,

h(M)i (n) =

{hi( nM ) for n = 0,±L,±2L..

0 otherwise. (2.7)

Third, summing all the shifted versions of h(M)i (n) as

h(n) =M−1∑i=0

h(M)i (n− i). (2.8)

The polyphase representation of a signal h(n) in the z-domain is [5]

H(z) =M−1∑i=0

z−iHi(zm), (2.9)

whereHi(z) =

∞∑n=0

hi(n)z−n =∞∑n=0

hi(nM + i)z−n. (2.10)

2.5.2 Noble IdentitiesThe noble identities allows to move the order of upsampling/downsampling and fil-tering [7]. Figure 2.9 shows the representation of the noble identities. Combinationof the polyphase representation and noble identities gives the efficient realizationof multirate structures. For example with M=2, the polyphase representation ofH(z) is derived from Eq. (2.9) as

H(z) = H0(z2) + z−1H1(z2). (2.11)

From the above equation, H(z) is an addition of two subfilters and a delay shownin Fig. 2.7. Using the noble identities, the upsampler is moved forward as shownin Fig. 2.7. In reality the polyphase interpolator is realized as shown in Fig. 2.10,where a device called commutator is used instead of summation at the output.

2.5 Polyphase Interpolation and DecimationStructures 11

Figure 2.7. (a) Interpolation by two, (b) obtained structure utilizing polyphase repre-sentation from Eq. 2.11, (c) restructured of (b), (d) polyphase interpolator using nobleidentities and (e) polyphase interpolator with commutator.


Figure 2.8. (a) Decimation by 2, (b) polyphase decimator for M=2, and (c) polyphasedecimator with commutator.

At each time instant, the inputs of the summation has only one non-zero sample,so the output can be taken alternatively, beginning from the upper branch. Adecimator is derived from the interpolator by reversing the signal-flow graph andreplacing the upsampler by a downsampler [8] which is shown in Fig. 2.8. Thepolyphase interpolator and decimator are shown in Figs. 2.10 and 2.11. In thesestructures, all the subfilters operate at the lower sampling rate which leads toeffective interpolation and decimation.

2.6 Converters with Time-Varying CoefficientsIn the polyphase interpolation/decimation we haveM parallel subfilters. If all thesubfilters are FIR filters with direct form structures, then it is possible to sharethe delay elements between the subfilters. The interpolator/decimator can berealised by changing the filter coefficients periodically, that is with time-varyingcoefficients. The interpolator can be realized by a filter with periodically time-varying coefficients [5], as illustrated in Fig 2.12.

The input signal x(n) is fed into a chain of Ni cascaded delay elements, whereNi denotes the order of the filter. The content in the delay elements are multiplied

2.6 Converters with Time-Varying Coefficients 13

Figure 2.9. Noble identities.

Figure 2.10. Polyphase interpolator.

Figure 2.11. Polyphase decimator.


by the impulse response values of hi(n), hi(n)=h(nM + i), i = 0, 1, ...,M − 1 [5].The output signal y(m) at the time instance nM + i is [5]

y(nM + i) =Ni∑k=0

hi(k)x(n− k) (2.12)

Figure 2.12. Interpolator realization using time-varying coefficients, m = nM + i andki is the largest integer smaller than or equal to (N − i)/M .

Chapter 3

Flexible Interpolators andDecimators

3.1 IntroductionThis chapter gives a brief introduction to the Farrow structure, interpolation/dec-imation filters, SRC utilizing the Farrow structure, and linear-phase FIR interpo-lation and decimation utilizing the Farrow structure.

The Farrow structure based interpolators and decimators have been used forconverting sampling rate from 44.1 KHz to 48 KHz in digital audio [9]. TheFarrow structure based interpolators are used in applications like symbol timingrecovery in QAM demodulation receiver [9], echo cancellation in digital modemsand sampling rate equalization in WIMAX and GSM communication systems [9].

3.2 Farrow StructureThe efficient way of implementing the polyphase interpolation/decimation filtersare by using the Farrow structure. The Farrow structure is composed of fixed FIRfilters. The output of each filter is obtained after a delay of a single unit from theprevious filter output [9]. Figure 3.1 shows the Farrow structure. The transferfunction is [8]

H(z) =L∑k=0

Gk(z)dkm, m = 1, 2, .....M − 1 (3.1)

whereG0(z), G1(z), .... GK(z) are linear-phase FIR filters and dm are the fractional-delay coefficients. The filters Gk(z) are designed to obtain a fractional-delay filterH(z) = z−dm [7]. If the fractional-delay coefficient value is the same for all inputs,the Farrow structure gives the delayed version of inputs, with a delay dm. TheFarrow structure used in this thesis is shown in Fig. 3.1.

15

16 Flexible Interpolators and Decimators

Figure 3.1. Farrow structure.

3.3 Farrow Structure for SRCIn the polyphase interpolation and decimation structures, if the SRC ratio changes,new filters are needed which limits the flexibility of interpolating and decimatingwith different SRC ratios. The polyphase interpolation and decimation structureslead to a large number of coefficients and more memory is required if the inter-polation/decimation factor is high. This can be solved elegantly by utilizing theFarrow structure [10].

To perform any integer SRC, it is required to modify the fractional-delay valuesrequired by the Farrow structure and, it is possible to use one set of subfilters [11].A delayed version of the input signal is generated by the Farrow structure, whendm is constant for all input samples [11]. The Farrow structure performs SRC, ifthe dm value changes for every input signal.

For example re-sampling a 8 KHz signal to 44.1 KHz, requires interpolation by441 and decimation by 80. For these conversions, the polyphase interpolation anddecimation structures are not preferable. Hence, SRC utilizing Farrow structureare preferred [10]. For more literature on SRC utilizing Farrow structure we referto [8], [7], [12].

The interpolation/decimation filters in [8] uses the modified Farrow structureshown in Fig. 3.2. But in this thesis the Farrow structure shown in Fig. 3.1 isused. There is no different in these two structures, the structure shown in Fig. 3.1is used because, it is easy to implement in VHDL.

3.4 Linear-Phase FIR Interpolation and Decima-tion Utilizing the Farrow Structure

This section gives the introduction of the interpolation and decimation filter trans-fer function proposed in [8] and a brief description on linear-phase FIR interpolator

3.4 Linear-Phase FIR Interpolation and Decimation Utilizing the Far-row Structure 17

Figure 3.2. Modified Farrow structure

and decimator. For the design of the interpolation and decimation filters we referto [8].

The filters proposed in [8] are based on the properties of interpolation anddecimation filters polyphase components. The transfer function of the polyphasecomponents is written as [8]

H(z) =M−1∑m=0

z−mHm(zM ) (3.2)

where Hm(z) are polyphase components and H(z) is a linear-phase interpolationor decimation lowpass filter. The filter H(z) is to approximate z−N/2 in theideal passband region ωT ∈ [−π/M, π/M ] and zero in the ideal stopband ωT ∈[−π,−π/M ]∪ [π/M, π] [8]. This approximation is achieved when the delay of eachz−mHm(zM ) approximates z−N/2 in the passband region [8]. That is,

z−mHm(zM ) ≈ z−N/2

Hm(zM ) ≈ z−((N/2)−m)

Hm(z) ≈ z−((N/2)−m)/M . (3.3)From Eq. 3.3, it follows that Hm(z) is an allpass filter with a fractional delayof ((N/2) − m)/M . Based on this approximation, the polyphase componentsare selected [8]. First H0(z), is an N0th-order, Type-I linear-phase FIR filter ofeven order. The selection of H0(z) ensures that H0(zM ) can approximate z−N/2,provided N satisfies [8]

N = N0M. (3.4)The polyphase components Hm(z) are realized using the Farrow structure

shown in Fig. 3.1 and the transfer functions Hm(z) are expressed as [8]

Hm(z) =L∑k=0

dkmGk(z), m = 1, 2, .....M − 1 (3.5)


Figure 3.3. Realization of the polyphase components Hm(z) and HM−m(z) in theinterpolator structure.

where Gk(z) are odd-order subfilters (linear-phase FIR filters) of order N1 and dmrepresents fractional-delay coefficients which are anti-symmetric [8]. The impulseresponse of subfilters, i.e., gk(n) = gk(N1 − n) (k is even) for symmetric andgk(n) = −gk(N1 − n) (k is odd) for anti-symmetric. The subfilters Gk(z) are hereof odd order [8].

The filter Hm(z) approximates an all-pass filter with a fractional delay ofN1/2 + dm, provided N satisfies [8]

N = (N1 + 1)M. (3.6)

The delay ((N/2)−m)/M must be equal to the delay N1/2 + dm leading to

dm = −mM

+ 12 (3.7)

where dm possess anti-symmetric according to dm = −dM−m.

3.4.1 Interpolator and Decimator structuresIn the interpolation and decimation filters, the polyphase components Hm(z) as inEq.( 3.5) have dm exhibiting anti-symmetric form, so the polyphase componentsHm(z) and HM−m(z) can be written as [8]

Hm(z) = Fm1(z) + Fm2(z) (3.8)

HM−m(z) = Fm1(z)− Fm2(z) (3.9)where

Fm1(z) =bL/2c∑k=0

d2kmG2k(z) (3.10)

3.4 Linear-Phase FIR Interpolation and Decimation Utilizing the Far-row Structure 19

Figure 3.4. Flexible intepolator structure.

Figure 3.5. Flexible decimator structure.

Fm2(z) =b(L+1)/2c∑

k=1d2k−1m G2k−1(z) (3.11)

where bL/2c is the largest integer smaller than or equal to L/2 and for b(L+1)/2cit is largest integer smaller than or equal to (L+1)/2. The polyphase componentsHm(z) and HM−m(z) can be realized simultaneously using the same dm [8]. Theeven polyphase components are realized from Fm1(z) and odd polyphase com-ponents by Fm2(z) as shown in Fig. 3.3. When M is even, dM/2 = 0 resultingin HM/2(z) = G0(z). Also note that for M = 2, the filters reduce to Type-Ilinear-phase FIR filters.

The interpolator can be realized as shown in Fig. 3.4. The wide arrow betweenGk(z) and dkm indicates L + 1 parallel signals. The interpolator structure hasthree main blocks, they are H0(z), Gk(z) and dkm, where H0(z) is a linear-phaseFIR filter of even order and Gk(z) are linear-phase FIR subfilters of odd order.The block dkm contains all the fractional-delay multipliers and adders to formthe polyphase component outputs. The decimator structure is a transpose ofinterpolator structure and is shown in Fig. 3.5.


h(0) = −0.00194202018921064 h(1) = 0.00454034034339180h(2) = −0.00852167200160272 h(3) = 0.0137483480181378h(4) = −0.0198982811398188 h(5) = 0.0264294829651506h(6) = −0.0326345311590520 h(7) = 0.0377645426334144h(8) = −0.0411489015845974 h(9) = 1.04233196249064h(10) = −0.0411489015845974 h(11) = 0.0377645426334144h(12) = −0.0326345311590520 h(13) = 0.0264294829651506h(14) = −0.0198982811398188 h(15) = 0.0137483480181378h(16) = −0.00852167200160272 h(17) = 0.00454034034339180h(18) = −0.00194202018921064

Table 3.1. Impulse response of The filter H0(z) .

By adding additional dkm (converter) to the same filters (H0(z),Gk(z)) severalinterpolators can be implemented simultaneously [8].

3.5 Filter DesignThe specification of the overall lowpass filter is

1− δc ≤ HR(ωT ) ≤ 1 + δc, ωT ∈ [0, ωcT ]

−δs ≤ HR(ωT ) ≤ δs, ωT ∈ [ωsT, π]

The frequency response of the overall filter can be written as

H(ejωT ) = e−jNωT/2HR(ωT ) (3.12)

where

HR(ωT ) = h(N2 ) + 2N/2∑n=1

h(N2 − n) cos(ωTn). (3.13)

HR(ωT ) is the real zero-phase frequency response of H(z). The passband edgeis at ωcT = π/M − δ, δ > 0, and the stopband edge is assumed to be at π/Mor π/M + δ. Refer to the paper [8] for optimization problem. The values for Land N1 are selected in a proper way. The value of L is selected from the outlineof [13]. The values of L and N1 are more or less independent of M . In this thesisthe specifications of the filter are ωcT = 0.5π/M , ωsT = π/M , δc = 0.01, andδs = 0.001. We have L = 5 and N1 = 17. The impulse response of filter H0(z) isshown in Table 3.1.

The impulse responses of the subfilters Gk(z) are shown in Tables 3.2 and 3.3.The coefficients of the filter H0(z) and subfilters Gk(z) are rounded to its respec-tive wordlength. The WL=6 for 8-bit interpolator/decimator, WL=14 for 16-bitinterpolator/decimator. The extra 2-bits are sign bit and gaurd bit.

h0_rounded_values = round(h0. ∗ 2WL);The wordlength issues and rounding of coefficients are dissused in Chapter 4.

3.5 Filter Design 21

g0(0) = g0(17) = 0.000423907467491607 g1(0) = −g1(17) = −0.0109728339316476 g2(0) = g2(17) = 0.00652113896386274g0(1) = g0(16) = −0.00278295410277547 g1(1) = −g1(16) = 0.0234310454071153 g2(1) = g2(16) = 0.000591968269721275g2(2) = g0(15) = 0.00778067242572729 g1(2) = −g1(15) = −0.0413749136266392 g2(2) = g2(15) = −0.0205320521637790g0(3) = g0(14) = −0.0168907327062642 g1(3) = −g1(14) = 0.0644759089718694 g2(3) = g2(14) = 0.0612896265404087g0(4) = g0(13) = 0.0321984118929472 g1(4) = −g1(13) = −0.0922640172379841 g2(4) = g2(13) = −0.133493198955283g0(5) = g0(12) = −0.0573660539510253 g1(5) = −g1(12) = 0.125327062310421 g2(5) = g2(12) = 0.254278225776589g0(6) = g0(11) = 0.101173603068474 g1(6) = −g1(11) = −0.170620446486171 g2(6) = g2(11) = −0.460641755519091g0(7) = g0(10) = −0.195576074607548 g1(7) = −g1(10) = 0.276472056339943 g2(7) = g2(10) = 0.858339506719040g0(8) = g0(9) = 0.630911493115840 g1(8) = −g1(9) = −1.41645954052583 g2(8) = g2(9) = −0.562485073259150g0(9) = 0.630911493115840 g1(9) = 1.41645954052583 g2(9) = −0.562485073259150g0(10) = −0.195576074607548 g1(10) = −0.276472056339943 g2(10) = 0.858339506719040g0(11) = 0.101173603068474 g1(11) = 0.170620446486171 g2(11) = −0.460641755519091g0(12) = −0.0573660539510253 g1(12) = −0.125327062310421 g2(12) = 0.254278225776589g0(13) = 0.0321984118929472 g1(13) = 0.0922640172379841 g2(13) = −0.133493198955283g0(14) = −0.0168907327062642 g1(14) = −0.0644759089718694 g2(14) = 0.0612896265404087g0(15) = 0.00778067242572729 g1(15) = 0.0413749136266392 g2(15) = −0.0205320521637790g0(16) = −0.00278295410277547 g1(16) = −0.0234310454071153 g2(16) = 0.000591968269721275g0(17) = 0.000423907467491607 g1(17) = 0.0109728339316476 g2(17) = 0.00652113896386274

Table 3.2. Impulse response of subfilters G0(z), G1(z), G2(z) .

g3(0) = −g3(17) = 0.0230531771718914 g4(0) = g4(17) = −0.0144582304123203 g5(0) = −g5(17) = −0.0261187500245253g3(1) = −g3(16) = −0.0481196802026734 g4(1) = g4(16) = 0.00981255694128763 g5(1) = −g5(16) = 0.0276963781252532g3(2) = −g3(15) = 0.0881736860353809 g4(2) = g4(15) = −0.000128371336298092 g5(2) = −g5(15) = −0.0507124665033307g3(3) = −g3(14) = −0.142618195943465 g4(3) = g4(14) = −0.0243954182405235 g5(3) = −g5(14) = 0.0826663269995300g3(4) = −g3(13) = 0.213454578972985 g4(4) = g4(13) = 0.0713389242773704 g5(4) = −g5(13) = −0.124595433292440g3(5) = −g3(12) = −0.309319397018928 g4(5) = g4(12) = −0.149652156731981 g5(5) = −g5(12) = 0.181715257148404g3(6) = −g3(11) = 0.468143061661191 g4(6) = g4(11) = 0.266291694614042 g5(6) = −g5(11) = −0.271784653712511g3(7) = −g3(10) = −0.891617508351147 g4(7) = g4(10) = −0.332995472022681 g5(7) = −g5(10) = 0.406465991108432g3(8) = −g3(9) = 1.46338807208500 g4(8) = g4(9) = 0.165634167120461 g5(8) = −g5(9) = −0.525717051152087g3(9) = −1.46338807208500 g4(9) = 0.165634167120461 g5(9) = 0.525717051152087g3(10) = 0.891617508351147 g4(10) = −0.332995472022681 g5(10) = −0.406465991108432g3(11) = −0.468143061661191 g4(11) = 0.266291694614042 g5(11) = 0.271784653712511g3(12) = 0.309319397018928 g4(12) = −0.149652156731981 g5(12) = −0.181715257148404g3(13) = −0.213454578972985 g4(13) = 0.0713389242773704 g5(13) = 0.124595433292440g3(14) = 0.142618195943465 g4(14) = −0.0243954182405235 g5(14) = −0.0826663269995300g3(15) = −0.0881736860353809 g4(15) = −0.000128371336298092 g5(15) = 0.0507124665033307g3(16) = 0.0481196802026734 g4(16) = 0.00981255694128763 g5(16) = −0.0276963781252532g3(17) = −0.0230531771718914 g4(17) = −0.0144582304123203 g5(17) = 0.0261187500245253

Table 3.3. Impulse response of subfilters G3(z), G4(z), G5(z) .

Chapter 4

VHDL Implementation

4.1 IntroductionIn this thesis work, the linear-phase FIR interpolator and decimator are imple-mented in VHDL (VHSIC Hardware Description Language) where VHSIC standsfor Very High Speed Integrated Circuits. A brief introduction to the linear-phaseFIR interpolator and decimator was given in Chapter 2.

The VHDL is intended for the circuit simulations and synthesis but not all theVHDL designs are synthesizable. The main applications of VHDL are in CPLDs(Complex Programmable Logic Devices), FPGAs (Field programmable Gate Ar-rays) and in the field of ASICs (Application Specific Integrated Circuits). TheVHDL code can be simulated, synthesized and implemented using several EDAtools [14]. Some EDA tools are Altera’s Quartus II, for Altera’s CPLD/FPGAand Xilinx’s ISE suite, for Xilinx’s CPLD/FPGA. In this thesis work, the VHDLcode is simulated in Modelsim, version Modelsim.SE 6.4 and compiled in QuartusII for timing analysis and register usage.

VHDL is mostly used for simulation and synthesis of electronic designs. Theprocess of compiling and mapping the VHDL code into an FPGA or an ASICis called synthesis. All the VHDL constructs are not suitable for synthesis. Forexample, the construct ’wait for 10 ns’ is not synthesizable but valid for simu-lations. The tools for synthesis of VHDL are inexpensive when compared withASIC synthesis tools. Both the hardware design and testbenches are portablebetween design tools and vendors. The VHDL provides technology independentdesign [14]. To implement the design in new technology, we can go back to thebehavioral VHDL description and then implement it the new technology knowingthe correct functionality is preserved [14].

4.2 Fixed Point PackageA package called Ieee_proposed.fixed_pkg is used for implementing the fractional-delay block (dkm) in the interpolator and decimator. The fixed point package

23

24 VHDL Implementation

Simulation tool ModelSim SE-64 6.4a, MATLAB, Quartus-IIH0(z)alinear − phaseFIRfilter order=18Gk(z) subfilters order=17L=5 k=0,1,2...5

Table 4.1. Table of specification.

Operation Result RangeA+B Max(A’left, B’left)+1 downto Min(A’right, B’right)A-B Max(A’left, B’left)+1 downto Min(A’right, B’right)A*B A’left + B’left +1 downto A’right + B’rightA rem B Min(A’left, B’left) downto Min(A’right, B’right)

Table 4.2. Table for operation sizing rules.

(ieee_proposed.fixed_pkg) has the advantage of representing the numbers lessthan 1.0 and rational values which has a fixed decimal point. Fixed point is a stepbetween integer math and floating point [1]. Fractional valued multipliers are usedin the interpolators and decimators. This package is used for the fractional or ra-tional multiplication and addition operations. Table 4.2 shows the operation sizingrules. For more information we refer to the fixed point package user’s guide [1].

4.3 VHDL Implementation of the InterpolatorThe flowchart in Fig. 4.1 explains the step-by-step procedure flow of implementingthe linear-phase FIR interpolator. The filter H0(z) has to be implemented insuch a way that the design has to be re-used for a subfilter implementation. Thefilter H0(z) coefficients are fixed, so the coefficients are given as constants in theimplementation instead of giving them as inputs. The subfilters Gk(z) block hassix subfilters with different coefficients but of same order. Instead of designing sixsubfilters, a subfilter can be designed by making coefficients as inputs. Therefore,six subfilters are implemented by instantiating the subfilter six times.

4.3.1 VHDL Implementation of the Filter H0(z)The transfer function of an FIR filter is [4]

H(z) =N−1∑k=0

h[k]z−k. (4.1)

In the time domain, we have

y[n] =N−1∑k=0

h[k]x[n− k]. (4.2)

4.3 VHDL Implementation of the Interpolator 25

Figure 4.1. Flowchart for implementing the interpolator.

The input signal is stored in the shift registers and the output of the shift registersis connected to the multipliers and then to the adders as shown in Fig. 4.2. TheVHDL code of filter H0(z) is shown in 4.1. It is very important that the VHDLcode is written in such a way that it is reusable or shared. It should be as genericas possible. By changing the order, XIN_WL and COEF_WL in line 13, anFIR filter of any order and wordlength can be implemented. The filter H0(z) hasfixed coefficients, so they can be given as constants, shown in lines 36 and 37.When RST is HIGH the coefficients are converted to signed bits. When RST isLOW the input signal stored in the shift registers is multiplied with coefficientsand then added, as shown in between lines 55-64.

Listing 4.1. VHDL code for filter H0(z)

1 −−−−−−−−−−−−−−−−−−−−− H0_FIR FILTER −−−−−−−−−−−


Figure 4.2. RTL representation of FIR filter.

2 −−−−−−−−−−−−−−−−−−−−−− MAIN CODE −−−−−−−−−−−−−−−−−−−−3 LIBRARY IEEE ;4 USE IEEE . STD_LOGIC_1164 . ALL ;5 USE IEEE .NUMERIC_STD. ALL ;6 USE IEEE . STD_LOGIC_unsigned . ALL ;7 LIBRARY WORK;8 USE WORK. ALL ;9 −−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−

10 −−−−−−−−−−−−−−−−−−−−−−− ENTITY −−−−−−−−−−−−−−−−−−−−−−11 −−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−12 ENTITY H0_FILTER_16BIT IS13 GENERIC (ORDER : INTEGER: = 1 8 ;XIN_WL: INTEGER: = 1 6 ;COEF_WL: INTEGER:=16) ;14 −−−−−WL IS XIN_WL. IT IS WORD LENGTH OF THE INPUT SIGNAL .15 −−−−−COEF_WL IS WORD LENGTH OF THE COEFFICIENTS OR TAPS .16 PORT(17 CLK, RST : IN STD_LOGIC ;18 XIN : IN SIGNED(XIN_WL−1 DOWNTO 0) ;−−−−−−−INPUT PORT19 YOUT: OUT SIGNED ( (XIN_WL+COEF_WL−1) DOWNTO 0)−−−−OUTPUT PORT2021 ) ;22 END H0_FILTER_16BIT ;2324 −−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−25 −−−−−−−−−−−−−−−−−−− ARCHITECTURE −−−−−−−−−−−−−−−−−−−−2627 ARCHITECTURE BEHAVIOURAL OF H0_FILTER_16BIT IS28 −−−−−−SIG_ARR IS D−FLIP_FLOP ARRAY.29 TYPE SIG_ARR IS ARRAY (ORDER−1 DOWNTO 0) OF SIGNED(XIN_WL−1 DOWNTO 0) ;30 −−−COEFFICIENTS31 TYPE COEF_ARR IS ARRAY (ORDER DOWNTO 0) OF SIGNED(COEF_WL−1 DOWNTO 0) ;32 type COEFFICIENTS i s a r r a y (0 to o r d e r ) o f i n t e g e r ;33 −−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−34 −−−−−−−−−−−−−−−−−−−− SIGNALS −−−−−−−−−−−−−−−−−−−−−−−−35 SIGNAL DFF: SIG_ARR ;36 CONSTANT COEF_H0: COEFFICIENTS:=( −60 ,92 , −159 ,247 , −336 ,430 , −517 ,593 , −638 ,37 17040 , −638 ,593 , −517 ,430 , −336 ,247 , −159 ,92 , −60) ;38 BEGIN39 −−−−−−−−−−−−−−−−− PROCESS −−−−−−−−−−−−−−−−−−−−−−−−−−−40 INTAL :PROCESS(CLK, RST)41 VARIABLE M_OUT,ADD_OUT: SIGNED ( (XIN_WL+COEF_WL−1) DOWNTO 0) :=(OTHERS= > '0 ') ;42 v a r i a b l e COEF:COEF_ARR;43 BEGIN44 IF (RST= '1 ') THEN45 FOR I IN ORDER−1 DOWNTO 0 LOOP46 f o r j i n XIN_WL−1 downto 0 l o o p47 DFF( I ) ( j ) <= '0 ';48 end l o o p ;49 END LOOP;50 −−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−51 FOR I IN 0 TO ORDER LOOP52 COEF( I ) := t o_s ig ned (COEF_H0( i ) ,COEF_WL) ;53 END LOOP;54 −−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−55 ELSIF RISING_EDGE(CLK) THEN56 ADD_OUT:= COEF( 0 ) ∗XIN ;57 FOR I IN 1 TO ORDER−1 LOOP58 M_OUT:=COEF( I ) ∗DFF(ORDER−1−I ) ;59 ADD_OUT:=ADD_OUT+M_OUT;60 END LOOP;


61 DFF<= XIN & DFF(ORDER−1 DOWNTO 1) ;62 end i f ;63 YOUT<=ADD_OUT;64 END PROCESS;65 END BEHAVIOURAL;

4.3.2 VHDL Implementation of the Subfilters Gk(z)In the block Gk(z) we have six subfilters. Instead of implementing six differentsubfilters, it is efficient to implement one subfilter and it can be instantiated L-times (L=5, where k=0,1,2,3,4,5) to implement the Gk(z) block. The coefficientsare different for every subfilter. A subfilter can be implemented from the filter codeof H0(z), by changing the coefficients to inputs instead of constants. Figure. 4.3shows the instantiation of six subfilters forming the block Gk(z). The VHDL codefor the subfilter is given in the appendix A.1.1.

Figure 4.3. The Gk(z) block with six subfilters.

The VHDL code for the block Gk(z) is shown 4.2. The subfilter namedFIR_FILTER_16BIT is declared first, which is shown in between lines 31-38. From line 36 it is clear that the subfilter has an input port for coefficientsand the input port is of type SIG_16, which is a special array declared in theuser package. The user package is shown in the appendix. The coefficients ofsix subfilters are declared in between lines 42-53. In the process (lines 65-89)the coefficients are converted into signed bits. The process executes when thereis a change in the reset. All the subfilters instantiated between lines 93-104 areexecuted simultaneously.

Listing 4.2. VHDL code for block Gk(z)

12 −−−−−MAIN CODE−−−−−−−−−−−−−3 LIBRARY IEEE ;


4 USE IEEE . STD_LOGIC_1164 . ALL ;5 USE IEEE .NUMERIC_STD. ALL ;6 USE WORK.PKG_SIGNED. ALL ;−−−−−−−−−USER DEFINED PACKAGE7 use IEEE . STD_LOGIC_unsigned . ALL ;8 USE STD . TEXTIO . ALL ;9 LIBRARY WORK;

10 USE WORK. ALL ;11 −−−−−−−−−−−−−−−−−12 −−ENTITY−−−−−−−−1314 ENTITY FARROW_STRUCTURE_16BIT IS15 GENERIC(F : INTEGER: = 6 ;WL: INTEGER: = 1 6 ;16 COEF_WL: INTEGER: = 1 6 ;ORDER: INTEGER:=17) ;17 PORT(18 CLK, RST : IN STD_LOGIC;19 XIN : IN SIGNED(WL−1 DOWNTO 0) ;20 FOUT :OUT SIG_32 (1 TO F)−−−− CHANGE WHEN WL IS CHANGED2122 ) ;23 END FARROW_STRUCTURE_16BIT;2425 −−−−−−−−−−−−−−−ARCHITECTURE2627 ARCHITECTURE BEHAV OF FARROW_STRUCTURE_16BIT IS2829 −−−−−−−−−−−−−−−−−−COMPONENT DECLARATION30 −−−−−−−−−−−−−−−−−− SUB−FILTER(G(Z) )−−−−31 COMPONENT FIR_FILTER_16BIT IS32 GENERIC (WL: INTEGER) ;33 PORT(34 CLK, RST : IN STD_LOGIC ;35 XIN : IN SIGNED(WL−1 DOWNTO 0) ;36 COEF: IN SIG_16 (0 TO ORDER) ;37 YOUT: OUT SIGNED(2∗WL−1 DOWNTO 0)38 ) ;39 END COMPONENT;40 −−−−−−−−−−−−ARRAY DECLARATION41 type c o e f f i c i e n t s i s a r r a y (0 to o r d e r ) o f i n t e g e r ;42 c o n s t a n t coef_1 : c o e f f i c i e n t s :=(33 , −69 ,164 , −323 ,582 , −989 ,1699 , −3230 ,43 10348 ,10348 , −3230 ,1699 , −989 ,582 , −323 ,164 , −69 ,33) ;44 c o n s t a n t coef_2 : c o e f f i c i e n t s :=( −254 ,462 , −711 ,1058 , −1510 ,1978 , −2706 ,45 4361 , −23066 ,23066 , −4361 ,2706 , −1978 ,1510 , −1058 ,711 , −462 ,254) ;46 c o n s t a n t coef_3 : c o e f f i c i e n t s :=( −101 ,110 , −636 ,1410 , −2635 ,4605 , −7911 ,14322 ,47 −9288 , −9288 ,14322 , −7911 ,4605 , −2635 ,1410 , −636 ,110 , −101) ;48 c o n s t a n t coef_4 : c o e f f i c i e n t s :=(62 , −973 ,1276 , −1983 ,3213 , −4208 ,6917 , −1328249 ,23043 , −23043 ,13282 , −6917 ,4208 , −3213 ,1983 , −1276 ,973 , −62) ;50 c o n s t a n t coef_5 : c o e f f i c i e n t s :=( −388 , −259 ,801 , −1357 ,2033 , −3390 ,5255 , −6306 ,51 3064 ,3064 , −6306 ,5255 , −3390 ,2033 , −1357 ,801 , −259 , −388) ;52 c o n s t a n t coef_6 : c o e f f i c i e n t s :=(44 , −139 , −43 ,99 , −157 ,347 , −1143 ,3033 ,53 −4898 ,4898 , −3033 ,1143 , −347 ,157 , −99 ,43 ,139 , −44) ;54 −−−−−−−−−−−−−−SIGNALS DECLERATION55 SIGNAL FIR_OUT: SIG_32 (1 TO F) ; −−−−−−−−−−CHANGE COEF_WL CHANGES56 SIGNAL COEF_FARROW_1: SIG_16 (1 TO ORDER+1) ;−−CHANGE COEF_WL CHANGES57 SIGNAL COEF_FARROW_2: SIG_16 (1 TO ORDER+1) ;−−CHANGE COEF_WL CHANGES58 SIGNAL COEF_FARROW_3: SIG_16 (1 TO ORDER+1) ;−−CHANGE COEF_WL CHANGES59 SIGNAL COEF_FARROW_4: SIG_16 (1 TO ORDER+1) ;−−CHANGE COEF_WL CHANGES60 SIGNAL COEF_FARROW_5: SIG_16 (1 TO ORDER+1) ;−−CHANGE COEF_WL CHANGES61 SIGNAL COEF_FARROW_6: SIG_16 (1 TO ORDER+1) ;−−CHANGE COEF_WL CHANGES62 −−SIGNAL TEST :D_ARRAY;63 BEGIN6465 PROCESS( r s t )66 VARIABLE COEF_VAR_1: SIG_16 (1 TO ORDER+1) ;−−CHANGE COEF_WL CHANGES67 VARIABLE COEF_VAR_2: SIG_16 (1 TO ORDER+1) ;−−CHANGE COEF_WL CHANGES68 VARIABLE COEF_VAR_3: SIG_16 (1 TO ORDER+1) ;−−CHANGE COEF_WL CHANGES69 VARIABLE COEF_VAR_4: SIG_16 (1 TO ORDER+1) ;−−CHANGE COEF_WL CHANGES70 VARIABLE COEF_VAR_5: SIG_16 (1 TO ORDER+1) ;−−CHANGE COEF_WL CHANGES71 VARIABLE COEF_VAR_6: SIG_16 (1 TO ORDER+1) ;−−CHANGE COEF_WL CHANGES72 BEGIN7374 FOR i IN 0 TO order −1 LOOP75 COEF_VAR_1( I +1):=TO_SIGNED(COEF_1( I ) ,COEF_WL) ;76 COEF_VAR_2( I +1):=TO_SIGNED(COEF_2( I ) ,COEF_WL) ;77 COEF_VAR_3( I +1):=TO_SIGNED(COEF_3( I ) ,COEF_WL) ;78 COEF_VAR_4( I +1):=TO_SIGNED(COEF_4( I ) ,COEF_WL) ;79 COEF_VAR_5( I +1):=TO_SIGNED(COEF_5( I ) ,COEF_WL) ;80 COEF_VAR_6( I +1):=TO_SIGNED(COEF_6( I ) ,COEF_WL) ;81 END LOOP;8283 COEF_FARROW_1<=COEF_VAR_1;84 COEF_FARROW_2<=COEF_VAR_2;85 COEF_FARROW_3<=COEF_VAR_3;86 COEF_FARROW_4<=COEF_VAR_4;87 COEF_FARROW_5<=COEF_VAR_5;88 COEF_FARROW_6<=COEF_VAR_6;89 END PROCESS;9091 −−−−−−−−−−−−−−COMPONENT INSTANTIATED9293 FIR1 : FIR_FILTER_16BIT GENERIC MAP(WL) PORT MAP(CLK, RST, XIN ,COEF_FARROW_6,94 FIR_OUT( 1 ) ) ;−− FIRST SUBFILTER


95 FIR2 : FIR_FILTER_16BIT GENERIC MAP(WL) PORT MAP(CLK, RST, XIN ,COEF_FARROW_5,96 FIR_OUT( 2 ) ) ;−− SECOND SUBFILTER97 FIR3 : FIR_FILTER_16BIT GENERIC MAP(WL) PORT MAP(CLK, RST, XIN ,COEF_FARROW_4,98 FIR_OUT( 3 ) ) ;−− THIRD SUBFILTER99 FIR4 : FIR_FILTER_16BIT GENERIC MAP(WL) PORT MAP(CLK, RST, XIN ,COEF_FARROW_3,

100 FIR_OUT( 4 ) ) ;−− FOURTH SUBFILTER101 FIR5 : FIR_FILTER_16BIT GENERIC MAP(WL) PORT MAP(CLK, RST, XIN ,COEF_FARROW_2,102 FIR_OUT( 5 ) ) ;−− FIFTH SUBFILTER103 FIR6 : FIR_FILTER_16BIT GENERIC MAP(WL) PORT MAP(CLK, RST, XIN ,COEF_FARROW_1,104 FIR_OUT( 6 ) ) ;−− SIXTH SUBFILTER105106 FOUT<=FIR_OUT;107 END BEHAV;

4.3.3 VHDL Implementation of the Delay Block dkm

Figure 4.4. Block diagram for VHDL implementation of the interpolator.

Figure 4.4 shows how an interpolator is implemented in VHDL. The filterH0(z) and subfilters Gk(z) are instantiated first and then the delay block code iswritten. The components H0(z), Gk(z) instantiation is showed in between lines31-44 in 4.3. These components are declared in lines 58 and 59. The output ofGk(z) is connected to a signal SOUT and the output of H0(z) is connected to asignal H0_SIGN .

The delay block dkm consists ofM−1 delay multiplier chain blocks, whereM isinterpolation factor. Each delay multiplier chain block gives one polyphase com-ponent Hm, where m = 1, 2..,M − 1. The filter H0(z) gives the zeroth polyphasecomponent H0. The lower part of Fig. 4.5 shows a delay multiplier chain block.The Fig. 4.5 shows how the subfilters and delay multiplier chain block can forma Farrow structure. The sampled value from subfilter G5(z) is multiplied by thefractional-delay multiplier value and then added to the sampled value from thesubfilter G4(z). This value is again multiplied with the fractional-delay multi-plier value and then added to the sampled value of subfilter G3(z), this processends after adding the sampled value from the subfilter G0(z) as shown betweenlines 110-117 in the code below. The values dm are generated using Eq. (4.3).


Even Factor M = 8 Odd Factor M = 5d0=1/2 d0=1/2d1=3/8 d1=3/10d2=1/4 d2=1/10d3=1/8 d3=-1/10d4=0 d4=-3/10d5=-1/8d6=-1/4d7=-3/8

Table 4.3. Fractional-delay multiplier values for M = 8 and M = 5.

Equation. (4.3) is a modified form of Eq. (4.4).

dm+1 = −1M

+ dm (4.3)

where d0 = 1/2.dm = −m

M+ 1

2 (4.4)

The generation of fractional-delay multiplier value (dm) is shown in between lines93-103. The values dm for M=8 and M=5 are given in Table 4.3. The Fractional-delay multiplier values are converted into binary representation using ’to_sfixed’.Example 3.1 shows how a fractional number is converted into binary. As theaddition and multiplication rules are different compared with the normal binaryaddition and multiplication, truncation of bits are required. RESIZE is used fortruncating the bits and an example is shown below.

Example 4.1: conversion and resizingvariable ADD(16downto− 5);ADD:=0000000000000000.00000 initially.ADD := to_sfixed(15.5, ADD);The binary value of ADD is: ADD:=0000000000001111.10000.

To change the wordlength from 16-bit to 8-bitvariable size_ADD (8downto− 5)size_ADD := resize(ADD, size_ADD);size_ADD=00001111.10000

Figure 4.6 shows how a delay multiplier chain block for 16-bit interpolator isimplemented and also shows where truncation of bits is performed. The sampledvalues of the subfilters are 16-bit (15 downto 0) and it is multiplied with 8-bit(2 downto -5) delay multiplier dm value results in 24-bit (18 downto -5). Themultiplied value is added to the 16-bit (15 downto 0) sample from the next subfilterresulting in 25-bits (19 downto -5). This 25-bit value is truncated to 16-bit (15downto 0). The dm values are small and when the sampled output of the subfilters


Figure 4.5. Subfilters and delay multiplier chain block.

are multiplied by the delay multiplier values they become very small. So five LSBand four MSB bits are truncated, line 114 from the code shows the truncation ofbits after addition.

Listing 4.3. VHDL code for the interpolator

12 −−−−−MAIN CODE−−−−−−−−−−−−−3 LIBRARY IEEE ;4 USE IEEE . STD_LOGIC_1164 . ALL ;5 USE IEEE .NUMERIC_STD. ALL ;6 l i b r a r y i e e e _ p r o p o s e d ;7 use i e e e _ p r o p o s e d . fixed_pkg . a l l ;−−−−−−−f i x e d p o i n t packages8 USE WORK.PKG_SIGNED. ALL ;−−−−−−−−−USER DEFINED PACKAGE9 use IEEE . STD_LOGIC_unsigned . ALL ;

10 use STD . t e x t i o . a l l ;11 LIBRARY WORK;12 USE WORK. ALL ;1314 −−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−ENTITY


Figure 4.6. Delay multiplier chain block with truncation.

1516 ENTITY DELAY_BLOCK_RW_16BIT IS17 GENERIC(F : INTEGER: = 6 ; WL: INTEGER: = 1 6 ; DELAY_WL: INTEGER: = 8 ;18 COEF_WL: INTEGER: = 1 6 ;IP_FACTOR: INTEGER:=2) ;19 PORT( CLK, RST : IN STD_LOGIC;20 XIN : IN SIGNED(WL−1 DOWNTO 0) ;21 FIN :OUT SIG_32 (0 TO F−1) ;−−CHANGE WHEN WL OR COEF_WL IS CHANGED22 −− CHANGE WHEN WL OR COEF_WL IS CHANGED (SPE_ARRAY) FROM PACKAGE.23 IOUT :OUT SPE_ARR_32(0 TO IP_FACTOR−1)24 ) ;25 END DELAY_BLOCK_RW_16BIT;2627 −−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−− ARCHITECTURE2829 ARCHITECTURE BEHAV OF DELAY_BLOCK_RW_16BIT IS3031 COMPONENT FARROW_STRUCTURE_16BIT IS32 PORT(CLK, RST : IN STD_LOGIC;33 XIN : IN SIGNED(WL−1 DOWNTO 0) ;34 FOUT:OUT SIG_32 (0 TO F−1)−−CHANGE WHEN WL OR COEF_WL CHANGES35 ) ;36 END COMPONENT;3738 COMPONENT H0_FILTER_16BIT IS39 PORT(40 CLK, r s t : IN STD_LOGIC;41 XIN : IN SIGNED( WL−1 DOWNTO 0 ) ;42 YOUT :OUT SIGNED(COEF_WL+WL−1 DOWNTO 0)43 ) ;44 END COMPONENT;45 −−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−ARRAY DECLERATION46 TYPE SIG_ARR_1_8 IS ARRAY (0 TO IP_FACTOR) OF SFIXED(2 DOWNTO −5) ;47 −−−IF (A+B) THEN48 TYPE SIG_ARR_9 IS ARRAY (0 TO IP_FACTOR−1) OF SFIXED(3 DOWNTO −5) ;4950 −−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−SIGNAL DECLERATION51 SIGNAL SOUT: SIG_32 (0 TO F−1) ;−−− CHANGE WHEN WL OR COEF_WL IS CHANGED52 −−− CHANGE WHEN WL OR COEF_WL IS CHANGED (SPE_ARRAY) FROM PACKAGE.53 SIGNAL WRITEOUT: SPE_ARR_32(0 TO IP_FACTOR−1) ;54 SIGNAL H0_SIGN : SIGNED(COEF_WL+WL−1 DOWNTO 0) ;55 s i g n a l t e s t : SFIXED(2 DOWNTO −5) ;56 BEGIN57 −−−−−−−−−−−−−−−−−−−−−−−−−−−−−−COMPONENT i n s t a n c a t i o n58 FARROW:FARROW_STRUCTURE_16BIT PORT MAP(CLK, RST, XIN ,SOUT) ;59 T_FIR_FILTER : H0_FILTER_16BIT PORT MAP(CLK, RST, XIN , H0_SIGN) ;60 −−−−−−−−−−−−−−−−−−−−−−−−−−−−−−− PROCESS61 PI :PROCESS(CLK, RST)62 VARIABLE Dm_SIGNED1: SIG_ARR_9 ;63 VARIABLE Dm_SIGNED : SIG_ARR_1_8 ;64 VARIABLE TEMP_IP_FACTOR: SFIXED(2 DOWNTO −5) ;65 −−−−−−CHANGE WHEN WL OR COEF_WL IS CHANGED66 VARIABLE SOUT_TEMP: SIGS_32 (0 TO F−1) ;


67 VARIABLE PROD : SFIXED(COEF_WL+WL+2 DOWNTO −5) ;68 VARIABLE ADD : SFIXED(COEF_WL+WL+3 DOWNTO −5) ;69 VARIABLE ADD_T: SFIXED(COEF_WL+WL−1 DOWNTO 0) ;70 VARIABLE H0 : SFIXED(COEF_WL+WL+3 DOWNTO −5) ;71 −−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−72 v a r i a b l e one : s f i x e d ( delay_wl −1 downto 0) ;73 v a r i a b l e M: s f i x e d ( delay_wl −1 downto 0) ;−−−−− i n t e r p o l a t i o n f a c t o r74 v a r i a b l e v a l u e : s f i x e d ( delay_wl downto −delay_wl +1) ;75 −−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−76 −−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−77 f i l e f i l e _ p o i n t e r : t e x t ;78 v a r i a b l e l i n e _ c o n t e n t : s t r i n g (1 to (DELAY_WL+COEF_WL+WL+1) ) ;79 −−− CHANGE WHEN WL OR COEF_WL IS CHANGED (SPE_ARRAY) FROM PACKAGE.80 v a r i a b l e bin_value : SPE_ARR_32(0 TO IP_FACTOR−1) ;81 v a r i a b l e bin_value_1 : SFIXED(COEF_WL+WL+3 DOWNTO −5) ;82 v a r i a b l e line_num : l i n e ;83 v a r i a b l e i , j , K, v : i n t e g e r : = 0 ;84 v a r i a b l e char : c h a r a c t e r : = ' 0 ' ;85 v a r i a b l e f i r s t t i m e : b o o l e a n := t r u e ;86 −−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−87 −−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−88 BEGIN89 −−r e p o r t " S t a r t i n g p r o c e s s PI " s e v e r i t y note ;90 i f r i s i n g _ e d g e ( c l k ) then9192 −−−−−−−−−−−−−−−−−−−−−−−−−−−−−−− GENERATING Dm VALUES93 Dm_SIGNED( 0 ) :=TO_SFIXED( 0 . 5 ,Dm_SIGNED( 0 ) ) ;94 −−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−95 M:= t o _ s f i x e d ( IP_factor ,M) ;96 one := t o _ s f i x e d ( 1 , one ) ;97 v a l u e :=( one /M) ;98 −−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−99 TEMP_IP_FACTOR:=RESIZE(−VALUE,TEMP_IP_FACTOR) ;

100 FOR I IN 0 TO IP_FACTOR−1 LOOP101 Dm_SIGNED1( I ) :=(TEMP_IP_FACTOR)+Dm_SIGNED( I ) ;102 Dm_SIGNED( I +1):=RESIZE (Dm_SIGNED1( I ) ,Dm_SIGNED( I ) ) ;103 END LOOP;104 −−−−−−−−−−−−−−−−−CONVERTING THE INTEGER 'SOUT' ,TO FIXED POINT105 FOR I IN 0 TO F−1 LOOP106 SOUT_TEMP( I ) :=TO_SFIXED(SOUT( I ) ,SOUT_TEMP( I ) ) ;107 END LOOP;108109 −−−−−−−−−−−−−−−−−−−−− MULT AND ADDING FOR EVERY INTERPOLATION FACTOR110 FOR I IN 1 TO IP_FACTOR−1 LOOP111 PROD:=SOUT_TEMP( 0 ) ∗Dm_SIGNED( I ) ;112 FOR J IN 1 TO F−1 LOOP113 ADD:=PROD+SOUT_TEMP( J ) ;114 ADD_T:=RESIZE (ADD,ADD_T) ;115 PROD:=ADD_T∗Dm_SIGNED( I ) ;116 END LOOP;117 IOUT( I )<=ADD;118 WRITEOUT( I )<=ADD;119 END LOOP;120 FIN<=SOUT;121 H0:=TO_SFIXED(H0_SIGN , H0) ;−−− c o n v e r t i n g the h0 output to s f i x e d .122 IOUT( 0 )<=H0 ;123 WRITEOUT( 0 )<=H0 ;124 t e s t <=TEMP_IP_FACTOR;125 end i f ;126 −−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−opening a f i l e and w r i t i n g to output . t x t127 i f f i r s t t i m e then128 −−Open the f i l e w r i t e . t x t from the s p e c i f i e d l o c a t i o n f o r w r i t i n g129 f i l e _ o p e n ( f i l e _ p o i n t e r , " / edu / venda501 / f i r _ f i l t e r / 1 . t x t " ,APPEND_MODE) ;130 f i r s t t i m e := f a l s e ;131 end i f ;132 BIN_VALUE:=WRITEOUT;133 FOR I IN 0 TO IP_FACTOR−1 LOOP134 BIN_VALUE_1:=BIN_VALUE( I ) ;135 K := 0 ;136 V:=WL+COEF_WL+3;137 FOR J IN V DOWNTO −5 LOOP138 IF K<(v+6) THEN139 K:=K+1;140 IF (BIN_VALUE_1( J ) = ' 1 ' ) then141 LINE_CONTENT(K) := ' 1 ' ;142 ELSIF BIN_VALUE_1( J ) = ' 0 ' then143 LINE_CONTENT(K) := ' 0 ' ;144 ELSE145 LINE_CONTENT(K) := ' 0 ' ;146 END IF ;147 END IF ;148 END LOOP;149 i f r i s i n g _ e d g e ( c l k ) then150 r e p o r t "<!−− i=" & i n t e g e r ' image ( i ) & " −−>" s e v e r i t y note ;151 w r i t e ( line_num , l i n e _ c o n t e n t ) ; −−w r i t e the l i n e .152 −−w r i t e the c o n t e n t s i n t o the f i l e .153 w r i t e l i n e ( f i l e _ p o i n t e r , line_num ) ;154 end i f ;155 end l o o p ;156 end p r o c e s s ;157 END BEHAV;


4.4 Wordlength Issues in InterpolatorIt is very important to consider the roundoff error and sign of the integer bit whileconverting into a binary value. A sign bit is used to represent the sign of thenumber and a guard bit is used to reduce the roundoff error. we have one signbit and one guard bit in a 16-bit binary value. The wordlength of coefficients forthe filter and subfilters are 14-bits. The coefficient values for the filter H0(z) andsubfilters Gk(z) are shown in the appendix.

The fractional-delay multiplier has three decimal bits and five fractional bits(2 downto -5) . There are some fractional value which cannot be exactly con-verted into a binary value. For example, d1=0.3 for M=5, after conversion thebinary value is ’000.01001’ which is not equal to 0.3. The exact fractional value of’000.01001’ is 0.28125.

4.5 VHDL Implementation of the DecimatorTo implement a decimator, the first step is to implement the delay block dkm, thesecond step is to implement the subfilters Gk(z), and then we make use of the filterH0(z) which is designed for the interpolator. The delay block dkm, the subfiltersGk(z), and the filter H0(z) are instantiated in one design to form the decimatoras shown in Fig. 4.7. The decimator is a (M -1)-input 1-output system, where Mis the decimation factor. The block diagram of the decimator is shown in Fig. 4.9.

Figure 4.7. Block diagram for VHDL implementitation of the decimator.

4.5.1 VHDL Implementation of the Delay Block dkm

The delay block consists of M -1 delay multiplier chain blocks and six adders,where M is the decimation factor. The blocks with dotted lines in Fig. 4.9are the delay multiplier chain blocks. H1, H2.........HM−1 are input samples and

4.5 VHDL Implementation of the Decimator 35

Gout(0), Gout(1)....Gout(5) are output ports to the delay block. Every delay mul-tiplier chain block has five outputs and they are G0, G1, G2, G3, G4, G5. The inputHm, where m=1,2,...M -1 is multiplied by the fractional-delay multiplier value re-sulting in Gk, where k=1,2...5. The G0 has the same value of Hm as shown inFig 4.9.

A 16-bit delay multiplier chain block is shown in Fig. 4.8. A 16-bit inputsample is multiplied by 8-bit fractional-delay multiplier value resulting in 24-bits(18 downto -5). The fractional-delay multipliers have very small values, so whenthe input samples are multiplied by the dm value they become comparatively verysmall. Thus we can truncate the unnecessary bits, 8-bits are truncated from 24-bitsresulting in 16-bits (15 downto 0).

Figure 4.8. A 16-bit delay multiplier chain block with truncation’s.

The first output of every delay multiplier chain block are summed to formGout(0) and every second output of the delay multiplier chain block are summedto form Gout(1) and so forth. The wordlength of the delay block increases withincrease in the decimation factor because of increase in delay multiplier chainblocks. In order to overcome this problem the output of the delay block is fixedfor 32-bits (31 downto 0). Due to these truncations a 16-bit decimator works for14-bits. The VHDL code for the delay block is given in the appendix.

4.5.2 VHDL Implementation of SubfiltersIn the interpolator, the subfilters have single input fed to every subfilter. But inthe decimator, the sum of the first output of every delay multiplier chain block isfed to the subfilter G0(z), the sum of second output of every delay multiplier chainblock is fed to G1(z) and so forth. The subfilter block in decimator is transpose


Figure 4.9. Block diagram of Decimator.

4.5 VHDL Implementation of the Decimator 37

of the subfilter block in interpolator. Hence the output of the subfilters block isthe sum of sampled outputs of every subfilter.

The delay block dkm, subfilters Gk(z) and the filter H0(z) are instantiated inbetween lines 69-75 as shown in 4.4.

Listing 4.4. VDL code for the decimator

1 −−−−−MAIN CODE−−−−−−−−−−−−−2 LIBRARY IEEE ;3 USE IEEE . STD_LOGIC_1164 . ALL ;4 USE IEEE .NUMERIC_STD. ALL ;5 USE WORK.PKG_SIGNED. ALL ;−−−−−−−−−USER DEFINED PACKAGE6 use IEEE . STD_LOGIC_unsigned . ALL ;7 USE STD . TEXTIO . ALL ;8 LIBRARY WORK;9 USE WORK. ALL ;

10 −−−−−−−−−−−−−−−−−11 −−ENTITY−−−−−−−−12 ENTITY DECIMATOR_BLOCK IS13 GENERIC(WL: INTEGER: = 1 6 ; xin_wl : i n t e g e r : = 1 6 ; COEF_WL: INTEGER: = 1 6 ;14 F : INTEGER: = 6 ; DECIMATOR_FACTOR: INTEGER:=8) ;15 PORT (16 CLK, RST : IN STD_LOGIC;17 DECIMATOR_IN: IN SIG_16 (0 TO DECIMATOR_FACTOR−1) ;18 DECIMATOR_OUT: OUT SIGNED(WL+COEF_WL−1 DOWNTO 0)19 ) ;20 END DECIMATOR_BLOCK;21 −−−−−−−−−−−−−−−−−−−−−−−−−ARCHITECTURE2223 ARCHITECTURE BEHAV OF DECIMATOR_BLOCK IS24 −−−−−−−−−−−−−−−−−−−−−−−−UBLOCK COMPONENT−−−−−−−−−−−−−25 COMPONENT UBLOCK_DECIMATOR IS26 g e n e r i c ( d e c i m a t o r _ f a c t o r : i n t e g e r ) ;27 PORT (28 CLK, RST : IN STD_LOGIC;29 DECIMATOR_IN: IN SIG_16 (1 TO DECIMATOR_FACTOR−1) ;30 GOUT : OUT SIG_16 (0 TO F−1)−−−−−change wl i s changed31 ) ;32 END COMPONENT;33 −−−−−−−−−−−−−−−−−−−−−FARROW STRUCTURE−−−−−−−−−−−−−−−−34 COMPONENT FARROW_STRUCTURE_16BIT IS35 PORT (36 CLK, RST : IN STD_LOGIC;37 GOUT_IN : IN SIG_16 (0 TO F−1) ;−−−− CHANGE WHEN WL IS CHANGED38 FOUT :OUT SIGNED(COEF_WL+WL−1 DOWNTO 0)3940 ) ;41 END COMPONENT;42 −−−−−−−−−−−−−−−−−−−−H0 FILTER−−−−−−−−−−−−−−−−−−−−−−−−43 COMPONENT H0_FILTER IS44 PORT (45 CLK, RST : IN STD_LOGIC ;46 XIN : IN SIGNED(xin_WL−1 DOWNTO 0) ;−−−−−−−INPUT PORT47 YOUT: OUT SIGNED(xin_WL+COEF_WL−1 DOWNTO 0)−−−−OUTPUT PORT48 ) ;49 END COMPONENT;5051 −−−−−−−−−−−−−−−−−SIGNALS52 SIGNAL FOUT_SIGNAL: SIGNED(WL+COEF_WL−1 DOWNTO 0) ;53 SIGNAL GOUT_SIGNAL : SIG_16 (0 TO F−1) ;54 SIGNAL FIROUT_SIGNAL : SIGNED(xin_WL+COEF_WL−1 DOWNTO 0) ;55 SIGNAL INPUT_SIGNAL : SIG_16 (1 TO DECIMATOR_FACTOR−1) ;56 s i g n a l write_out : s i g n e d ( wl+coef_wl −1 downto 0) ;57 BEGIN58 PROCESS( c l k )59 VARIABLE VAR : SIG_16 (1 TO DECIMATOR_FACTOR−1) ;60 BEGIN61 FOR I IN 1 TO DECIMATOR_FACTOR−1 LOOP62 VAR( I ) :=DECIMATOR_IN( I ) ;63 END LOOP;64 INPUT_SIGNAL<=VAR;65 DECIMATOR_OUT <= FIROUT_SIGNAL+FOUT_SIGNAL;66 write_out<=FIROUT_SIGNAL+FOUT_SIGNAL;67 END PROCESS;68 −−−−−−−−−−−− u b l o c k69 B1 :UBLOCK_DECIMATOR g e n e r i c map( d e c i m a t o r _ f a c t o r ) PORT MAP (CLK, RST,70 INPUT_SIGNAL,GOUT_SIGNAL) ;7172 −−−−−−−−−−−−− f a r r o w b l o c k73 FARROW:FARROW_STRUCTURE_16BIT PORT MAP(CLK, RST,GOUT_SIGNAL,FOUT_SIGNAL) ;74 −−−−−−−−−−−−− h0 f i l t e r75 FILTER : H0_FILTER PORT MAP(CLK, RST,DECIMATOR_IN( 0 ) ,FIROUT_SIGNAL) ;7677 f i l e _ w r i t i n g : p r o c e s s ( c l k )78 f i l e f i l e _ p o i n t e r : t e x t ;


79 v a r i a b l e l i n e _ c o n t e n t : s t r i n g (1 to 32) ;80 v a r i a b l e w r i t e _ v a l u e : Signed ( wl+coef_wl DOWNTO 1) ;81 v a r i a b l e line_num : l i n e ;82 v a r i a b l e i , j ,K : i n t e g e r : = 0 ;83 v a r i a b l e char : c h a r a c t e r : = ' 0 ' ;84 v a r i a b l e f i r s t t i m e : b o o l e a n := t r u e ;8586 b e g i n87 −−−−−−−−−−−−−−−−−−opening a f i l e and w r i t i n g to output . t x t88 i f f i r s t t i m e then89 −−Open the f i l e w r i t e . t x t from the s p e c i f i e d l o c a t i o n f o r w r i t i n g90 f i l e _ o p e n ( f i l e _ p o i n t e r , " / Decimator / o u t p u t f i l e 1 0 . t x t " ,APPEND_MODE) ;91 f i r s t t i m e := f a l s e ;92 end i f ;93 write_VALUE:=WRITE_OUT;94 k:= t o _ i n t e g e r ( write_out ) ;95 i f r i s i n g _ e d g e ( c l k ) then96 r e p o r t "<!−− i=" & i n t e g e r ' image ( i ) & " −−>" s e v e r i t y note ;97 w r i t e ( line_num ,K) ; −−w r i t e the l i n e .98 w r i t e l i n e ( f i l e _ p o i n t e r , line_num ) ;99 end i f ;

100 end p r o c e s s ;101 END BEHAV;

Chapter 5

Testbench and SimulationResults

5.1 IntroductionOnce the design is completed, it has to be tested in order to check whether itperforms as desired. The main advantage with VHDL is that a testbench can bedesigned to apply stimulus to the design that has to be tested and the testbenchis portable between VHDL tools from different vendors. VHDL is not only ahardware description language but also a stimulus definition language. A VHDLtestbench has an empty entity and an architecture with component that has to betested, internal signals for input and output, system clock process and stimulusprocess.

5.2 Design Flow for Testing InterpolatorThe design flow for testing the interpolator is shown in Fig. 5.1.

5.2.1 Generating a Sine WaveA sine wave is generated in MATLAb with

Xin = sin(n. ∗ wT );n = 0 to 2000− 1;wT = π/6.

The generated sine wave is rounded with the input wordlength, in this case theinput signal wordlength is 16-bit.

Xin_rounded = round(Xin ∗ 2(wl));

The rounded sine wave is written to a text file using

Fopen(′Input.txt′,′ w′) and Fprintf(fid,′%d/n′, Xin_rounded).

39

40 Testbench and Simulation Results

Figure 5.1. Design flow for testing interpolator.

5.2.2 VHDL TestbenchA testbench is a empty design entity which serves as a host environment for anotherdesign entity. The entity under test is called "unit under test", which has to beinstantiated in the architecture. The VHDL code for the interpolator testbench isshown below. The system clock and reset are generated in clock process and resetprocess. The input stimulus is generated using MATLAB, and the samples arewritten into a text file named "INPUT.TXT". A single sample is given for everyclock period. Simulation results are shown in Fig. 5.2. From Fig. 5.2 it is verydifficult to verify the output. Therefore, the output of the interpolator is writtento a text file as shown in lines 126-155 in the interpolator VHDL code. The outputof the interpolator (IOUT) is a 41-bit value, of which 36 are integer bits and 5fractional bits.

5.2.3 Simulation resultsA code is written in MATLAB to read the output text file generated by theinterpolator and also to convert the 41-bit binary value to a rational value. Thecode is shown in 5.1.

Listing 5.1. Code to read the output file from the interpolator

1 c l c ; c l o s e a l l ; c l e a r a l l ; format l o n g ; format compact ;2 FracPart = 5 ; DecPart = 36 ; B i t s = FracPart+DecPart+1 ;3 M = 3 ;45 f i d = f o p e n ( ' / edu / venda501 / t h e s i s / i n p u t s / input_M2.txt ' , ' r ' ) ; x i n = f s c a n f ( f i d , '%d ' ) ;6 f c l o s e ( f i d ) ; f r e q z ( x i n )78

5.2 Design Flow for Testing Interpolator 41

Figure 5.2. output of interpolator in Modelsim.


Figure 5.3. Testbench for the Interpolator.

9 rho = 0 . 0 5 ; [ n , fo , mo,w] = f i r p m o r d ([1 − rho 1+rho ] . ∗ p i /M, [ 1 0 ] , [ 1 e−5 1e −5] ,2∗ p i ) ;10 h p e r e f e c t = f i r p m ( n , fo , mo,w) ;11 x o u t p e r f e c t = conv ( upsample ( xin ,M) , h p e r e f e c t ) ;1213 f i d = f o p e n ( ' / edu / venda501 / t h e s i s / o u t p u t _ f i l e s / M_2.txt ' , ' r ' ) ;14 tmp = f s c a n f ( f i d , '%c ' ) ; f c l o s e ( f i d ) ;1516 %FracPart = 3 ; DecPart = 5 ; B i t s = FracPart+DecPart+1 ; tmp = ' 1 1 0 1 1 0 1 1 9 '17 f o r k = 0 : l e n g t h ( tmp ) / Bits −118 i f k==019 xChar ( k + 1 , : ) = tmp ( 1 : B i t s ) ;20 e l s e21 xChar ( k + 1 , : ) = tmp ( k∗ B i t s +1:( k+1)∗ B i t s ) ;22 end23 f o r m = 1 : FracPart+DecPart24 i f xChar ( k+1,m) == ' 0 '25 tmp1 ( k+1,m) = 0 ;26 e l s e i f xChar ( k+1,m) == ' 1 '27 tmp1 ( k+1,m) = 1 ;28 e l s e29 tmp1 ( k+1,m) = 1000000 ;30 end31 end32 Value = 0 ;33 f o r m = 1 : FracPart+DecPart34 i f m>DecPart35 Value = Value + 2^(−m+DecPart ) ∗tmp1 ( k+1,m) ;% [m −m+DecPart xout ( k+1,m) ]36 e l s e i f m==137 Value = Value − ( 2 ^ ( DecPart−m) ) ∗tmp1 ( k+1,m) ;% [m DecPart−m xout ( k+1,m) ]38 e l s e39 Value = Value + ( 2 ^ ( DecPart−m) ) ∗tmp1 ( k+1,m) ;% [m DecPart−m xout ( k+1,m) ]40 end41 end42 xout ( k+1) = Value ;43 %Value = [ −2^( DecPart −1) 2 . ^ [ DecPart − 2 : 0 ] ] . ∗ DecBits + [ 2 . ^[ −1: −1: FracPart ] ] . ∗

F r a c B i t s44 end45 xout = xout (20:end−10) ;46 f i g u r e47 stem ( xout ) ;4849 Ft_Sze =14;50 f i g u r e ( )51 s u b p l o t ( 2 1 1 ) ;52 wT = l i n s p a c e ( 0 , pi , 1 e3 ) ;53 p l o t (wT/ pi , db ( abs ( f r e q z ( xin , 1 ,wT) ) ) ) ;54 t i t l e ( ' Magnitude r e s p o n s e o f i n p u t s i g n a l ' , ' F o n t S i z e ' , Ft_Sze , ' FontName ' , ' t i m e s ' ) ;55 y l a b e l ( ' |H( e ^{ j {\omega}T}) | [ dB ] ' , ' F o n t S i z e ' , Ft_Sze , ' FontName ' , ' t i m e s ' ) ;56 x l a b e l ( ' Normalized Frequency ( x \ p i rad / sample ) ' , ' F o n t S i z e ' , Ft_Sze , ' FontName ' , ' t i m e s ' )

;57 s u b p l o t ( 2 1 2 ) ;5859 wT = l i n s p a c e ( 0 , pi , 1 e3 ) ;60 p l o t (wT/ pi , db ( abs ( f r e q z ( xout , 1 ,wT) ) ) , ' l i n e w i d t h ' , 2 ) ;61 t i t l e ( [ ' ( Magnitude r e s p o n s e o f i n t e r p o l a t o r ) M= ' , num2str (M) , ' ' ] , ' F o n t S i z e ' , Ft_Sze , '

FontName ' , ' t i m e s ' ) ;62 y l a b e l ( ' |H( e ^{ j {\omega}T}) | [ dB ] ' , ' F o n t S i z e ' , Ft_Sze , ' FontName ' , ' t i m e s ' ) ;63 x l a b e l ( ' Normalized Frequency ( x \ p i rad / sample ) ' , ' F o n t S i z e ' , Ft_Sze , ' FontName ' , ' t i m e s ' )

;64 f i g u r e ( )65 s u b p l o t ( 2 1 1 ) ;66 wT = l i n s p a c e ( 0 , pi , 1 e3 ) ;67 p l o t (wT/ pi , db ( abs ( f r e q z ( x o u t . ∗ b l a c k m a n h a r r i s ( l e n g t h ( xout ) ) . ' , 1 ,wT) ) ) , ' l i n e w i d t h ' , 2 ) ;68 t i t l e ( [ ' ( Magnitude r e s p o n s e o f i n t e r p o l a t o r ) M= ' , num2str (M) , ' ' ] , ' F o n t S i z e ' , Ft_Sze , '

FontName ' , ' t i m e s ' ) ;69 y l a b e l ( ' |H( e ^{ j {\omega}T}) | [ dB ] ' , ' F o n t S i z e ' , Ft_Sze , ' FontName ' , ' t i m e s ' ) ;70 x l a b e l ( ' Normalized Frequency ( x \ p i rad / sample ) ' , ' F o n t S i z e ' , Ft_Sze , ' FontName ' , ' t i m e s ' )

5.3 Testbench for the Decimator 43

;7172 s u b p l o t ( 2 1 2 ) ;73 wT = l i n s p a c e ( 0 , pi , 1 e3 ) ;74 p l o t (wT/ pi , db ( abs ( f r e q z ( x o u t . ∗ b l a c k m a n h a r r i s ( l e n g t h ( xout ) ) . ' , 1 ,wT) ) ) , ' l i n e w i d t h ' , 2 ) ;

hold on ;75 p l o t (wT/ pi , db ( abs ( f r e q z ( x o u t p e r f e c t . ∗ b l a c k m a n h a r r i s ( l e n g t h ( x o u t p e r f e c t ) ) , 1 ,wT) ) ) , ' r ' ) ;76 t i t l e ( [ ' ( Magnitude r e s p o n s e o f i n t e r p o l a t o r with p e r f e c t f i l t e r ) M= ' , num2str (M) , ' ' ] , '

F o n t S i z e ' , Ft_Sze , ' FontName ' , ' t i m e s ' ) ;77 y l a b e l ( ' |H( e ^{ j {\omega}T}) | [ dB ] ' , ' F o n t S i z e ' , Ft_Sze , ' FontName ' , ' t i m e s ' ) ;78 x l a b e l ( ' Normalized Frequency ( x \ p i rad / sample ) ' , ' F o n t S i z e ' , Ft_Sze , ' FontName ' , ' t i m e s ' )

;

Figure 5.4 shows the input signal and the interpolated signal. Observe that forevery input sample there are three output samples. The frequency response ofthe interpolator output is plotted in Fig. 5.5. The interpolator is simulated withdifferent interpolation factors (M=3,6,10), and the frequency response is shownin Figs. [5.5-5.7]. The interpolator output is not quantized, so there is no noise inthe plots.

185 190 195 200 205 210 215 220 225

−1.5

−1

−0.5

0

0.5

1

1.5

x 104 input signal

700 720 740 760 780 800 820

−2

−1

0

1

2

x 108 (interpolator output) M=3

Figure 5.4. sinusoidal signal and the interpolated sinusoidal signal (M=3).

5.3 Testbench for the DecimatorThe process for testing the decimator is the same as testing the interpolator. Anupsampled sine wave is given as an input. The output of the decimator (deci-mator out) is a 32-bit binary value, it has 32 integer bits. The output text filegenerated by the decimator has integer values, implying that conversion of bitsis not required. The frequency response of the decimator output is plotted inFigs. [5.9-5.11].


0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1

0

20

40

60

80

100

120

Magnitude response of inputsignal

|H(e

jωT)|

[dB

]

Normalized Frequency (x π rad/sample)

0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1

80

100

120

140

160

180

200

220

(Magnitude response of interpolator output) M=3

|H(e

jωT)|

[dB

]


Figure 5.5. Frequency response for the interpolator output.

0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1

50

100

150

200


|H(e

jωT)|[dB]


0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1

50

100

150

200

(Magnitude response of interpolator output followed by perfect filter) M=6

|H(e

jωT)|[dB]



5.4 Synthesis and Timing Analysis 45

0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1

60

80

100

120

140

160

180


|H(e

jωT)|[dB]


0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1

0

50

100

150

(Magnitude response of interpolator output followed by perfect filter) M=10

|H(e

jωT)|[dB]



LEs LABs Fmax (MHz) System clock16-bit Interpolator 17230 1283 13.95 1000 MHz16-bit Decimator 15099 1099 59.99 1000 MHz

Table 5.1. Table for resource utilization and performance.

5.4 Synthesis and Timing AnalysisThe report below shows the total use of the logical elements and logical registersby Interpolator. This synthesis is done by selecting the Cyclone IV GX familyand EP4CGX30CF23C6 device. Table 5.1 shows the number of logical elementsand logical array blocks used for the interpolator and decimator. The interpo-lation factor is 10 and the decimation factor is 4. Due to the difference in thefactors there is a difference in the LEs, LABs, and Fmax. The coefficients ofthe interpolation/decimation filters are stored in the regiters. The output of in-terpolator/decimators are 32-bits, for the 16-bit interpolator/decimator. In thisimplementation the 16-bit interpolator output wordlength is 40 bits in which 8bits are truncated. The performance of the interpolator can be increased by usingadvanced multiplication techniques.

5.4.1 Synthesis and Time Quest Analyzer Reports


Figure 5.8. Output of the decimator in Modelsim.


0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1−50

0

50

100

150


|H(e

jωT)|[dB]


0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 150

100

150

200

250

(Magnitude response of decimator output) M=2

|H(e

jωT)|[dB]


Figure 5.9. Frequency response for the decimator output.

0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1−50

0

50

100

150


|H(e

jωT)|[dB]


0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 150

100

150

200


|H(e

jωT)|[dB]




0 100 200 300 400 500 600 700 800 900 100050

60

70

80

90

100

110

120


|H(e

jωT)|[dB]


0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 150

100

150

200


|H(e

jωT)|[dB]



1 Resource Usage Summary r e p o r t f o r DELAY_BLOCK_RW_16BIT2 Tue Nov 6 1 4 : 2 2 : 4 0 20123 Quartus I I V e r s i o n 10 . 1 Bu il d 197 01/19/2011 S e r v i c e Pack 1 SJ F u l l V e r s i o n456 −−−−−−−−−−−−−−−−−−−−−7 ; Table o f Contents ;8 −−−−−−−−−−−−−−−−−−−−−9 1 . L e g a l N o t i c e

10 2 . F i t t e r Resource Usage Summary11121314 −−−−−−−−−−−−−−−−15 ; L e g a l N o t i c e ;16 −−−−−−−−−−−−−−−−17 Copyright (C) 1991 −2011 A l t e r a C o r p o r a t i o n18 Your use o f A l t e r a Corporation ' s d e s i g n t o o l s , l o g i c f u n c t i o n s19 and o t h e r s o f t w a r e and t o o l s , and i t s AMPP p a r t n e r l o g i c20 f u n c t i o n s , and any output f i l e s from any o f the f o r e g o i n g21 ( i n c l u d i n g d e v i c e programming or s i m u l a t i o n f i l e s ) , and any22 a s s o c i a t e d documentation or i n f o r m a t i o n a r e e x p r e s s l y s u b j e c t23 to the terms and c o n d i t i o n s o f the A l t e r a Program L i c e n s e24 S u b s c r i p t i o n Agreement , A l t e r a MegaCore Function L i c e n s e25 Agreement , or o t h e r a p p l i c a b l e l i c e n s e agreement , i n c l u d i n g ,26 without l i m i t a t i o n , t h a t your use i s f o r the s o l e purpose o f27 programming l o g i c d e v i c e s manufactured by A l t e r a and s o l d by28 A l t e r a or i t s a u t h o r i z e d d i s t r i b u t o r s . P l e a s e r e f e r to the29 a p p l i c a b l e agreement f o r f u r t h e r d e t a i l s .30313233 +−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−+34 ; F i t t e r Resource Usage Summary ;35 +−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−+−−−−−−−−−−−−−−−−−−−−−−−−−−+36 ; Resource ; Usage ;37 +−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−+−−−−−−−−−−−−−−−−−−−−−−−−−−+38 ; Total l o g i c e l e m e n t s ; 17 ,230 / 29 ,440 ( 59 % ) ;39 ; −− Combinational with no r e g i s t e r ; 16526 ;40 ; −− R e g i s t e r o n l y ; 48 ;41 ; −− Combinational with a r e g i s t e r ; 656 ;42 ; ; ;43 ; L o g i c element usage by number o f LUT i n p u t s ; ;44 ; −− 4 i n p u t f u n c t i o n s ; 3395 ;45 ; −− 3 i n p u t f u n c t i o n s ; 11228 ;46 ; −− <=2 i n p u t f u n c t i o n s ; 2559 ;47 ; −− R e g i s t e r o n l y ; 48 ;48 ; ; ;49 ; L o g i c e l e m e n t s by mode ; ;50 ; −− normal mode ; 6228 ;51 ; −− a r i t h m e t i c mode ; 10954 ;


52 ; ; ;53 ; Total r e g i s t e r s ∗ ; 704 / 30 ,876 ( 2 % ) ;54 ; −− Dedicated l o g i c r e g i s t e r s ; 704 / 29 ,440 ( 2 % ) ;55 ; −− I /O r e g i s t e r s ; 0 / 1 ,436 ( 0 % ) ;56 ; ; ;57 ; Total LABs : p a r t i a l l y or c o m p l e t e l y used ; 1 ,283 / 1 ,840 ( 70 % ) ;58 ; User i n s e r t e d l o g i c e l e m e n t s ; 0 ;59 ; V i r t u a l p i n s ; 0 ;60 ; I /O p i n s ; 210 / 307 ( 68 % ) ;61 ; −− Clock p i n s ; 1 / 8 ( 13 % ) ;62 ; −− Dedicated i n p u t p i n s ; 0 / 17 ( 0 % ) ;63 ; Global s i g n a l s ; 2 ;64 ; M9Ks ; 0 / 120 ( 0 % ) ;65 ; Total b l o c k memory b i t s ; 0 / 1 , 1 0 5 , 9 2 0 ( 0 % ) ;66 ; Total b l o c k memory im p l e m e n t a t i o n b i t s ; 0 / 1 , 1 0 5 , 9 2 0 ( 0 % ) ;67 ; Embedded M u l t i p l i e r 9− b i t e l e m e n t s ; 20 / 160 ( 13 % ) ;68 ; PLLs ; 0 / 6 ( 0 % ) ;69 ; Global c l o c k s ; 2 / 30 ( 7 % ) ;70 ; JTAGs ; 0 / 1 ( 0 % ) ;71 ; CRC b l o c k s ; 0 / 1 ( 0 % ) ;72 ; ASMI b l o c k s ; 0 / 1 ( 0 % ) ;73 ; GXB R e c e i v e r c h a n n e l PCSs ; 0 / 4 ( 0 % ) ;74 ; GXB R e c e i v e r c h a n n e l PMAs ; 0 / 4 ( 0 % ) ;75 ; GXB T r a n s m i t t e r c h a n n e l PCSs ; 0 / 4 ( 0 % ) ;76 ; GXB T r a n s m i t t e r c h a n n e l PMAs ; 0 / 4 ( 0 % ) ;77 ; Impedance c o n t r o l b l o c k s ; 0 / 3 ( 0 % ) ;78 ; Average i n t e r c o n n e c t usage ( t o t a l /H/V) ; 11% / 10% / 13% ;79 ; Peak i n t e r c o n n e c t usage ( t o t a l /H/V) ; 49% / 46% / 54% ;80 ; Maximum fan−out node ; CLK~ i n p u t c l k c t r l ;81 ; Maximum fan−out ; 706 ;82 ; H i g h e s t non−g l o b a l fan−out s i g n a l ; RST~ i n p u t ;83 ; H i g h e s t non−g l o b a l fan−out ; 226 ;84 ; Total fan−out ; 54972 ;85 ; Average fan−out ; 2 . 9 9 ;86 +−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−+−−−−−−−−−−−−−−−−−−−−−−−−−−+87 ∗ R e g i s t e r count does not i n c l u d e r e g i s t e r s i n s i d e RAM b l o c k s or DSP b l o c k s .

From the time quest timing analysis report of the interpolator the Fmax=12.44MHz for the slow 1200 mv 85c model and Fmax=13.95 MHz for the slow 1200mv 0c model. For the decimator the Fmax=53.39 MHz for the slow 1200 mv 85cmodel and Fmax=59.99 MHz for the slow 1200 mv 0c model.

1 Resource Usage Summary r e p o r t f o r Decimator_block2 Tue Nov 13 1 7 : 1 6 : 5 6 20123 Quartus I I V e r s i o n 10 . 1 Bu il d 197 01/19/2011 S e r v i c e Pack 1 SJ F u l l V e r s i o n456 −−−−−−−−−−−−−−−−−−−−−7 ; Table o f Contents ;8 −−−−−−−−−−−−−−−−−−−−−9 1 . L e g a l N o t i c e

10 2 . F i t t e r Resource Usage Summary11121314 −−−−−−−−−−−−−−−−15 ; L e g a l N o t i c e ;16 −−−−−−−−−−−−−−−−17 Copyright (C) 1991 −2011 A l t e r a C o r p o r a t i o n18 Your use o f A l t e r a Corporation ' s d e s i g n t o o l s , l o g i c f u n c t i o n s19 and o t h e r s o f t w a r e and t o o l s , and i t s AMPP p a r t n e r l o g i c20 f u n c t i o n s , and any output f i l e s from any o f the f o r e g o i n g21 ( i n c l u d i n g d e v i c e programming or s i m u l a t i o n f i l e s ) , and any22 a s s o c i a t e d documentation or i n f o r m a t i o n a r e e x p r e s s l y s u b j e c t23 to the terms and c o n d i t i o n s o f the A l t e r a Program L i c e n s e24 S u b s c r i p t i o n Agreement , A l t e r a MegaCore Function L i c e n s e25 Agreement , or o t h e r a p p l i c a b l e l i c e n s e agreement , i n c l u d i n g ,26 without l i m i t a t i o n , t h a t your use i s f o r the s o l e purpose o f27 programming l o g i c d e v i c e s manufactured by A l t e r a and s o l d by28 A l t e r a or i t s a u t h o r i z e d d i s t r i b u t o r s . P l e a s e r e f e r to the29 a p p l i c a b l e agreement f o r f u r t h e r d e t a i l s .30313233 +−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−+34 ; F i t t e r Resource Usage Summary ;35 +−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−+−−−−−−−−−−−−−−−−−−−−−−−−−−+36 ; Resource ; Usage ;37 +−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−+−−−−−−−−−−−−−−−−−−−−−−−−−−+38 ; Total l o g i c e l e m e n t s ; 15 ,099 / 29 ,440 ( 51 % ) ;39 ; −− Combinational with no r e g i s t e r ; 12731 ;40 ; −− R e g i s t e r o n l y ; 112 ;41 ; −− Combinational with a r e g i s t e r ; 2256 ;42 ; ; ;43 ; L o g i c element usage by number o f LUT i n p u t s ; ;


44 ; −− 4 i n p u t f u n c t i o n s ; 3901 ;45 ; −− 3 i n p u t f u n c t i o n s ; 9249 ;46 ; −− <=2 i n p u t f u n c t i o n s ; 1837 ;47 ; −− R e g i s t e r o n l y ; 112 ;48 ; ; ;49 ; L o g i c e l e m e n t s by mode ; ;50 ; −− normal mode ; 5811 ;51 ; −− a r i t h m e t i c mode ; 9176 ;52 ; ; ;53 ; Total r e g i s t e r s ∗ ; 2 ,368 / 30 ,191 ( 8 % ) ;54 ; −− Dedicated l o g i c r e g i s t e r s ; 2 ,368 / 29 ,440 ( 8 % ) ;55 ; −− I /O r e g i s t e r s ; 0 / 751 ( 0 % ) ;56 ; ; ;57 ; Total LABs : p a r t i a l l y or c o m p l e t e l y used ; 1 ,099 / 1 ,840 ( 60 % ) ;58 ; User i n s e r t e d l o g i c e l e m e n t s ; 0 ;59 ; V i r t u a l p i n s ; 0 ;60 ; I /O p i n s ; 98 / 167 ( 59 % ) ;61 ; −− Clock p i n s ; 4 / 6 ( 67 % ) ;62 ; −− Dedicated i n p u t p i n s ; 0 / 16 ( 0 % ) ;63 ; Global s i g n a l s ; 2 ;64 ; M9Ks ; 0 / 120 ( 0 % ) ;65 ; Total b l o c k memory b i t s ; 0 / 1 , 1 0 5 , 9 2 0 ( 0 % ) ;66 ; Total b l o c k memory im p l e m e n t a t i o n b i t s ; 0 / 1 , 1 0 5 , 9 2 0 ( 0 % ) ;67 ; Embedded M u l t i p l i e r 9− b i t e l e m e n t s ; 0 / 160 ( 0 % ) ;68 ; PLLs ; 0 / 4 ( 0 % ) ;69 ; Global c l o c k s ; 2 / 20 ( 10 % ) ;70 ; JTAGs ; 0 / 1 ( 0 % ) ;71 ; CRC b l o c k s ; 0 / 1 ( 0 % ) ;72 ; ASMI b l o c k s ; 0 / 1 ( 0 % ) ;73 ; GXB R e c e i v e r c h a n n e l PCSs ; 0 / 4 ( 0 % ) ;74 ; GXB R e c e i v e r c h a n n e l PMAs ; 0 / 4 ( 0 % ) ;75 ; GXB T r a n s m i t t e r c h a n n e l PCSs ; 0 / 4 ( 0 % ) ;76 ; GXB T r a n s m i t t e r c h a n n e l PMAs ; 0 / 4 ( 0 % ) ;77 ; Impedance c o n t r o l b l o c k s ; 0 / 3 ( 0 % ) ;78 ; Average i n t e r c o n n e c t usage ( t o t a l /H/V) ; 18% / 16% / 21% ;79 ; Peak i n t e r c o n n e c t usage ( t o t a l /H/V) ; 31% / 26% / 39% ;80 ; Maximum fan−out node ; CLK~ i n p u t c l k c t r l ;81 ; Maximum fan−out ; 2368 ;82 ; H i g h e s t non−g l o b a l fan−out s i g n a l ; RST~ i n p u t ;83 ; H i g h e s t non−g l o b a l fan−out ; 320 ;84 ; Total fan−out ; 54115 ;85 ; Average fan−out ; 3 . 0 7 ;86 +−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−+−−−−−−−−−−−−−−−−−−−−−−−−−−+87 ∗ R e g i s t e r count does not i n c l u d e r e g i s t e r s i n s i d e RAM b l o c k s or DSP b l o c k s .

Chapter 6

Conclusion and Future Work

6.1 ConclusionIn this thesis work, the interpolators and decimators work efficiently up to a con-version factor of 20. For larger factors new subfilters have to be designed. Thisdesign gives the flexibility to implement the different wordlength interpolators anddecimators. This implementation proves that the design proposed in [8] works wellfor conversions by prime numbers and is flexible for the conversion factors. Thefixed point package made the design more flexible and easier. By instantiating thedelay block, several sampling rate converters can be implemented simultaneously,with the same set of filters. The only additional cost to obtain another converteris to add another delay block. Hence, several sampling rate converters can beimplemented simultaneously at low cost. The interpolator and decimator cannotbe implemented on the FPGA board, because the FPGA board cannot read orwrite the text files given in the code. The program Teraterm or Hyperterminalcan be used to transfer a text file with large amount of binary data.

6.2 Future Work• One can implement the design without using the fixed point package and

verify the performance and registers usage.

• More advanced techniques can be used for truncation of bits.

• To implement the design on the FPGA board one can use the teratermprogram. By using this program the entire text file can be transferred to theFPGA board via a PC serial port.

• Another way to implement the design on the FPGA board is by using theSDRAM. The input sequence is saved in the SDRAM and the output ofthe interpolator or decimator has to be pointed to the remaining memoryaddress in the SDRAM. The SDRAM on FPGA board is small, so we cannotgive many input samples.

51

Appendix A

Appendix

A.1 VHDL Code

A.1.1 VHDL Code for Subfilter

12 −−−−−−− FIR FILTER−−−−−−−−−3 −− This FIR f i l t e r i n s t a n c e s a r e used i n the Farrow s t r u c t u r e4 −−−−−MAIN CODE−−−−−−−−−−−−−5 LIBRARY IEEE ;6 USE IEEE . STD_LOGIC_1164 . ALL ;7 USE IEEE .NUMERIC_STD. ALL ;8 use IEEE . STD_LOGIC_unsigned . ALL ;9 USE WORK.PKG_SIGNED. ALL ;−−−−−−−−−USER DEFINED PACKAGE

10 LIBRARY WORK;11 USE WORK. ALL ;12 −−−−−−−−−−−−−−−−−13 −−ENTITY−−−−−−−−14 ENTITY FIR_FILTER_16BIT IS15 GENERIC (ORDER : INTEGER: = 1 7 ;WL: INTEGER: = 1 6 ;COEF_WL: INTEGER:=16) ;16 −−−−−−−WL IS WORDLENGTH OF XIN(INPUT SIGNAL)17 −−−−−−−COEF_WL IS WORDLENGTH OF COEFFICIENTS OR TAPS18 PORT (19 CLK, RST : IN STD_LOGIC ;20 XIN : IN SIGNED(WL−1 DOWNTO 0) ;21 −−−−THE PORT TYPE HAS TO BE CHANGED IF COEF_WL CHANGES22 COEF: IN SIG_16 (0 TO ORDER) ;23 YOUT: OUT SIGNED(COEF_WL+WL−1 DOWNTO 0)24 ) ;25 END FIR_FILTER_16BIT ;2627 −−−−−−−−−−−−−−−−−−28 −−−ARCHITECTURE−−−2930 ARCHITECTURE BEHAVIOURAL OF FIR_FILTER_16BIT IS31 TYPE SIG_ARR IS ARRAY (ORDER−1 DOWNTO 0) OF SIGNED(WL−1 DOWNTO 0) ;32 −−−−−−−−−SIGNALS−−−−−−−−−−−−−−−−−−−−−−33 SIGNAL DFF: SIG_ARR ;34 BEGIN3536 INTAL :PROCESS(CLK, RST)37 VARIABLE M_OUT,ADD_OUT: SIGNED(COEF_WL+WL−1 DOWNTO 0) :=(OTHERS= > '0 ') ;38 BEGIN39 IF (RST= '1 ') THEN40 FOR I IN ORDER−1 DOWNTO 0 LOOP41 f o r j i n WL−1 downto 0 l o o p42 DFF( I ) ( j ) <= '0 ';43 end l o o p ;44 END LOOP;45 −−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−46 ELSIF ( r i s i n g _ e d g e ( c l k ) ) then47 ADD_OUT:= COEF( 0 ) ∗XIN ;48 FOR I IN 1 TO ORDER−1 LOOP49 M_OUT:=COEF( I ) ∗DFF(ORDER−1−I ) ;50 ADD_OUT:=ADD_OUT+M_OUT;51 END LOOP;

53

54 Appendix

52 DFF<= XIN & DFF(ORDER−1 DOWNTO 1) ;53 end i f ;54 YOUT<=ADD_OUT;55 END PROCESS;56 END BEHAVIOURAL;

A.1.2 VHDL Code for Delay Block of Decimator

1 −−−−−−−−−− Delay Block o f Decimator −−−−−−−−−−−−−−−−−2 −−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−3 −−−−−−−−−−−−−−−−−−−−−− MAIN CODE −−−−−−−−−−−−−−−−−−−−4 LIBRARY IEEE ;5 USE IEEE . STD_LOGIC_1164 . ALL ;6 USE IEEE .NUMERIC_STD. ALL ;7 USE IEEE . STD_LOGIC_unsigned . ALL ;8 l i b r a r y i e e e _ p r o p o s e d ;9 use i e e e _ p r o p o s e d . fixed_pkg . a l l ;−−−−−−−f i x e d p o i n t packages

10 USE WORK.PKG_SIGNED. ALL ;−−−−−−−−−USER DEFINED PACKAGE11 use s t d . t e x t i o . a l l ;12 LIBRARY WORK;13 USE WORK. ALL ;14 −−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−15 −−−−−−−−−−−−−−−−−−−−−−− ENTITY −−−−−−−−−−−−−−−−−−−−−−16 −−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−17 ENTITY UBLOCK_DECIMATOR IS18 GENERIC(XIN_WL: INTEGER: = 1 6 ;F : INTEGER: = 6 ;19 DECIMATOR_FACTOR: INTEGER: = 6 ;Dm_WL: INTEGER:=8) ;20 PORT (21 CLK, RST : IN STD_LOGIC;22 DECIMATOR_IN: IN SIG_16 (1 TO DECIMATOR_FACTOR−1) ;23 GOUT : OUT SIG_16 (0 TO F−1)−−−−−−−−−−−−−change wl i s changed24 ) ;25 END UBLOCK_DECIMATOR;2627 ARCHITECTURE BEHAV OF UBLOCK_DECIMATOR IS28 −−−−−−−−−−−−−−−−−−−−−ARRAYS−−−−−−−−−−−−−−−−−−−−−−−−−−29 TYPE Dm_VAR_ARRAY IS ARRAY(0 TO DECIMATOR_FACTOR−1)30 OF SFIXED(1 DOWNTO −Dm_WL+2) ;−−(0 TO −7)31 TYPE Dm_TEMP_ARRAY IS ARRAY(1 TO DECIMATOR_FACTOR−1)32 OF SFIXED(2 DOWNTO −Dm_WL+2) ;−−(1 TO −7)33 TYPE G_VAR_ARRAY IS ARRAY (0 TO F−1)34 OF SFIXED(XIN_WL−1 DOWNTO 0) ;−−(15 DOWNTO 0)35 TYPE G_TEMP_ARRAY IS ARRAY(1 TO F−1)36 OF SFIXED(XIN_WL DOWNTO −Dm_WL+1) ;37 −−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−38 BEGIN39 PROCESS(CLK, RST)40 VARIABLE Dm_VAR:Dm_VAR_ARRAY;−−(0 TO −7)41 VARIABLE Dm_TEMP:Dm_TEMP_ARRAY;−−(1 TO −7)42 VARIABLE G_VAR:G_VAR_ARRAY;−−(15 DOWNTO 0)43 VARIABLE G_TEMP:G_TEMP_ARRAY;−−−−−WL=16(16 DOWNTO −7)44 VARIABLE GOUT_VAR: SIG_16 (0 TO F−1) ;−−−change when wl i changed45 VARIABLE TEMP1: SFIXED(1 DOWNTO −Dm_WL+2) ;46 VARIABLE TEMP2: SIGNED(XIN_WL−1 DOWNTO 0) ;47 v a r i a b l e once : s f i x e d (XIN_WL−1 downto 0) ;48 v a r i a b l e d : s f i x e d ( XIN_wl−1 downto 0) ;49 v a r i a b l e v a l u e : s f i x e d ( XIN_wl downto −XIN_wl+1) ;50 BEGIN51 IF (RST= '1 ') THEN52 FOR I IN 0 TO F−1 LOOP53 FOR J IN 0 TO 15 LOOP54 GOUT_VAR( I ) ( J ) : = ' 0 ' ;55 END LOOP;56 END LOOP;57 ELSif ( r i s i n g _ e d g e ( c l k ) ) then58 once := t o _ s f i x e d ( 1 , once ) ;59 d:= t o _ s f i x e d ( d e c i m a t o r _ f a c t o r , d ) ;60 v a l u e := once /d ;61 temp1:= r e s i z e (−value , temp1 ) ;62 −−−−−−−−−−−−−63 Dm_VAR( 0 ) :=TO_SFIXED( 0 . 5 ,Dm_VAR( 0 ) ) ;6465 FOR I IN 1 TO DECIMATOR_FACTOR−1 LOOP66 Dm_TEMP( I ) :=TEMP1+Dm_VAR( I −1) ;−−−−(1 DOWNTO −7)67 Dm_VAR( I ) :=RESIZE (Dm_TEMP( I ) ,Dm_VAR( I ) ) ;−−(0 DOWNTO −7)68 −−−−−CONVERTING SIGNED(WL−1 DOWNTO 0) TO SFIXED(15 DOWNTO 0)69 G_VAR( 0 ) :=TO_SFIXED(DECIMATOR_IN( I ) ,G_VAR( 0 ) ) ;70 FOR J IN 1 TO F−1 LOOP71 G_TEMP( J ) :=Dm_VAR( I ) ∗G_VAR( J−1) ;−−(16 DOWNTO −7)72 G_VAR( J ) :=RESIZE (G_TEMP( J ) ,G_VAR( 0 ) ) ;−−(15 DOWNTO 0)73 END LOOP;74 FOR J IN 0 TO F−1 LOOP75 TEMP2:=TO_SIGNED(G_VAR( J ) ,XIN_WL) ;76 GOUT_VAR( J ) :=TEMP2+GOUT_VAR( J ) ;

A.1 VHDL Code 55

77 END LOOP;78 END LOOP;79 GOUT<=GOUT_VAR;80 END IF ;81 END PROCESS;82 END BEHAV;

A.1.3 VHDL Code for Farrow Structure of Decimator

1 −−− Farrow s t r u c t u r e f o r Decimator −−−−−−−−−−−−2 −−−−−MAIN CODE−−−−−−−−−−−−−3 LIBRARY IEEE ;4 USE IEEE . STD_LOGIC_1164 . ALL ;5 USE IEEE .NUMERIC_STD. ALL ;6 USE WORK.PKG_SIGNED. ALL ;−−−−−−−−−USER DEFINED PACKAGE7 use IEEE . STD_LOGIC_unsigned . ALL ;8 USE STD . TEXTIO . ALL ;9 LIBRARY WORK;

10 USE WORK. ALL ;11 −−−−−−−−−−−−−−−−−12 −−ENTITY−−−−−−−−1314 ENTITY ublk_FARROW_STRUCTURE IS15 GENERIC(F : INTEGER: = 6 ;WL: INTEGER: = 1 6 ;COEF_WL: INTEGER: = 1 6 ;ORDER: INTEGER: = 1 7 ;16 DECIMATOR_FACTOR: INTEGER: = 6 ; XIN_WL: INTEGER:=16) ;17 PORT(18 CLK, RST : IN STD_LOGIC;19 DECIMATOR_IN: IN SIG_16 (1 TO DECIMATOR_FACTOR−1) ;20 GOUT_IN :OUT SIG_16 (0 TO F−1) ;−−−− CHANGE WHEN WL IS CHANGED21 FOUT :OUT SIGNED(COEF_WL+WL−1 DOWNTO 0)2223 ) ;24 END ublk_FARROW_STRUCTURE;2526 −−−−−−−−−−−−−−− ARCHITECTURE2728 ARCHITECTURE BEHAV OF ublk_FARROW_STRUCTURE IS2930 −−−−−−−−−−−−−−−−−− COMPONENT DECLARATION31 −−−−−−−−−−−−−−− H0_FILTER −−−−−−−−−−−−−−−−−−−−−−−−−−32 COMPONENT H0_FILTER IS33 PORT34 (35 CLK, RST : IN STD_LOGIC ;36 XIN : IN SIGNED(XIN_WL−1 DOWNTO 0) ;−−−−−−−INPUT PORT37 YOUT: OUT SIGNED ( (XIN_WL+COEF_WL−1) DOWNTO 0)−−−−OUTPUT PORT38 ) ;39 END COMPONENT;4041 −−−−−−−−−−−−−−− UBLOCK −−−−−−−−−−−−−−−−−−−−−−−−−−−−−−42 COMPONENT UBLOCK_DECIMATOR IS43 PORT44 (45 CLK, RST : IN STD_LOGIC;46 DECIMATOR_IN: IN SIG_16 (1 TO DECIMATOR_FACTOR−1) ;47 GOUT : OUT SIG_16 (0 TO F−1)−−change wl i s changed48 ) ;49 END COMPONENT;5051 −−−−−−−−−−−−−−−−−−−−− FIR_FILTER −−−−−−−−−−−−−−−−−−−−52 COMPONENT FIR_FILTER IS53 GENERIC (WL: INTEGER) ;54 PORT(55 CLK, RST : IN STD_LOGIC ;56 XIN : IN SIGNED(WL−1 DOWNTO 0) ;57 −−−PORT TYPE HAS TO BE CHANGED IF COEF_WL CHANGES58 COEF: IN SIG_16 (0 TO ORDER) ;59 YOUT: OUT SIGNED(COEF_WL+WL−1 DOWNTO 0)60 ) ;61 END COMPONENT;62 −−−−−−−−−−−−ARRAY DECLARATION63 −−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−64 type c o e f f i c i e n t s i s a r r a y (0 to o r d e r ) o f i n t e g e r ;65 TYPE FIR_OUT_ARRAY IS ARRAY (0 TO F−1) OF SIGNED(COEF_WL+WL−1 DOWNTO 0) ;66 c o n s t a n t coef_1 : c o e f f i c i e n t s :=(33 , −69 ,164 , −323 ,582 , −989 ,1699 , −3230 ,10348 ,67 10348 , −3230 ,1699 , −989 ,582 , −323 ,164 , −69 ,33) ;68 c o n s t a n t coef_2 : c o e f f i c i e n t s :=( −254 ,462 , −711 ,1058 , −1510 ,1978 , −2706 ,4361 ,69 −23066 ,23066 , −4361 ,2706 , −1978 ,1510 , −1058 ,711 , −462 ,254) ;70 c o n s t a n t coef_3 : c o e f f i c i e n t s :=( −101 ,110 , −636 ,1410 , −2635 ,4605 , −7911 ,14322 ,71 −9288 , −9288 ,14322 , −7911 ,4605 , −2635 ,1410 , −636 ,110 , −101) ;72 c o n s t a n t coef_4 : c o e f f i c i e n t s :=(62 , −973 ,1276 , −1983 ,3213 , −4208 ,6917 , −13282 ,73 23043 , −23043 ,13282 , −6917 ,4208 , −3213 ,1983 , −1276 ,973 , −62) ;74 c o n s t a n t coef_5 : c o e f f i c i e n t s :=( −388 , −259 ,801 , −1357 ,2033 , −3390 ,5255 , −6306 ,75 3064 ,3064 , −6306 ,5255 , −3390 ,2033 , −1357 ,801 , −259 , −388) ;

56 Appendix

76 c o n s t a n t coef_6 : c o e f f i c i e n t s :=(44 , −139 , −43 ,99 , −157 ,347 , −1143 ,3033 , −4898 ,4898 ,77 −3033 ,1143 , −347 ,157 , −99 ,43 ,139 , −44) ;78 −−−−−−−−−−−−−−SIGNALS DECLERATION79 SIGNAL GOUT_SIGNAL: SIG_16 (0 TO F−1) ;80 SIGNAL FIR_OUT: sig_32 (1 to f ) ; −−−−−−−−−−CHANGE COEF_WL CHANGES81 −−SIGNAL H0_OUT: SIGNED(XIN_WL+COEF_WL−1 DOWNTO 0) ;82 SIGNAL INPUT_SIGNAL : SIG_16 (1 TO DECIMATOR_FACTOR−1) ;83 SIGNAL COEF_SIGNAL_1 : SIG_16 (0 TO ORDER) ;−−CHANGE COEF_WL CHANGES84 SIGNAL COEF_SIGNAL_2 : SIG_16 (0 TO ORDER) ;−−CHANGE COEF_WL CHANGES85 SIGNAL COEF_SIGNAL_3 : SIG_16 (0 TO ORDER) ;−−CHANGE COEF_WL CHANGES86 SIGNAL COEF_SIGNAL_4 : SIG_16 (0 TO ORDER) ;−−CHANGE COEF_WL CHANGES87 SIGNAL COEF_SIGNAL_5 : SIG_16 (0 TO ORDER) ;−−CHANGE COEF_WL CHANGES88 SIGNAL COEF_SIGNAL_6 : SIG_16 (0 TO ORDER) ;−−CHANGE COEF_WL CHANGES89 −−SIGNAL TEST : ;90 BEGIN9192 PROCESS( c l k )9394 VARIABLE COEF_VAR_1: SIG_16 (0 TO ORDER) ;−−CHANGE COEF_WL CHANGES95 VARIABLE COEF_VAR_2: SIG_16 (0 TO ORDER) ;−−CHANGE COEF_WL CHANGES96 VARIABLE COEF_VAR_3: SIG_16 (0 TO ORDER) ;−−CHANGE COEF_WL CHANGES97 VARIABLE COEF_VAR_4: SIG_16 (0 TO ORDER) ;−−CHANGE COEF_WL CHANGES98 VARIABLE COEF_VAR_5: SIG_16 (0 TO ORDER) ;−−CHANGE COEF_WL CHANGES99 VARIABLE COEF_VAR_6: SIG_16 (0 TO ORDER) ;−−CHANGE COEF_WL CHANGES

100 −−VARIABLE INPUT_VAR: SIG_16 (1 TO DECIMATOR_FACTOR−1) ;101102 b e g i n103 i f r s t = '1 ' then104 f o r i i n 0 to o r d e r l o o p105 COEF_VAR_1( I ) :=TO_SIGNED(COEF_1( I ) ,COEF_WL) ;106 COEF_VAR_2( I ) :=TO_SIGNED(COEF_2( I ) ,COEF_WL) ;107 COEF_VAR_3( I ) :=TO_SIGNED(COEF_3( I ) ,COEF_WL) ;108 COEF_VAR_4( I ) :=TO_SIGNED(COEF_4( I ) ,COEF_WL) ;109 COEF_VAR_5( I ) :=TO_SIGNED(COEF_5( I ) ,COEF_WL) ;110 COEF_VAR_6( I ) :=TO_SIGNED(COEF_6( I ) ,COEF_WL) ;111 END LOOP;112 COEF_SIGNAL_1<=COEF_VAR_1;113 COEF_SIGNAL_2<=COEF_VAR_2;114 COEF_SIGNAL_3<=COEF_VAR_3;115 COEF_SIGNAL_4<=COEF_VAR_4;116 COEF_SIGNAL_5<=COEF_VAR_5;117 COEF_SIGNAL_6<=COEF_VAR_6;118 end i f ;119120 END PROCESS;121 p r o c e s s 2 : p r o c e s s ( c l k )122 VARIABLE INPUT_VAR: SIG_16 (1 TO DECIMATOR_FACTOR−1) ;123 b e g i n124 i f r i s i n g _ e d g e ( c l k ) then125 f o r i i n 1 to d e c i m a t o r _ f a c t o r −1 l o o p126 input_var ( i ) := decimator_in ( i ) ;127 end l o o p ;128 i n p u t _ s i g n a l <=input_var ;129 end i f ;130 end p r o c e s s ;131132133 −−−−−−−−−−−−−−COMPONENT DELECERATION134 −−−−−−−−−−−−−−−−−−−−H0_FILTER−−−−−−−−−−−−135136 −−H0FILTER : H0_FILTER PORT MAP(CLK, RST,DECIMATOR_IN( 0 ) ,H0_OUT) ;137 −−−−−−−−−−−−DELAY BLOCK−−−−−−−−−−−−−−−−−−138 UBLOCK:UBLOCK_DECIMATOR PORT MAP(CLK, RST, i n p u t _ s i g n a l ,GOUT_SIGNAL) ;139 GOUT_IN<=GOUT_SIGNAL;140 −−−−−−−−−−−−FIR−FILTER−−−−−−−−−−−−−−−−−−141 FIR1 : FIR_FILTER GENERIC MAP(WL) PORT MAP(CLK, RST,GOUT_SIGNAL( 5 ) ,142 COEF_SIGNAL_6,FIR_OUT( 1 ) ) ;143 FIR2 : FIR_FILTER GENERIC MAP(WL) PORT MAP(CLK, RST,GOUT_SIGNAL( 4 ) ,144 COEF_SIGNAL_5,FIR_OUT( 2 ) ) ;145 FIR3 : FIR_FILTER GENERIC MAP(WL) PORT MAP(CLK, RST,GOUT_SIGNAL( 3 ) ,146 COEF_SIGNAL_4,FIR_OUT( 3 ) ) ;147 FIR4 : FIR_FILTER GENERIC MAP(WL) PORT MAP(CLK, RST,GOUT_SIGNAL( 2 ) ,148 COEF_SIGNAL_3,FIR_OUT( 4 ) ) ;149 FIR5 : FIR_FILTER GENERIC MAP(WL) PORT MAP(CLK, RST,GOUT_SIGNAL( 1 ) ,150 COEF_SIGNAL_2,FIR_OUT( 5 ) ) ;151 FIR6 : FIR_FILTER GENERIC MAP(WL) PORT MAP(CLK, RST,GOUT_SIGNAL( 0 ) ,152 COEF_SIGNAL_1,FIR_OUT( 6 ) ) ;153154 FOUT<=FIR_OUT( 1 )+FIR_OUT( 2 )+FIR_OUT( 3 )+FIR_OUT( 4 )+FIR_OUT( 5 )+FIR_OUT( 6 ) ;155156 END BEHAV;

A.1.4 User Package

A.1 VHDL Code 57

1 −−−−−−−−−PACKAGE:−−−−−−−−−−−2 LIBRARY IEEE ;3 LIBRARY IEEE_PROPOSED;4 USE IEEE . STD_LOGIC_1164 . ALL ;5 USE IEEE .NUMERIC_STD. ALL ;6 use IEEE . STD_LOGIC_unsigned . ALL ;7 use i e e e _ p r o p o s e d . fixed_pkg . a l l ;8 −−−−−−−−−−−−−−−−−−−−−−−−−−−9 PACKAGE PKG_SIGNED IS

10 TYPE SIG_8 IS ARRAY (NATURAL RANGE <>) OF Signed (7 DOWNTO 0) ;11 TYPE SIG_12 IS ARRAY (NATURAL RANGE <>) OF Signed (11 DOWNTO 0) ;12 TYPE SIG_16 IS ARRAY (NATURAL RANGE <>) OF Signed (15 DOWNTO 0) ;13 TYPE SIG_20 IS ARRAY (NATURAL RANGE <>) OF Signed (19 DOWNTO 0) ;14 TYPE SIG_24 IS ARRAY (NATURAL RANGE <>) OF Signed (23 DOWNTO 0) ;15 TYPE SIG_28 IS ARRAY (NATURAL RANGE <>) OF Signed (27 DOWNTO 0) ;16 TYPE SIG_32 IS ARRAY (NATURAL RANGE <>) OF Signed (31 DOWNTO 0) ;17 −−−−−−−−−−−−−−−−−−−−−−−−s i g n e d f i x e d p o i n t a r r a y s18 TYPE SIGS_32 IS ARRAY (NATURAL RANGE <>) OF SFIXED(31 DOWNTO 0) ;19 TYPE SIGS_28 IS ARRAY (NATURAL RANGE <>) OF SFIXED(27 DOWNTO 0) ;20 TYPE SIGS_24 IS ARRAY (NATURAL RANGE <>) OF SFIXED(23 DOWNTO 0) ;21 TYPE SIGS_20 IS ARRAY (NATURAL RANGE <>) OF SFIXED(19 DOWNTO 0) ;22 TYPE SIGS_16 IS ARRAY (NATURAL RANGE <>) OF SFIXED(15 DOWNTO 0) ;23 TYPE SIGS_12 IS ARRAY (NATURAL RANGE <>) OF SFIXED(11 DOWNTO 0) ;24 TYPE SIGS_8 IS ARRAY (NATURAL RANGE <>) OF SFIXED(7 DOWNTO 0) ;25 −−−−−−−−−−−−−−−−−−−−−−−−s p e c i a l a r r a y s26 TYPE SPE_ARR IS ARRAY (NATURAL RANGE <>) OF SFIXED(19 DOWNTO −5) ;−−x i n wl=8 b i t27 TYPE SPE_ARR_12 IS ARRAY (NATURAL RANGE <>) OF SFIXED(23 DOWNTO −5) ;−−x i n wl=12

b i t28 TYPE SPE_ARR_24 IS ARRAY (NATURAL RANGE <>) OF SFIXED(27 DOWNTO −5) ;−−xin_wl =12 ,

coef_wl =12 , t o t a l =33 b i t s29 TYPE SPE_ARR_32 IS ARRAY (NATURAL RANGE <>) OF SFIXED(35 DOWNTO −5) ;−−xin_wl =16 ,

coef_wl =16 , t o t a l =41 b i t s30 TYPE SPE_ARR_40 IS ARRAY (NATURAL RANGE <>) OF SFIXED(43 DOWNTO −5) ;−−xin_wl =20 ,

coef_wl =20 , t o t a l =49 b i t s31 END PKG_SIGNED;

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[8] H. Johansson and O. Gustafsson, “Linear-phase FIR interpolation, decima-tion, and mth-band filters utilizing the Farrow structure,” IEEE Trans. Cir-cuits and Syst. I, vol. 52, pp. 2197–2207, oct. 2005.

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[12] H. Johansson, “Farrow-structure-based reconfigurable bandpass linear-phaseFIR filters for integer sampling rate conversion,” IEEE Trans. Circuits andSyst. II, vol. 58, pp. 46–50, jan. 2011.

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