Implementing a CPU using FPGA

Introduction

These laboratory sessions will continue with your Logic Design laboratory. You shall design and implement a simple

CPU using Terasic DE2-115.

We shall be using the University Program version of Altera software.

http://www.altera.com/education/univ/software/unv-software.html. Download the latest version of Quartus II

and Modelsim for Altera’s University Program. Just download the free web edition. If the web edition is no longer

sufficient, we can use the 30 day trial edition.

Lab Outcomes:

To implement a CPU using FPGA.

Session 1: Combined Verilog and Schematic design using Altera Megafunctions (3 hours)

(i) Follow the instructions in the tutorial file My_First_Fpga.pdf but skip the unnecessary driver installation

procedure. The USB-BLASTER driver has already been installed for you but please note that this tutorial is

the only documentation on the USB-BLASTER installation but it does not work for some MS windows

operating systems.

(ii) This tutorial is a revision of the previous Logic Design HDL laboratory session. However, this time change the

name of the project and top level entity to your name such as OthmanCpu. No student should have the

same name for their top level entity.

(iii) Make sure that your Synopsys Design Constraints File (.sdc) has the same name as your new top level entity.

Question: Change the frequency of the clock fed to the counter and records the effects. (5 marks)

Session 2: Designing and implementing an immediate load instruction 1. (2 hours)

Combine all your knowledge gained so far to design immediate load instructions.

(i) Copy the whole directory into another and rename it. Then proceed to work within the new directory.

(ii) Each student will be given different sets of bits to load while making the unloaded most significant bits

(MSB) zero (zero fill). Use the slide switches (SW) as your inputs. Load 6 bits of data starting from bit

positions corresponding to the last digit of your matriculation number into a 16- bit register.

(iii) You may use Altera’s Megafunctions/storage/lpm_ram_dq for your register but it is better to find an

equivalent using the Megawizard Plugin Manager.

(iv) The output of the registers should be displayed on the red LEDs (LEDR).

(v) Use the push buttons (KEY) as your clocks. Use the key number (Matriculation number) Mod 4. You can use

the calculator program in your Windows operating system to calculate the modulus (Mod) operation.

Question: Draw a diagram to illustrate the instruction format. (5 marks)

Session 3: Designing and implementing an immediate load instruction 2. (1 hour)

(i) Enhance session 2 by storing 6 bits of data starting from the bit positions corresponding to the last digit of

your matriculation number into 4 16-bit registers.

(ii) The address register bits for selecting the registers is placed at the MSB end for those with position

numbers of 4 and less, and vice versa.

(iii) Display the output of the selected registers on the LEDs, using the remaining slide switches 17, 18 to select

the registers to be displayed. Use a 16-bit instruction format.

Question: Draw a diagram to illustrate the instruction format. (5 marks)

Session 4: Designing and implementing immediate operations instructions (1 hour)

Implement a 16-bit adder where operand A is hard programmed with the last digit of your matriculation

number. Operand B is derived from the slide switches as in session 3. You may use the lpm_add_sub but it is better

to find an equivalent using the Megawizard Plugin Manager. If you use the lpm library, you may need to manually

change the instance (inst) labels yourself.

Question: Draw this instruction format. (5 marks)

Session 5: Designing and implementing an opcode decoder (2 hours)

(i) Combine session 3 and 4, by adding an opcode bit. This bit will choose where the inputs selected by the

slide switches will go, either to the registers or to the adder. Draw the instruction format. (5 marks)

(ii) The meaning of this opcode will be different for different groups of students. For those with even

matriculation numbers, the value of A bit = 1 means “not add”. For those with odd matriculation numbers, 1

means “add”.

(iii) Use lpm_mux to choose the desired outputs, either from register or from adder.

(iv) Use lpm_constant to generate the zeros for the zero fill.

(v) Just use bus labelling to connect the bus, BusB[15..0], together.

(vi) Test it by loading an immediate data first by using the “move” instruction, and then add the stored number

with the immediate data using the “add” instruction. Use at least 10 test samples including adding numbers

where the bits are all 1. (10 marks)

(vii) Students with even matriculation numbers, use negative logic for A.

(viii) Students with odd matriculation numbers, use positive logic for A.

Opcode matric mod 12 Opcode matric mod 12RA--- 0 ---AR 6RA--- 1 ---AR 7RA--- 2 ---AR 8RA--- 3 ---AR 9RA--- 4 ---AR 10RA--- 5 ---AR 11Question: Write down your instruction table showing all the bits. (5 marks)

Session 6: Designing and implementing a program memory (3 hours)

(i) Write down a two-instruction machine code program using your implementations in session 5. (2 marks)

(i) Use File/New/Memory Files/Hexadecimal (Intel Hex Format) to create an Intel Hex Format file of binary

data by programming the input bits of a program memory with the binary pattern of your instruction codes.

(ii) Use the Megawizard Plugin Manager to create a 1-port ROM for the program memory.

(iii) Use one of the slide switches to select which program memory address will be used. Note that you can join

busses together by naming your combined bus with the name of the two busses to be combined using a

comma(,) , such as Zero[2..0],ProgMem[12..0].

(iv) Modify it further by using a counter clocked by an oscillator to select the program memory outputs instead

of the slide switches. This counter is called a program counter.

Question: Justify the frequency used for your program counter. (5 marks)

Session 7: Designing and implementing a jump instruction (3 hours)

(i) Increase the program memory into 4 addresses.

(ii) While not changing the location of the register address bits, implement another instruction, the jump

instruction by adding another opcode bit, where the immediate data is loaded to the program counter.

(iii) Students with even matriculation numbers, use negative logic for A, J.

(iv) Students with odd matriculation numbers, use positive logic for A, J.

(v) The assignment for the opcode bits will be further allocated as follows:

R register address bits, J jump, A add

Opcode matric mod 12 Opcode matric mod 12

RJA---- 0 ---JAR 6RJA---- 1 ---JAR 7RAJ---- 2 ---AJR 8RAJ---- 3 ---AJR 9RJA--- 4 ---JAR 10RAJ--- 5 ---AJR 11

(vi) Test the instruction by putting an instruction that does nothing such as adding zero (nop), at address 2, and

jump instruction at address 3. The jump instruction is to jump to address 2, i.e. nop.

(vii) Connect the reset pin of the counter to a push button which is (Matriculation number + 1) mod 4.

(viii) Implement a step utility by using the push button as the clock for the counter instead of from the oscillator.

Question: Write down your instruction table showing all the bits and describe your circuit using Boolean equations.

(5 marks)

Session 8: Designing and implementing a conditional jump instruction (3 hours)

(i) Implement a zero value detector for the output of the register pointed out by the register address bits. It

will output a Z=1 when the value of the pointed register is zero.

(ii) Implement another opcode bit, C, in order to implement the conditional jump instruction when zero.

(iii) You must prepare a truth table for the Load pin of the program counter where the inputs are J, C and Z.

(iv) Now you have 4 opcode bits, 2 address bits, at least 6 immediate data bits for your instruction format.

(v) For the test code, just replace the jump instruction with a conditional jump instruction that tests a register

that is the (matriculation number) mod 4 which is set to zero by an immediate load instruction on reset.

(vi) Students with even matriculation numbers, use negative logic for A and J, positive logic for C.

(vii) Students with odd matriculation numbers, use positive logic for A and J, negative logic for C.

Opcode matric mod 12 Opcode matric mod 12RJAC--- 0 ---CJAR 6RJCA--- 1 ---JCAR 7RAJC--- 2 ---CAJR 8RACJ--- 3 ---ACJR 9RCJA--- 4 ---JACR 10RCAJ--- 5 ---AJCR 11

Question: Write down the truth table that is used to generate the jump address Load pin. (5 marks)

Session 9: Designing and Implementing a register to register instruction (3 hours)

(i) Implement a 3-ported register file design as shown by Mano’s book, Logic and Computer Design

Fundamentals, Fourth Edition, page 464 in Figure 9-1. Alternatively, use Altera’s

Megafunctions/storage/alt3pram.

(ii) The opcode bit can be called I, but the book calls the control signal MB select. The immediate data is called

constant in. Your design is a simplified design of Fig. 1. Your immediate data is sent to operand B.

(iii) Rearrange your immediate data, instead of having adhoc starting positions as in previous assignments. It

should be as large as possible as well as including register address for operand B, SB as well as SA. Your

immediate data for move, jump and cjump instructions is now 10 bits in size.

(iv) Your instruction format should now be Opcode.SD[2].SA[2].SB[2]DATA[6].

(v) Students with even matriculation numbers, use negative logic for A, J, positive logic for I, C.

(vi) Students with odd matriculation numbers, use positive logic for A, J, negative logic for I, C.

Opcode matric mod 24 Opcode matric mod 24IJAC 0 JACI 12IJCA 1 JCAI 13IAJC 2 AJCI 14IACJ 3 ACJI 15ICJA 4 CJAI 16ICAJ 5 CAJI 17

IJAC 6 JAIC 18JICA 7 JCIA 19AIJC 8 AJIC 20AICJ 9 ACIJ 21CIJA 10 CJIA 22CIAJ 11 CAIJ 23Question: Write down your instruction table showing all the bits. (5 marks)

Figure 1: From Mano's figure 9-1, Logic and Computer Design Fundamentals, 4th Ed.

Session 10: Designing and Implementing additional input output instructions ( 3 hours)

(i) Implement the data memory input output. Refer to Fig. 2 which is copied from Figure 9-15 page 489 of

Mano’s book.

(ii) Implement an opcode bit M, called MD in Fig. 2.

(iii) For the data memory, implement only 2 16-bit registers. Use Altera’s ROM module for it. It allows you to

preload with binary bit patterns using Intel hex files.

(iv) Implement your program memory in a similar way. In this way you can preload your program and data

memory using hex files.

(v) Implement your input using switches addressed as data memory at the highest address.

(vi) Similarly, implement your output using LEDs as data memory at the highest address.

Figure 2

tut_quartus_intro_vhdl.pdf

tut_quartus_intro_schematic.pdf

My_First_Fpga.pdf