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Abstract—In this paper, we implement a stepper motor drive system on field programmable gate array (FPGA), and the design is mainly based on vector control strategy. First, the control system is built by MATLAB/Simulink and simulated on Modelsim platform. Next, the resulting software system is converted into Verilog HDL codes, and implemented on an Altera Cyclone III FPGA. The stator’s currents of the developed hardware system are first shown by simulation and experiment to verify the validness and performances of the vector control structure. After that, the speed responses of motor rotor are shown to prove the performances of the outer loop control system and encoder counter circuit. Keywords: MATLAB/Simulink, Stepper Motor, Vector Control, FPGA.
I. INTRODUCTION
Because of the high precision of positioning, no cumulative error and lower costs of the driver, stepper motors are widely used in some automation systems. In addition to the development of modern industry, there are more and more requirements of precision and high speed performance for using the stepper motor as drive system, the control mode of stepper motor is thus gradually developed into closed loop control, and adopts high efficient controller to get better performances [1] as comparing to open-loop control.
Recently, the vector control is widely used on induction motor [2] and permanent magnet synchronous motor (PMSM) [3, 4]. Due to the fact that the hybrid stepper motor is similar to permanent magnet synchronous motor in the mechanism of action, theoretical basis and analysis foundation of the vector control for stepper motor are also proposed [1, 5].
Due to the fact that the flexibility and high performance of Field programmable gate array (FPGA), it has been widely used on the hardware implementation of controller, some examples are about the design of the PID controller [6] and the fuzzy controller [3]. It is also applied on power electronics circuit [7], and the drive system designs of permanent magnet synchronous motor [3, 4], induction motor [2], switched reluctance motor [8], and brushless DC motor [9].
In this study, we use FPGA to the stepper motor drive system design, and the vector control strategy is used to regulate the currents. We first design and build the drive system on MATLAB/Simulink platform [7], and simulate the
Research supported by Ministry of Science and Technology of Taiwan. Chiu-Keng Lai is with the Electrical Engineering Department, National
Chin-Yi University of Technology, Taichung City, 41170 Taiwan. (corresponding author to provide phone: 886-4-23924505 ext 7216; fax: 886-4-23924419; e-mail: [email protected]).
Jhang-Shan Ciou is with the Electrical Engineering Department, National Chin-Yi University of Technology, Taichung City, 41170 Taiwan. (e-mail: [email protected])
Chia-CheTsai is with the Electrical Engineering Department, National Chin-Yi University of Technology, Taichung City, 41170 Taiwan. (e-mail: [email protected]).
software system on Quartus II and Modelsim [10]. The resulting digital hardware system is practically implemented on an Altera Cyclone III FPGA. Finally, the FPGA-based system and the power module are applied to the current and speed control of a hybrid stepper motor to show the validness and performance.
II. THE EXPERIMENTAL SETUP AND MODELLING OF THE
DEVELOPED DRIVE SYSTEM
A. The experimental setup
The experimental hardware setup of the proposed system is shown in Fig. 1. It includes the FPGA board and power module. In the FPGA board, it includes FPGA IC, analog to digital converter (ADC) and digital to analog converter (DAC). In the power board, there are two H-bridge circuits and two Hall current sensors. Besides, the DC power supply and hybrid stepper motor are also shown. The FPGA chip is used to develop the hardware control system which includes the vector control, the speed control and the encoder counter. The ADC is used to get the analog current signals of phases A and B detected by Hall sensors. DAC is used to output the corresponding analog voltage signals of the controlled variables to be checked and compared, and those signals will be shown on oscilloscope. The stepper motor is a hybrid one with rated current 2A, and the DC bus voltage is 24V. Also, the stepper motor is equipped with encoder for speed feedback.
Figure 1. The setup for experiment.
B. The modelling of the stepper motor
The mathematic expressions for two-phase hybrid stepper
motor are shown in (1)~(4) [6],
L
VP
L
Ki
L
R
dt
di aee
ma
a ++−= )sin( θω (1)
L
VP
L
Ki
L
R
dt
di bee
mb
b +−−= )sin( θω (2)
FPGA-based Stepper Motor Vector Control System Design
Chiu-Keng Lai, CACS Member, Jhang-Shan Ciou, and Chia-CheTsai
)]sin()sin([ ebeame PiPiKT θθ +−= (3)
eecLm
m TPFTBdt
dJ =+++ )4sin( θωω (4)
where aV and bV are respectively the voltages of phase A and
B, ai and bi are respectively the currents, R is the resistor,
L is the inductance, mK is the torque constant, eω is the
electrical speed, eθ is the rotor position, P is the rotor teeth
number, eT is the generated torque, J is the rotor inertia, B
is the viscous fraction coefficient, mω is the rotor speed, and
cF is the fourth harmonic detent torque constant. With the modelling of (1)~(4), we have the block as shown
in Fig. 2 named as Stepper-Motor. To realize the vector control for phase currents, ai and bi in (1) and (2), we use the blocks named as 2s to 2e and 2e to 2s to execute the transformation, where
)cos()sin()sin()cos(
ee
eebaq
badθθ
θθ+−=
+= (5)
for stationary to rotation transformation, and
)cos()sin()sin()cos(
ee
eeqdbqda
θθθθ
+=−= (6)
for rotation to stationary transformation. In (5) and (6), eθ is
the rotor position, d and q are the rotation reference variables, a and b are the stationary variable. In the designed system, we create two look-up tables to realize the sine and cosine functions as shown in Fig. 3.
Figure 2. The block diagram for drive system
The system is designed based on a 32-bit data format, variables have their integer part and fractional part as showm in Fig. 4, the mathematic calculations are done with fixed-point structure. The usage of the chip is shown in Table 1.
Table 1. The summary of the usage for the designed system.
(a)
(b)
Figure 3. The (a) sine and (b) cosine tables.
Fig. 4. The block diagram of vector control and data format.
Moreover, we use two PI controllers named as d and q for
the current regulation of phase A and B respectively. Besides, to demonstrate the performance of outer loop velocity control, a velocity PI controller, which accepts the velocity command and the velocity feedback from encoder, is also built. For the
design of digital control system, an inner loop should have a faster sampling time than the outer loop. We thus set the sampling frequency 20kHz for vector current control loop, and 2kHz for velocity control loop.
In order to realize the overall drive systems with FPGA, we first design the system in MATLAB/Simulink, and then simulate them by Modelsim to verify the correctness. Finally, we convert them into Verilog HDL codes. The hardware systems are shown in Fig. 5 where the block named as HDL cosimulation located at the center with yellow is the hardware model of the proposed vector control system for stepper motor. The performance of the system by applying the hardware code to current and velocity controls will be shown on next section.
Figure 5. The resulting hardware digital control system
III. THE SIMULATION RESULTS AND DISCUSSIONS
The simulations are done with the commands of square wave and sinusoidal waveform as shown in Figs. 6-10. First, to show the performances of current regulation, a square wave with amplitude 1A and frequency 100Hz is applied to the current command input. The simulation result is shown in Fig. 6. Next, we change the input to a sinusoidal signal with amplitude 1A and frequencies 100Hz and 500Hz respectively. The simulated results are shown in Figs. 7 and 8. Among them, the blue curve stands for the command, and green curve is the response. The outputs quite match to the command input except a little phase lag and amplitude drop-off.
Next, we demonstrate the simulated results of outer loop speed control by Figs. 9 and 10. In Fig. 9, it is the results with speed command 10 rad/sec, and Fig. 10 is the simulated results with command 200 rad/sec. Those simulated results show the correctness of the designed system. All the figures, cmd is the command input, and fb is the feedback signal.
Figure 6. The responses with command 1A/100 Hz square wave.
Figure 7. The responses with command 2A/100Hz sinusoidal waveform.
Figure 8. The responses with the command of 2A/500Hz sinusoidal waveform.
0 0.002 0.004 0.006 0.008 0.01 0.012 0.014 0.016 0.018 0.02-1.5
-1
-0.5
0
0.5
1
1.5
time(sec)
i q(A)
iq cmd
iq fb
0 0.002 0.004 0.006 0.008 0.01 0.012 0.014 0.016 0.018 0.02-2.5
-2
-1.5
-1
-0.5
0
0.5
1
1.5
2
time(sec)
i q(A)
iq cmd
iq fb
0 0.5 1 1.5 2 2.5 3 3.5 4
x 10-3
-2
-1.5
-1
-0.5
0
0.5
1
1.5
2
time(sec)
i q(A)
iq cmd
iq fb
Figure 9. 10 rad/s square waveform commands and responses. (a) speed; (b)
q-axis current; (c) d-axis current.
Figure 10. 200 rad/s square waveform command and responses.
Figure 11. Current responses with sinusoidal command 2A/100Hz.
Yellow: command, Green: output. (2A/DIV)
Figure 12. Current responses with sinusoidal command 2A/500Hz.
Yellow: command, Green: output. (2A/DIV)
IV. THE EXPERIMENTAL RESULTS AND DISCUSSION
According to the hardware controllers designed in section II, we realize them on Altera Cyclone III FPGA as shown in Fig. 1. For current command inputs, they are respectively sinusoidal waveform and constant DC value. In addition, we assume two kinds of commands, square wave and constant value, for speed control.
Figures 11 and 12 are the experimental current responses for the commands with amplitude 2A, and frequency 100 Hz and 500 Hz respectively. We output the commands and the responses through the DAC converter, and show them on the oscilloscope. The yellow trace is command input and green trace is the system output sensed by the current probe. Since the range of analog voltage output of DAC is 0-5V, we thus set 2.5V as 0A. Furthermore, to separate the input from the output, we set them at different reference level. Figures 11 and 12 show that the responses for different frequency inputs can get a quite good performance only with a little phase lag and amplitude drop-off. For demonstrating the performances of constant current commands, we respectively set the command currents to be 0.5A and 1 A, and their results are shown in Figs. 13 and 14. For 0.5A command, the steady-state response quite matches to the desired level. Since the back emf is proportional to the motor speed, there is steady-state error for 1A DC command as shown in Fig. 14.
Figure 13. Current responses with constant command 0.5 A.
Yellow: command, Green: output. (0.5A/DIV)
Figure 14. Current responses with constant command 1 A. Yellow: command, Green: output. (1A/DIV)
Figure 15. Speed responses with command 0 rpm and 400 rpm in 0.5 Hz.
Yellow: command, Green: output.
Figure 16. Speed responses with constant command 800 rpm.
Yellow: command, Green: output.
Next, we verify the performances by adding the velocity loop to the system, and show the speed responses for square wave speed and constant speed commands. Fig. 15 is the results with two speed commands, 0 rpm and 400 rpm, the responses quite match to the command. After that, we put a constant speed input of 800 rpm, and its outputs are shown in Fig. 16.
V. CONCLUSIONS
In this paper, we have demonstrated the design of stepper motor current controllers by vector control, and realized them with the FPGA chip. The performance of current vector controller is verified by constant and sinusoidal command inputs, and the speed control loop is evaluated by the commands of constant and square wave. The simulation and practical realization results show that the performances of stepper motor drive system by vector control strategy and FPGA chip have successfully reached to the desired. And it is an easy way to design a hardware digital system starting from MATLAB/Simulink. The further works should be in increasing the motor speed as high as about 3000rpm, and optimizing the circuits by reducing the usage of gate counters.
ACKNOWLEDGMENT
The authors would like to thank the financial support of Ministry of Science and Technology of Taiwan under grant number MOST 106-2622-E-167-008-CC3.
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