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International Journal of Communications and Engineering
Volume 03– No.3, Issue: 01 March2012
Page 45
FPGA BASED INDIRECT POSITION DETECTION
AND SPEED CONTROL OF PMBLDC MOTOR
USING VIRUTAL INSTRUMENTATION
ABSTRACT
Recently, the brushless dc (BLDC) motor is becoming popular in various applications because of its
high efficiency, high power factor, high torque, simple control, and lower maintenance. Moreover,
reducing of the drive components is more attractive for low cost applications. This paper proposes a
speed response of the FPGA-based sensorless control of brushless dc(BLDC) motor drives. The
sensorless position detection proposed in this paper is based on the detection of zero crossing points of the
line voltage difference measured at the terminals of the motor using Virtual Instrumentation.The speed
control of the motor is obtained by pulse width modulation of the pulses given to the MOSFET inverter
circuit using FPGA. The effectiveness of the proposed method is demonstrated through simulation and
experimental results
Index Terms: Brushless machines, Inverters, Zero-crossing Detection, Virtual Instrumentation, Labview,
Field programmable gate array (FPGA), Sensorless control.
I.INTRODUCTION
Permanent magnet brushless dc (BLDC)
motors have used wide application due to their
power density and ease of control. Moreover, the
machines have high efficiency over a wide speed
range. Therefore, it is suitable for variable speed
applications and results in energy saving
[machines and Stepper motors.
The control of BLDC motors can be done in
sensor or sensorless mode, but to reduce overall
cost of actuating devices, sensorless control
techniques are normally used. The advantage of
sensorless BLDC motor control is that the
sensing part can be omitted, and thus overall
costs can be considerably reduced. Sensorless
control is highly advantageous when the motor
is operated in dusty or oily environment, where
cleaning and maintaining of Hall Sensors is
required for proper sensing of rotor position.
Sensorless method is preferred when the
motor is in less accessible location.
Accommodation of position sensor in motor
used in compact unit such as computer hard disk
may not be possible. Novel direct back emf
detection for sensorless BLDC motor is given in
[7]. The BLDC motor without position and
speed sensors has attracted wide attention and
many papers have reported work on this. These
International Journal of Communications and Engineering
Volume 03– No.3, Issue: 01 March2012
Page 46
methods are based on using back-EMF of the
motor, detection of the conducting state of
freewheeling diode in the unexcited phase ,
back-EMF integration method, detection of
stator third harmonic voltage components.
Back-EMF estimation methods typically on
the zero crossing detection of the EMF
waveform. In the method proposed in this paper
the line voltage difference is fed to the virtual
instrument developed in Lab VIEW through
serial communication and the zero crossing
points are detected. Using thisdetails pulses for
the inverter circuit are generated. The generated
pulses are given to the FPGA (field
programmable array) through serial port and the
pulse width modulation is done according to the
set speed. The method is simple, reliable and
does not involve any integration. Further, since
line voltages are used, the requirement of neutral
potential has been eliminated. The Zero crossing
instants are done using virtual circuits developed
in Labview. This also eliminates the common
mode noise. Device drops and their variations
would also not play a part since line voltages are
used.
Section II describes the proposed back-EMF
zero crossing estimation method. Section III
hardware implementation of the proposed
method. Section IV presents the virtual
instrument and results that validate the proposal
and section V presents the conclusion.
II. THE PROPOSED BACK-EMF ZERO
CROSSING ESTIMATION METHOD
Typically, a BLDC motor is wound in a
three-phase wye configuration. This
configuration connects one end of each phase
together to make a center point of a “Y” or the
motor neutral point. This is then driven by a
three-phase inverter with what is called six-step
commutation. At any step, only two of the three
phases are conducting current where current
flows into one phase and then out another. For
example, when phase A and phase B conduct
current, phase C is floating. A transition from
one step to another step is called commutation.
So, totally, there are six steps in one cycle. As
shown in Fig. 1, the first step is AB (phase A and
B conducting current), then to AC, to BC, to BA,
to CA, to CB and then the pattern is repeated. In
order to produce maximum torque, the inverter
should be commutated every 60 electrical
degrees so that current is in phase with the back
EMF. The conducting interval for each phase is
120 electrical degrees, or two steps. The
commutation timing is determined by the rotor
position, which can be determined every 60
electrical degrees by detecting when the back
EMF on the floating phase crosses the zero
potential point, or “zero crossing.” Fig. 1 shows
the typical inverter configuration and current
commutation sequence.
As mentioned above, since only two phases
are conducting current at any step, one phase is
available to measure back EMF. To measure the
back EMF across a phase the conventional
method (shown in Fig. 2) requires monitoring
the phase terminal and the motor neutral point.
The zero crossing of the back EMF can be
obtained by comparing the terminal voltage to
the neutral point. In most cases, the motor
neutral point is not available. The most
commonly used method is to build a virtual
neutral point that will, in theory, be at the same
potential as the neutral point of the wye-wound
motor. This conventional detection scheme is
quite simple and has been in use for some time
[1]. However, this scheme has its drawbacks.
When using PWM to regulate motor speed or
torque/current for instance, the virtual neutral
point fluctuates at the PWM frequency. As a
result there is a very high common-mode voltage
and high-frequency noise.
International Journal of Communications and Engineering
Volume 03– No.3, Issue: 01 March2012
Page 47
Then the phase A terminal voltage with
respect to the star point of the stator Van, is
Van = Raia + La (dia/dt) +ean - (1)
Similar equations for the other two phases are,
Vbn = Rbib+ Lb (dib/dt) +ebn - (2)
Vcn = Rcic + Lc (dic/dt) +ecn - (3)
From equation (1),(2),(3) the line voltage Vab
and Vbc may be determined
Vab = Van - Vbn
= R (ia- ib) + L (d (ia- ib ) /dt) + ean-ebn
Vbc = Vbn – Vcn
= R (ib- ic) + L (d (ib- ic) /dt) +ebn- ecn
.
Fig 1: PMBLDC drive and Zero crossing
points of the back-EMF and phase current
commutation points.
In the interval when phases A and C are
conducting and phase B is open, phase A
winding is connected to the positive of the DC
supply, phase C to the negative of the DC
supply and phase B is open. Therefore ia = -ic
and ib = 0. Therefore in this interval the equation
is simplified as,
Vabbc = Vab - Vbc = -2 ebn
The line voltage difference waveform is thus
an inverted representation of the back-EMF
waveform. The error between the line voltage
difference and back EMF ,also shown in Fig. 2
is negligible at the zero crossing instant.
Therefore the operation Vab-Vbc (Vabbc) enables
detection of the zero crossing of the phase B
EMF. Similarly the line voltage difference
Vbcca enables the detection of zero crossing of
phase C back-EMF. The line voltage difference
Vcaab waveform gives the zero crossing of phase
A back-EMF. Therefore the zero crossing
instants of the back-EMF waveforms may be
estimated indirectly from the line voltage
differences.
The line voltage difference waveform is fed in
to the virtual instrument developed in LabVIEW
using RS232 serial communication. In the VI the
zero crossing of the back e.m.f is determined
and the switching signals are generated.
The switching signals are further fed to the
FPGA. In Field programmable array the pulse
width modulation of the particular signals are
performed and fed to the MOSFET inverter
circuit. The set speed is given by the user in the
VI developed in LabVIEW and its fed to the
FPGA using serial communication.
International Journal of Communications and Engineering
Volume 03– No.3, Issue: 01 March2012
Page 48
Fig 2: Line voltage difference and back-EMF
III. DESCRIPTION OF EXPERIMENTAL
SETUP
The block diagram of the experimental setup of
the proposed sensorless BLDC motor drive is
shown in fig.3. The experimental setup consists
of a 24v, 8000rpm 4pole PMBLDC drive. In a
three-phase brushless motor and a 120-
electrical-degreetype inverter, transistor
commutation occurs at intervals of 60 electrical
degrees. This causes important transient in the
motor terminal voltages, so some techniques are
necessary for the direct use of these voltages for
sensing rotor position. Three phase bridge
inverter fabricated using n – channel MOSFET
is operated in 120 degree mode to provide
square wave current excitation to the stator
windings. MOSFETs are used to control the
speed of the motor by varying the supply voltage
to the motor. It is switched with very high speed
with the help of PWM waves. The PWM waves
are generated by the FPGA.
Inverter switches are triggered in a sequence
provided by the high performance digital
controller IC MC 33035. The IC contains all the
functions required to implement a full featured
open loop control. The output of MC 33035 is
ideally suited for driving power MOSFETs of
low ratings. To drive MOSFETs of higher
ratings the outputs of MC 33035 are given to
driver circuits through opto-couplers. MC 33035
is capable of controlling the speed of the motor
in open loop mode only. For closed loop
operation, it requires an input voltage
proportional to the motor speed. This can be
achieved using MC 33039.
Fig 3: Experimental setup
The isolation circuit is mainly used to isolate
the high voltage and low voltage circuit, SCR
and Triac circuit, mechanical relay and pulse
transformer. Here the 4N35 opto coupler
constructs the isolation circuit. The opto coupler
consists of photo LED and phototransistor. The
phototransistor conducts only when light rays
falls on the base of the transistor. The signal to
be isolated is given to base of BC547 switching
transistor.
An FPGA platform used for controlling the
BLDC machine is Spartan 3 family, from Xilinx.
Reference speed value was set digitally, and a
speed loop was used to compare the actual speed
and the reference speed and based on error to
determine the duty cycle for the next period. The
actual speed was easily calculated as a time
between line voltages. Furthermore, this scheme
can be effectively implemented on an FPGA as
opposed to DSPs that are used for the
implementation of complex control schemes.
International Journal of Communications and Engineering
Volume 03– No.3, Issue: 01 March2012
Page 49
This makes the present technique significantly
cost effective. The FPGA operates at a clock
frequency of 12 MHz.
IV.VIRTUAL INSTRUMENTATION AND
ITS EXPERIMENTAL RESULTS
LabVIEW is a graphical programming language
that uses icons instead of lines of text to create
applications. LabVIEW programs are called
virtual instruments, or VIs, because their
appearance and operation imitate physical
instruments, such as oscilloscopes and
multimeters LabVIEW program facilitates
virtual instrumentation (VI), which imitates the
appearance and operation of physical
instruments: VI is defined as a process of
combining hardware and software with industry
standard computer technology to create a user-
defined instrumentation solution. Several other
add-on toolsets can be incorporated for
developing the specialised applications. Labview
done the zero crossing detection and speed ,
current and voltage measurements.
Fig 4: Timing simulation of the trigger for
estimated commutations
Table B shows how much logic resource of
FPGA is used to implement the whole system,
and as shown in the table every item is below
40%. It means one can select a smaller and Low
cost FPGA S350, to further reduce the cost, or
one can also build up a microcontroller
Intellectual Properties (IP)into FPGA to
implement more sophisticated control algorithm.
The Generation of pwm is implemented in
Xilinx FPGA. Fig 4 shows the timing simulation
of the trigger for estimated commutations
Fig 5: Experimental set-up for the proposed
method
The experimental results for the speed
response of the FPGA-based sensorless control
of brushless dc motor are discussed for the
desired speed. Figure 5 shows the experimental
set-up for the proposed method. Figure 6 shows
the measured back emf waveform for the
proposed method. Figure 7 shows the results for
the speed control of brushless dc motor using
Labview. The set speed and the actual speed of
the motor is also displayed in front panel of
labview. The actual speed value for the different
set speed is given in Table1.
International Journal of Communications and Engineering
Volume 03– No.3, Issue: 01 March2012
Page 50
Fig 6: Line voltage Difference
Table 1 Speed Obtained for different Set
speed in this proposed method.
Fig 7: Results for the proposed method
V. CONCLUSION
This paper has presented a novel FPGA-based
sensorless control scheme for six-switch three-
phase brushless dc motor drives. In the scheme,
the speed response of the FPGA-based
sensorless control of brushless dc(BLDC) motor
drives is proposed. The position information is
estimated from the crossings of voltage
waveforms in floating phases, and a low cost
FPGA is utilized to implement the algorithm.
Because the stator current waveforms of the
inverter using this novel voltage PWM scheme
are rectangular, the motor will operate smoothly
and the torque ripple will be reduced. Compared
with the conventional back EMF zero crossing
sensorless control, the proposed new sensorless
control methods for brushless DC technique is
more robust, easier to implement, and cost
Effective because of virtual instrumentation and
FPGA. Theoretical analysis and experimental
results verified that satisfactory performance is
achieved with the motors with the proposed
method.
APPENDIX
A. PMBLDC Motor Specifications
Number of poles 4 Poles
Line to line resistance 0.2 ohms
Lineto line inductance 0.45 mH
Nominal voltage 24 V
Rated current 3A
Rated Speed 8000RPM
B.Device utilizations summary of Fpga:
S.No Set Speed
RPM
Actual Speed
RPM
1 2500 2560
2 4500 4560
3 5000 5120
4 6200 6260
5 7500 7520
International Journal of Communications and Engineering
Volume 03– No.3, Issue: 01 March2012
Page 51
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