Training Courseon

FPGA based Digital Design using Verilog HDL

By

NAUMAN MIRNAUMAN MIR( HDL Designer )

* Organized by Skill Development Council Organized by Skill Development Council, ( Ministry of Labour, Manpower and overseas Pakistani )

Govt. of Pakistan.

Core GeneratorThe CORE Generator System is a design tool that

delivers parameterized cores optimized for Xilinx® FPGAs. It provides you with a catalog of ready-madefunctions ranging in complexity from simple p y parithmetic operators suchas adders, accumulators,and multipliers to systemand multipliers, to system-level building blocks suchas filters, transforms, FIFOs, and memories.

FPGA FPGA based Digital Design using Verilog HDL( f p g a c o u r s e @ y a h o o . c o m )

Core Generator – contd.Starting the CORE Generator from Xilinx ISEThe CORE Generator can be opened from within

P j t N i t i thProject Navigator in these ways:If you have added a core to an ISE project, you can

then open theCORE Generator GUI from within the ISE Projectthe ISE Project Navigator. Project Navigator will run on a PCon a PC.

FPGA FPGA based Digital Design using Verilog HDL( f p g a c o u r s e @ y a h o o . c o m )

Core Generator – contd.To open the CORE Generator GUI from within Xilinx ISE:a. In Project Navigator, select an IP core name in

the Sources in Project windowthe Sources in Project window.b. Click the "+" icon

next to the Coregeni h Pprocess in the Process-

es for Current Sourcewindow.

The Manage Cores proce-ss shows in the process-

i des window.c. Double-click on ManageCores. The CORE Gener-

FPGA FPGA based Digital Design using Verilog HDL( f p g a c o u r s e @ y a h o o . c o m )

ator window displays.

Core Generator – contd.To Instantiate an IP Core in an HDL Source

1. Select Edit > Language Template to open the Language Template windowLanguage Template window.

2. Click the "+" iconnext to COREGENi h Lin the Language Template window.The COREGEN directory will expand.

Copy & Paste into your Design File

FPGA FPGA based Digital Design using Verilog HDL( f p g a c o u r s e @ y a h o o . c o m )

Core Generator – contd.3. Click the "+" on either VHDL Component

Instantiation or Verilog Component Instantiation The list of availableInstantiation. The list of available instantiation templates will expand.

4. Click on the core to display the instantiation t l t t t Th t l t ill di ltemplate you want to use. The template will display in the right pane of the Language Template window.

5. Cut and paste the template into the open HDL file in p p pthe ISE Text Editor window.

FPGA FPGA based Digital Design using Verilog HDL( f p g a c o u r s e @ y a h o o . c o m )

Design ExampleGenerate Block RAM Core from Core Generator Tool (ISE 8.2i)

FPGA FPGA based Digital Design using Verilog HDL( f p g a c o u r s e @ y a h o o . c o m )

Design ExampleGenerate Block RAM Core from Core Generator Tool (ISE 8.2i)

FPGA FPGA based Digital Design using Verilog HDL( f p g a c o u r s e @ y a h o o . c o m )

Design ExampleGenerate Block RAM Core from Core Generator Tool (ISE 8.2i)

FPGA FPGA based Digital Design using Verilog HDL( f p g a c o u r s e @ y a h o o . c o m )

Design ExampleGenerate Block RAM Core from Core Generator Tool (ISE 8.2i)

FPGA FPGA based Digital Design using Verilog HDL( f p g a c o u r s e @ y a h o o . c o m )

Design ExampleGenerate Block RAM Core from Core Generator Tool (ISE 8.2i)

FPGA FPGA based Digital Design using Verilog HDL( f p g a c o u r s e @ y a h o o . c o m )

Design ExampleGenerate Block RAM Core from Core Generator Tool (ISE 8.2i)

FPGA FPGA based Digital Design using Verilog HDL( f p g a c o u r s e @ y a h o o . c o m )

Design ExampleGenerate Block RAM Core from Core Generator Tool (ISE 8.2i)

FPGA FPGA based Digital Design using Verilog HDL( f p g a c o u r s e @ y a h o o . c o m )

Design ExampleGenerate Block RAM Core from Core Generator Tool (ISE 8.2i)

FPGA FPGA based Digital Design using Verilog HDL( f p g a c o u r s e @ y a h o o . c o m )

Design ExampleGenerate Block RAM Core from Core Generator Tool (ISE 8.2i)

FPGA FPGA based Digital Design using Verilog HDL( f p g a c o u r s e @ y a h o o . c o m )

Design ExampleGenerate Block RAM Core from Core Generator Tool (ISE 8.2i)

FPGA FPGA based Digital Design using Verilog HDL( f p g a c o u r s e @ y a h o o . c o m )

Design ExampleGenerate Block RAM Core from Core Generator Tool (ISE 8.2i)

FPGA FPGA based Digital Design using Verilog HDL( f p g a c o u r s e @ y a h o o . c o m )

Design ExampleGenerate Block RAM Core from Core Generator Tool (ISE 8.2i)

FPGA FPGA based Digital Design using Verilog HDL( f p g a c o u r s e @ y a h o o . c o m )

Design ExampleGenerate Block RAM Core from Core Generator Tool (ISE 8.2i)

FPGA FPGA based Digital Design using Verilog HDL( f p g a c o u r s e @ y a h o o . c o m )

Design ExampleGenerate Block RAM Core from Core Generator Tool (ISE 8.2i)

FPGA FPGA based Digital Design using Verilog HDL( f p g a c o u r s e @ y a h o o . c o m )

Design ExampleGenerate Block RAM Core from Core Generator Tool (ISE 8.2i)

FPGA FPGA based Digital Design using Verilog HDL( f p g a c o u r s e @ y a h o o . c o m )

Constraints EditorConstraints Editor: The Constraints Editor is a

graphical user interface (GUI) tool for entering timing g p ( ) g gconstraints and pin location constraints. The user interface simplifies constraint entry by guiding you through constraint creation without your needing tothrough constraint creation without your needing to understand UCF (User Constraint File) file syntax.

The Constraints Editor interface consists of a mainThe Constraints Editor interface consists of a main window, four tab windows, a constraints window, an output window, and numerous dialog boxes.

FPGA FPGA based Digital Design using Verilog HDL( f p g a c o u r s e @ y a h o o . c o m )

Constraints Editor – contd.Starting the Constraints Editor from the Project

Navigator: Within the Project Navigator, you can launch th C t i t Edit f th P i d Fi tthe Constraints Editor from the Processes window. First select a design file in the Sources window. Then double-click Create Timing gConstraints in the Processes window, which is locatedwhich is locatedwithin User Constr-aints underneath D i UtilitiDesign Utilities.

FPGA FPGA based Digital Design using Verilog HDL( f p g a c o u r s e @ y a h o o . c o m )

Constraints Editor – contd.2. With the design loaded in the Constraints Editor, go to

the Ports tab.3 Right click in the Location field corresponding to the3. Right-click in the Location field corresponding to the

desired I/O signal.4. In the Location dialog box, enter the desired pin

location.

Pad to Setup / Clock to PadpSpecifies the timing relationshipbetween an external clock and data at the pins of a devicedata at the pins of a device. Operates on pads or predefined groups of pads.

FPGA FPGA based Digital Design using Verilog HDL( f p g a c o u r s e @ y a h o o . c o m )

Constraints Editor – contd.PeriodDefines a clock period.LocationLocationLocks a user-defined port to a device pin.FAST/SLOWAssigns a slew rate to selected port.PULLUP/PULLDOWNSignifies a pull level (PULLUP, PULLDOWN, or KEEPER) S g es a pu e e ( U U , U O , o )for a selected output port.KEEPER is used for Virtex devices only. When a 3-state buffer goes to high impedance KEEPER keeps the input level of the bufferimpedance,KEEPER keeps the input level of the buffer on the pad net.

FPGA FPGA based Digital Design using Verilog HDL( f p g a c o u r s e @ y a h o o . c o m )

Constraints Editor – contd.DRIVEThis constraint assigns a signal strength to a selected portport.IOSTANDARDAssigns an input/output standard (LVTTL, LVCMOS, and so forth) to a selected net attached to the port.

FPGA FPGA based Digital Design using Verilog HDL( f p g a c o u r s e @ y a h o o . c o m )

Constraints Editor – contd.Assigning Pins Using Xilinx PACE Tool..

To assign pin locations using the Xilinx PACE:1 I th P f S i d d th U1. In the Processes for Source window, expand the User

Constraints tree and double-click onthe Assign PackagePins to display the Xilinx PAECTool.Tool.

FPGA FPGA based Digital Design using Verilog HDL( f p g a c o u r s e @ y a h o o . c o m )

Design Synthesisg yXilinx Synthesis Technology (XST) Flow:

XST is a Xilinx® tool that synthesizes HDL designs to create Xilinx® specific netlist files called NGC files. The NGC file is a netlist thatcontains both logical designg gdata and constraints that takes the place of both EDIF and NCF filesand NCF files.

FPGA FPGA based Digital Design using Verilog HDL( f p g a c o u r s e @ y a h o o . c o m )

Xilinx Synthesis Technology (XST)y gy ( )XST in Project Navigator:

Before you synthesize your design, you can set avariety of options for XST. The following are theinstructions to set the options andrun XST from Project Navigator.run XST from Project Navigator.1. Select your top-level design in the Source window.

FPGA FPGA based Digital Design using Verilog HDL( f p g a c o u r s e @ y a h o o . c o m )

Xilinx Synthesis Technology (XST) – contd.2. To set the options, right-click Synthesize - XST in

the Process window.3. Select Properties to display the Process Properties3. Select Properties to display the Process Properties

dialog box.

FPGA FPGA based Digital Design using Verilog HDL( f p g a c o u r s e @ y a h o o . c o m )

Xilinx Synthesis Technology (XST) – contd.4. When synthesis is complete, view the results by double-clicking View Synthesis Report. Following is a portion of a sample report.portion of a sample report.

FPGA FPGA based Digital Design using Verilog HDL( f p g a c o u r s e @ y a h o o . c o m )

Xilinx Synthesis Technology (XST) – contd.HDL Coding Techniques for XST:

Designs are usually made up of combinatorial logicg y p gand macros (for example, flip-flops, adders, subtractors, counters, FSMs, RAMs). The macros greatly improve performance of the synthesizedgreatly improve performance of the synthesizeddesigns. Therefore, it is important to use some codingtechniques to model the macros so that they are

ti ll d b XSToptimally processed by XST.

NOTE: For detail please see the XST User Guide

FPGA FPGA based Digital Design using Verilog HDL( f p g a c o u r s e @ y a h o o . c o m )

Xilinx Synthesis Technology (XST) – contd.HDL Coding Techniques for XST:

During its run, XST first tries to recognize (infer) asDuring its run, XST first tries to recognize (infer) as many macros as possible. Then all of these macros arepassed to the Low Level Optimization step, either preserved as separate blocks or merged withpreserved as separate blocks or merged with surrounded logic in order to get better optimizationresults. This filtering depends on the type and size of amacro (for example, by default, 2-to-1 multiplexersare not preserved by the optimization engine). You have full control of the processing of inferred macroshave full control of the processing of inferred macrosthrough synthesis constraints.

FPGA FPGA based Digital Design using Verilog HDL( f p g a c o u r s e @ y a h o o . c o m )

Xilinx Synthesis Technology (XST) – contd.Language Support TablesThe following tables indicate which Verilog constructs are supported in XSTsupported in XST.

FPGA FPGA based Digital Design using Verilog HDL( f p g a c o u r s e @ y a h o o . c o m )

Xilinx Synthesis Technology (XST) – contd.Language Support Tables

FPGA FPGA based Digital Design using Verilog HDL( f p g a c o u r s e @ y a h o o . c o m )

Xilinx Synthesis Technology (XST) – contd.Language Support Tables

FPGA FPGA based Digital Design using Verilog HDL( f p g a c o u r s e @ y a h o o . c o m )

Xilinx Synthesis Technology (XST) – contd.Language Support Tables

FPGA FPGA based Digital Design using Verilog HDL( f p g a c o u r s e @ y a h o o . c o m )

Xilinx Synthesis Technology (XST) – contd.Verilog Reserved Keywords

FPGA FPGA based Digital Design using Verilog HDL( f p g a c o u r s e @ y a h o o . c o m )