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Four Bit ALU Presented By: Project Manager: Arturo Coronado Digital Circuit Design: Rodger Stamness Clocking: Rodger Stamness I/O: Juan Tello

Four Bit ALU Presented By: Project Manager: Arturo Coronado Digital Circuit Design: Rodger Stamness Clocking:Rodger Stamness I/O:Juan Tello

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Page 1: Four Bit ALU Presented By: Project Manager: Arturo Coronado Digital Circuit Design: Rodger Stamness Clocking:Rodger Stamness I/O:Juan Tello

Four Bit ALU

Presented By:

Project Manager: Arturo Coronado

Digital Circuit Design: Rodger Stamness

Clocking: Rodger Stamness

I/O: Juan Tello

Page 2: Four Bit ALU Presented By: Project Manager: Arturo Coronado Digital Circuit Design: Rodger Stamness Clocking:Rodger Stamness I/O:Juan Tello

Objective

• Familiarization with the full custom IC design methodology.

• Develop good test and debugging skills.

• Learn to work on a team

• Learn documentation procedures

• Have fun!!!!!!

Page 3: Four Bit ALU Presented By: Project Manager: Arturo Coronado Digital Circuit Design: Rodger Stamness Clocking:Rodger Stamness I/O:Juan Tello

Design Flow

Page 4: Four Bit ALU Presented By: Project Manager: Arturo Coronado Digital Circuit Design: Rodger Stamness Clocking:Rodger Stamness I/O:Juan Tello

Philips’s 74L181

Page 5: Four Bit ALU Presented By: Project Manager: Arturo Coronado Digital Circuit Design: Rodger Stamness Clocking:Rodger Stamness I/O:Juan Tello

Specifications

• Functionality: Logic and Arithmetic implementation of Philips 74L181

• Frequency: 25MHz

• Power: 750 mW

• Area: 1800 X 1800

Page 6: Four Bit ALU Presented By: Project Manager: Arturo Coronado Digital Circuit Design: Rodger Stamness Clocking:Rodger Stamness I/O:Juan Tello

Chip Input & Output Circuits

• Design quality is a critical factor

-Reliability

-Signal Integrity

-Interchip Communication speed

• ESD

-Most prevalent causes for chip failures:

-Manufacturing and Field Operation

Page 7: Four Bit ALU Presented By: Project Manager: Arturo Coronado Digital Circuit Design: Rodger Stamness Clocking:Rodger Stamness I/O:Juan Tello

Schimtt Trigger

Page 8: Four Bit ALU Presented By: Project Manager: Arturo Coronado Digital Circuit Design: Rodger Stamness Clocking:Rodger Stamness I/O:Juan Tello

Super Buffer

Page 9: Four Bit ALU Presented By: Project Manager: Arturo Coronado Digital Circuit Design: Rodger Stamness Clocking:Rodger Stamness I/O:Juan Tello

Padframe Floor plan

Page 10: Four Bit ALU Presented By: Project Manager: Arturo Coronado Digital Circuit Design: Rodger Stamness Clocking:Rodger Stamness I/O:Juan Tello

Functions

Page 11: Four Bit ALU Presented By: Project Manager: Arturo Coronado Digital Circuit Design: Rodger Stamness Clocking:Rodger Stamness I/O:Juan Tello

Cell-Base implementation

• A.O.I each function to get circuits.

• Each circuit is turned into a cell.

• Each cell builds up the ALU one cell at time; thus Bottom-Up design.

• Approximately 1/3 of the Design

Page 12: Four Bit ALU Presented By: Project Manager: Arturo Coronado Digital Circuit Design: Rodger Stamness Clocking:Rodger Stamness I/O:Juan Tello

Transistor Level Design

Page 13: Four Bit ALU Presented By: Project Manager: Arturo Coronado Digital Circuit Design: Rodger Stamness Clocking:Rodger Stamness I/O:Juan Tello

Cell Z1

Page 14: Four Bit ALU Presented By: Project Manager: Arturo Coronado Digital Circuit Design: Rodger Stamness Clocking:Rodger Stamness I/O:Juan Tello

Cell-Base implementation

Page 15: Four Bit ALU Presented By: Project Manager: Arturo Coronado Digital Circuit Design: Rodger Stamness Clocking:Rodger Stamness I/O:Juan Tello

Layout Cellular Design

Page 16: Four Bit ALU Presented By: Project Manager: Arturo Coronado Digital Circuit Design: Rodger Stamness Clocking:Rodger Stamness I/O:Juan Tello

Final ALU Test Bench

Page 17: Four Bit ALU Presented By: Project Manager: Arturo Coronado Digital Circuit Design: Rodger Stamness Clocking:Rodger Stamness I/O:Juan Tello

Waveform

Page 18: Four Bit ALU Presented By: Project Manager: Arturo Coronado Digital Circuit Design: Rodger Stamness Clocking:Rodger Stamness I/O:Juan Tello

Project Update

• Completed:

-15/16 Functional Logic Blocks

-DFF

-Superbuffer

-Schmitt Trigger

• To be Completed

-Final Floor Plan and Verification Block

-Full Layout Assembly and Test

May 15, 2002