AUTOMATIC REFINEMENT OF ESL MODEL ABSTRACTIONS

by

Reema AgarwalID 0663834

Under the supervision of

Prof. Anshul KumarProfessor, CS & E (IIT, Delhi) &

Mrs. Ritu SharmaSr. Lecture, E & CE (MNIT, Jaipur)

MALAVIYA NATIONAL INSTITUTE OF TECHNOLOGY, JAIPURJUNE 2008

DEPARTMENT OF ELECTRONICS & COMMUNICATION ENGINEERING

AUTOMATIC REFINEMENT OF ESL MODEL ABSTRACTIONSSubmitted in partial fulfillment of requirements for the degree of

MASTER OF TECHNOLOGYby

Reema AgarwalID 0663834

Under the supervision of

Prof. Anshul KumarProfessor, CS & E (IIT, Delhi) &

Mrs. Ritu SharmaSr. Lecture, E & CE (MNIT, Jaipur)

MALAVIYA NATIONAL INSTITUTE OF TECHNOLOGY, JAIPURJUNE 2008

DEPARTMENT OF ELECTRONICS & COMMUNICATION ENGINEERING

ACKNOWLEDGEMENTOne of the most pleasant parts of writing a thesis is the opportunity to thank those who have contributed to it. Unfortunately the list of expression of thanks, no matter how extensive, is always incomplete and inadequate. These acknowledgements are no exceptions. I am greatly indebted to my supervisor Professor Anshul Kumar, Department of Computer Science & Engineering, Indian Institute of Technology, Delhi for giving me the privilege to work under his esteemed guidance. I am grateful for his invaluable technical guidance and moral support during the project work. I would like to owe my deep rooted heartiest thanks to Dr. Preeti Ranjan Panda for his precious guidance and support during my learning period in IIT, Delhi. into the problems. I take this opportunity to offer my sincere and whole hearted gratitude to my guide Mrs. Ritu Sharma, Malaviya National Institute of Technology, Jaipur for her kind and invaluable guidance throughout the period of my M. Tech. dissertation. I would like to extend my gratitude to Dr. Vineet Sahula for his guidance and constructive encouragement. Last but not the least; I would like to thank all my friends and colleagues for their direct and indirect support and also making my stay in IIT Delhi and MNIT enjoyable and memorable. Reema Agarwal ID 0663834 M.Tech. (VLSI) MNIT, Jaipur I am very much grateful to my supervisor Aravinda Thimmapuram at NXP semiconductor, Bangalore for his valuable guidance and deep in sight

ABSTRACTESL can model a system at different abstraction levels such as programmers view (PV), Architects View (PV+T) and Verification View (VV) and they are needed to serve different use cases (Software development, architectural exploration). The modeling at different abstraction level is possible by using SystemC based Transaction Level Modeling (TLM). For development of any peripheral we have used features of COWARE SystemC modeling library and TLM peripheral modeling library. Manual development of all these abstraction levels is effort consuming and error prone activity. This project aims to develop an automatic methodology for refinement of abstraction levels with some additional inputs preserving the original functionality.

CONTENTSACKNOWLEDGEMENT ........................................................................... I ABSTRACT ............................................................................................... III CONTENTS ............................................................................................... V LIST OF FIGURES ................................................................................. VII

CHAPTER 1: INTRODUCTION ....................................11.1 1.2 1.3 1.4 1.5 Objective ............................................................................................................... 1 Motivation ............................................................................................................. 2 Related Work ......................................................................................................... 2 Methodology .......................................................................................................... 3 Thesis Organization ............................................................................................... 3

CHAPTER 2: BACKGROUND ...................................... 52.1 SystemC ................................................................................................................. 5 2.1.1 SystemC 2.0 Language Architecture ................................................................... 5 2.1.2 Overview Of SystemC Components .................................................................. 6 2.1.3 SystemC Simulation Kernel ................................................................................ 7 2.2 Transaction Level Modeling ................................................................................... 8 2.2.1 What Is A Transaction? ...................................................................................... 8 2.2.2 TLM Use Cases And Abstraction Levels ............................................................ 9

CHAPTER 3: MODELING TLM PERIPHERALS ..... 133.1 General Modeling Methodology ........................................................................... 13 Communication ............................................................................................... 14 Behavior........................................................................................................... 14 Timing ............................................................................................................. 14 3.2 Target Peripherals Modeling................................................................................. 14 3.2.1 Target Modeling Objects .................................................................................. 15 3.2.2 Highlights Of SCML ........................................................................................ 17 3.1.1 3.1.2 3.1.3

CHAPTER 4: CASE STUDY .......................................... 21

4.1 4.2

Generic Interrupt Controller ................................................................................ 21 Architecture ......................................................................................................... 22 4.2.1 Hardware Interface .......................................................................................... 22 4.2.2 Software Interface. ........................................................................................... 24

CHAPTER 5: TLM MODEL OF IP ............................. 255.1 5.2 5.3 PV Model of IP.................................................................................................... 25 PV+T Model of IP .............................................................................................. 28 Test Bench ........................................................................................................... 32

CHAPTER 6: AUTOMATION OF MODELING REFINEMENT FROM PV TO PV+T MODEL ......... 356.1 6.2 6.3 6.4 Annotated Model ................................................................................................. 35 Standalone Timed Model ..................................................................................... 36 General Concept Of Refinement.......................................................................... 36 Proposed Algorithm for refinement from PV into PV+T ................................... 37

CHAPTER 7: CONCLUSIONS & FUTURE WORK ... 41 BIBLIOGRAPHY .......................................................... 43 APPENDIX A ................................................................ 45Output of Test Case ............................................................................................................ 45

APPENDIX B ................................................................. 51Case study of methodology................................................................................................. 51

LIST OF FIGURESFig 1.1 Fig 2.1 Fig 2.2 Fig 2.3 Fig 2.4 Fig 2.5 Fig 3.1 Fig 3.2 Fig 3.3 Fig 4.1 Fig 4.2 Fig 5.1 Fig 5.2 Fig 5.3 Fig 5.4 Fig 5.5 Fig 5.6 Fig 5.7 Fig 5.8 Fig 5.9 Fig 6.1 Fig 6.2 Transaction Level Models .................................................................................................. 2 SystemC language architecture........................................................................................... 6 SystemC components .......................................................................................................... 6 SystemC simulation kernel ................................................................................................. 7 Communication model ....................................................................................................... 9 TLM Platform Models in the ESL Design Flow ............................................................ 9 Methodology Approach .................................................................................................... 13 Generic TLM Target Pattern ........................................................................................... 15 Memory Modeling Objects............................................................................................... 16 Abstract View of IP ........................................................................................................... 21 Architecture of IP .............................................................................................................. 22 PV model of IP .................................................................................................................. 25 Internal Flow chart of method Signal_interrupt_changes ........................................... 26 PV model of access_vector_register ( ) call back function.......................................... 28 PV + T model of IP .......................................................................................................... 28 Non overlapping Interrupt request ................................................................................. 30 Overlapping of interrupt requests ................................................................................... 30 Flow chart for minimum latency calculation ................................................................. 31 PV+T model of access_vector_register ( ) call back function .................................... 32 Test bench for IP ............................................................................................................... 33 Annotated timing model ................................................................................................... 36 Standalone timing model .................................................................................................. 36

Fig 5.10 Flow chart for Test bench ................................................................................................ 33

CHAPTER 1INTRODUCTION1.1 Objective 1.2 Motivation 1.3 Related works (write about the works in market presently) 1.4 Methodology 1.5 Report organizationThis report includes the following: Chapter 2:--------------------(one line descriptions for each) Chapter 3: -------------------Chapter 4: ----------------------

CHAPTER 2BACKGROUND2.1 MSP430 (Basic Introduction) 2.1.1 2.1.2 2.1.3 Architecture Block diagram of MSP430 Pin description

2.2 ADC 2.3 Comparator 2.4 Any other components of MSP used in your project (eg timer/interrupts) 2.5 Sensors of MSP430 used (eg. Temp sensor) 2.6 Launchpad ( Diagram + description)

Note: in the topics 2.2, 2.3, 2.4, 2.5 etcwrite only about those components of MSP430 that you have used in your project. After including all components used, write about Launchpad and number the headings accordingly.

CHAPTER 3PROJECT DETAILS3.1 Block Diagram 3.2 Description- working of project 3.3 Schematic Diagram

CHAPTER 4HARDWARE4.1 ICs used in the Project 4.1.1 Pin diagram 4.1.2 Pin description 4.1.3 Utilisation 4.2 Other components used(4.2: Resistors (with ratings) 4.3 Capacitors (with ratings) 4.4 Transistors (with ratings) 4.5 Motors etc)

CHAPTER 5 SOFTWARE5.1 CCS Studio ( description using screen snapshots) 5.1.1 5.1.2 Write all steps of using it in points. Other specifications if any

5.2 Flowchart of Project ( in proper flowchart format) 5.3 Description of used instructions. 5.3.1 5.3.2 5.3.3 instruction 1 + explanation instruction 2+ explanation instruction 3+ explanation( do not write about all instructions, write only about the main and complex to understand instructions)

CHAPTER 6 RESULTS6.1 Prototype (Basic Explanation)6.1.1 6.1.2

Bread Board Prototype (with picture) PCB Prototype ( with picture)

6.2 Any other Comparison/ Results( eg tables, Observations etc.) 6.3

Costing Details ( costing of each and every component+ total cost)

CHAPTER 7CONCLUSIONS WORKS7.1 Innovation 7.2 Commercial Aspect 7.3 Applications of the Project 7.4 Future Enhancements

AND

FUTURE

BIBLIOGRAPHY Write about all the papers used in the proper IEEE format Write about the websites with their particular pages and links that were used in the course of the project.

APPENDIX A(Datasheets of ICs used)

Important Notes:1. There will be a total of 4 reports from one group making a project. One spiral bound report for Reema maam. This will be a combined report from both members of a group. Second will be a hard bound report for submission to the department. This will be a combined report from both members of a group. Third will be a hard bound report for submission during the time of submission during external viva. This will be an individual file. This will be from the first member of the group. Fourth will be a hard bound report for submission during the time of submission during external viva. This will be an individual file. This will be from the second member of the group. 2. All pages starting from chapter 1 must contain a header and footer. Header must be the title of the project on the top right corner of every page. Footer must be the page number in the bottom centre of every page. 3. New chapters should always begin from the odd numbered page.

4. The headings will be exactly in the same format and font size as given and explained in the previous pages for every chapter. They are Garamond, B, 28. The chapter subheading will be in Garamond, B, 18. Justified. 5. Each paragraph must begin after giving one tab. 6. References of papers used must be given in IEEE format including square brackets. [ ] 7. A CD also has to be submitted along with the report. The contents of the CD will be: Video of the working prototype Code in the .c file Entire report 8. After completing the report send a mail to Reema Maam for final approval before taking the print and binding. The mail id to be used is: reemaagarwal.ece@jecrc.ac.in The subject line of the mail must be: project report_roll no1,roll no2 9. Binding details are as given below: Black hard bound cover as front page with embossed text Butter paper of good quality Print of the inner page on a glossy sheet of paper. (color print) Acknowledgement Blank The chapter subheadings will be in Garamond , B, 14. The normal text will be in Times new Roman, 12,

Abstract Blank Contents The footer of all the initial pages will be page numbers in roman numbers on the bottom right corner of every page. The footer for the inner page will be: Jaipur Engineering College and Research Centre, Jaipur,2012 All Rights Reserved (Details of the contents on these pages is already given as samples)