Forging a Future in Memory - Hot Chips...express or implied, by estoppel or otherwise, to any such patents, trademarks, copyrights, or other intellectual pr operty rights. Designers

Forging a Future in Memory:

Ed Doller

New Technologies, New Markets, New Applications

Ed DollerV.P. Chief Memory Systems Architect

l lNon-Volatile Memory SeminarHot Chips ConferenceAugust 22, 2010Memorial AuditoriumStanford University

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© 2010 Micron Technology, Inc. | 1July 27, 2010

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Technology Lifecycle

EarlyMajority

LateMajority

Earlyd

I nnovators

AdoptersLaggards

NORNANDPCM


NOR Scaling

Tt

floating-gate

traps

tunnel oxide Silicon

traps

NOR R li bilit W it / ENOR (ETOX & NROM) S li NOR Reliability: Write / Erase Tox traps leading to TAT or de-trapping of trapped oxide electrons

NOR (ETOX & NROM) Scaling:3.2ev required to surmount Si-SiO2 barrier Æ Limits Cell Gate Length Scaling

2011 2012 201320092008 2010 2014 2015+

NOR65nm

45nm


NOR 45nm32nm ?

NAND Scaling

NAND Electron Scaling10000

30120Endurance & ECC Scaling

2007

2006

2004

1000

10000

ns 15

20

25

60

80

100

nce

(K)

CC

20122011

20102009

2008100

# E

lect

ron

5

10

15

20

40

60

Endu

ran EC

1020406080100

Litho Node

2011 2012 201320092008 2010 2014 2015+

0090 70 60 50 40 30 20

Litho Node

NAND4xnm

3xnm2

2011 2012 201320092008 2010 2014 2015+


2xnm

The 10’s

NOR / NAND / DRAM/ /

• The technology “Brick Wall”

• What can / should we do about it?

• What’s beyond the brick wall?

© 2010 Micron Technology, Inc. | 67/27/2010

y

Phase Change Memory• Storage

Ⴇ GST: Germanium-Antimony-Tellurium Chalcogenide glass

Ⴇ Cell states varying from amorphous (high resistance) to

Crystalline AmorphousႧ Cell states varying from amorphous (high resistance) to

crystalline (low resistance) states

• Read OperationႧ Measure resistance of the GSTႧ Measure resistance of the GST

• Write OperationႧ Heat GST via current flow (Joule effect)

Time at critical temperature determines cell state

IIႧ Time at critical temperature determines cell state

T Reset (amorphization)ture

T Reset (amorphization)

VV0.75

Crystal Amorphous

Ti

Tx

T ( p )

Set (crystallization)

TiTem

pera

t

x

Tm

( p )

Set (crystallization)0.25

0.50

Vth

Cur

rent

[mA

]


TimeTimeTTemperature during write

0.0 0.5 1.0 1.50.00

Voltage [V]

Memory CharacteristicsPCM Offers Attributes of RAM & NANDPCM Offers Attributes of RAM & NAND

Good

DRAM

Not

PCM

it ee ce d cyte cy n- tyal st

GoodNAND

BiAl

tera

bl

Wri

t eEn

dura

nc

Rea

Late

nc

Wri

tLa

tenc

Non

Vola

tilit

Theo

reti

caCo

s


T

Performance & Density ComparisonsCirca 2011, 45nm Silicon

Attributes DRAM PCM NAND HDDN V l il N Y Y YNon-Volatile No Yes Yes Yes

Idle Power ~100mW/GB ~1 mW/GB ~1 mW/GB ~10W

E / P Si N / 64B t N / 32B t Y / 256KB No / Erase / Page Size No / 64Byte No / 32Byte Yes / 256KB 512Byte

Write Bandwidth ~GB/sper die

50-100 MB/sper die

5-40 MB/sper die

~200MB/sper drive

Page Write Latency 20-50 ns ~1 us ~500 us ~5 ms

Page Read 20 50 ns ~70 ns ~25 µs ~5 msgLatency 20-50 ns ~70 ns ~25 µs ~5 ms

Endurance � 106 Æ 107 105 Æ 104 �

Maximum Density 4Gbit 4Gbit 64Gbit 2TByte

© 2010 Micron Technology, Inc. | 9

Maximum Density 4Gbit 4Gbit 64Gbit 2TByte

Theoretical Cost


Theoretical Chip Cost Factorsp

Silicon Cost Component SLC PCM DRAM SLC NANDDie Size Cell Size (F2) 5.5 6.0 5.0

4G Prod Example 1.0x 1.2x 1.0x

Wafer Total Process M k C t

~35 ~34 30Complexity Mask Count

300mm cost structure

1.2x 1.2x 1.0x

Theoretical Die Cost Summary 1 2x 1 4x 1 0xTheoretical Die Cost Summary 1.2x 1.4x 1.0x

• PCM will be cheaper than DRAM at lithography parity

• PCM scales to lower densities better than NAND

• PCM attributes can also save cost at system level


y

Bit Alterability


Bit AlterabilityRidiculously SimpleRidiculously Simple

I have a new mobile number: NAND PCM

1. Read 4KB from NAND w/ECC 1 Write 1 bit in PCM

mobile number:(555) 555-5554 NAND PCM

2. Write to RAM

3. Modify RAM

1. Write 1 bit in PCM

Much less bus traffic4. Locate new NAND page

5. Write new NAND page

6. Calculate & Write ECC

Much less bus traffic“Hidden” Power

Ridiculously Simple6. Calculate & Write ECC

7. Mark old NAND page “dirty”

8. Eventually erase NAND block


Endurance & Retention


ReliabilitySystem ImplicationsSystem Implications

High

emen

ts

tions

olut

ions

Medium

on R

equi

re

Si S

olut

Read Endurance Retention

Syst

em S

o

Low

Appl

icat

io

Read Endurance Retention

Endurance Retention Read S

72nm 55nm 35nm 25nm

Multi-Media(MP3, USB, Memory Card)

Wireless(Code Execution, Data Storage)

Computing(Cache, SSD)

SLC / MLC


EnduranceScalabilityScalability

1 000 000PCM

800,000

1,000,000

600,000

20X

rase

Cyc

les

200 000

400,000NAND

Er

0

200,000


2010 2012 2014 2016Source: My Estimates

Data RetentionHistorical ViewHistorical View

“Endurance is a measure of the ability of a nonvolatile

10 yr at “ low cycles”1 yr at data sheet200k year?

memory device to meet its data sheet specifications as a function of accumulated nonvolatile data rewrites or program/erase cycles.”

y10 year

(with sticker)

200 ka 1971 1998

p g / y

2006


News Flash: PCM Retention is NOT a function of endurance

EnduranceSSD: Fast Growing SegmentSSD: Fast Growing Segment

$4

$5

$2

$3

Billi

ons

$1

$2B

$0

2009 2010 2011 2012 2013


Source: iSupply, Dec 2009

Enterprise Notebook

InterfacesGetting Faster

8

Getting Faster

6

4

GB/s

0

2

0SATA 1 SATA 2 SATA 3 SAS PCIe 1 PCIe 2 PCIe 3


Note: PCIe x8

4GB/s at 90/10 Read/Write Equates to 34TB’s per day

System SolutionsEndurance vs DensityEndurance vs. DensityPCIe2

1600acity

90/10

800

1200

r�64GB�Capa

nsity

90/10

400

800

ual�G

B's�for

NAND

20X

De

5 yrs

0

Actu

PCM

NAND5 yrs


2010 2012 2014 2016

Latency


Performance Bandwidth vs. LatencyBandwidth vs. Latency

Bandwidth“Add More”

Latency

0 60 h Æ 10 4 0 60 h Æ 3 5

Latency“Add Something Faster”


0-60mph Æ 10.4s$20,000

0-60mph Æ 3.5s$200,000

Application to ComputeApproach is ChangingApproach is Changing

CPU RAM DI SK TAPEDI SK

ns / GB ms / TB s / PB

Bandwidth Improvement

Latency Improvement or

CPU RAM DI SK TAPESSD


ns / GB ms / TB s / PBus / GBAll logos or trademarks are the property of their respective owners

PerformanceRelatively SpeakingRelatively Speaking

PCM If R d L t 1 dPCM

SSD

I f Random Latency = 1 day

Then latency = 17 daysSSD

HDD Then… latency = 9 years

Then… latency = 17 days

SCM PCM

HDD

Then… latency = 30 min

Then… latency 9 years

Storage Class PCM can perform > 800 database searches in the time it takes an SSD to do 1


base searches in the time it takes an SSD to do 1

LatencyValue goes up with information growthValue goes up with information growth

“… every 100ms of latency cost them 1% in sales”Source: http: / /highscalability.com

“…an extra 500ms in search pagegeneration time dropped traffic by 20% ”g pp y

Source: http: / / royal.pingdom.com

“… a broker could lose $4 Million Dollars permillisecond if their electronic trading platform ismillisecond if their electronic trading platform is5ms behind the competition”

Source: http:/ / highscalability.com

CPU RAM DI SK TAPESSDPCM


ns / GB ms / TB s / PBus / GBns / GB

July 27, 2010

All logos or trademarks are the property of their respective owners

LatencyStill Not Convinced?Still Not Convinced?


PCMIndustry Demands Will Drive ChangeIndustry Demands Will Drive Change

Bit AlterableRidiculously

Simple

EnduranceHigh ReliabilityUsage ModelsSimple Usage Models

Latency RetentionLatencyI nstant Access

RetentionNot a functionOf Endurance


July 27, 2010

Documents

Forging a Future in Memory - Hot Chips...express or implied, by estoppel or otherwise, to any such patents, trademarks, copyrights, or other intellectual pr operty rights. Designers