for Blue Gene/Q - Argonne National Laboratory · for Blue Gene/Q Note: This document and the information it contains are provided on an as-is basis. There is no plan for providing

A2 Processor

User’s Manual

for Blue Gene/QNote: This document and the information it contains are provided on an as-is basis. There is no plan for providing for future updates and corrections to this document.

October 23, 2012 Version 1.3

Title Page

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Version 1.3October 23, 2012

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User’s Manual

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Contents

List of Figures ............................................................................................................... 21

List of Tables ................................................................................................................. 23

Revision Log ................................................................................................................. 29

About This Book .......................................................................................................... 31Who Should Use This Book .................................................................................................................. 31How to Use This Book ........................................................................................................................... 31Notation ................................................................................................................................................. 32Related Publications ............................................................................................................................. 33

List of Acronyms and Abbreviations .......................................................................... 35

1. Overview .................................................................................................................... 451.1 A2 Core Key Design Fundamentals ................................................................................................ 451.2 A2 Core Features ............................................................................................................................ 461.3 The A2 Core as a Power ISA Implementation ................................................................................ 49

1.3.1 Embedded Hypervisor ........................................................................................................... 491.4 A2 Core Organization ...................................................................................................................... 49

1.4.1 Instruction Unit ....................................................................................................................... 501.4.2 Execution Unit ....................................................................................................................... 511.4.3 Instruction and Data Cache Controllers ................................................................................. 51

1.4.3.1 Instruction Cache Controller ........................................................................................... 511.4.3.2 Data Cache Controller .................................................................................................... 51

1.4.4 Memory Management Unit (MMU) ........................................................................................ 521.4.5 Timers .................................................................................................................................... 541.4.6 Debug Facilities ..................................................................................................................... 54

1.4.6.1 Debug Modes ................................................................................................................. 541.4.6.2 Development Tool Support ............................................................................................. 55

1.4.7 Floating-Point Unit Organization ............................................................................................ 551.4.7.1 Arithmetic and Load/Store Pipelines .............................................................................. 56

1.4.8 IEEE 754 and Architectural Compliance ............................................................................... 561.4.8.1 IEEE 754 Compliance .................................................................................................... 57

1.4.9 Floating-Point Unit Implementation ....................................................................................... 571.4.9.1 Reciprocal Estimates ...................................................................................................... 571.4.9.2 Denormalized B Operands ............................................................................................. 571.4.9.3 Non-IEEE mode ............................................................................................................. 57

1.4.10 Floating-Point Unit Interfaces .............................................................................................. 571.4.10.1 A2 Processor Core Interface ........................................................................................ 571.4.10.2 Clock and Power Management Interface ..................................................................... 58

1.5 Core Interfaces ................................................................................................................................ 581.5.1 System Interface .................................................................................................................... 581.5.2 Auxiliary Execution Unit (AXU) Port ...................................................................................... 591.5.3 JTAG Port .............................................................................................................................. 59

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2. CPU Programming Model ......................................................................................... 612.1 Logical Partitioning .......................................................................................................................... 61

2.1.1 Overview ................................................................................................................................ 612.2 Storage Addressing ......................................................................................................................... 62

2.2.1 Storage Operands .................................................................................................................. 622.2.2 Effective Address Calculation ................................................................................................ 64

2.2.2.1 Data Storage Addressing Modes .................................................................................... 652.2.2.2 Instruction Storage Addressing Modes ........................................................................... 65

2.2.3 Byte Ordering ......................................................................................................................... 662.2.3.1 Structure Mapping Examples ......................................................................................... 662.2.3.2 Instruction Byte Ordering ................................................................................................ 672.2.3.3 Data Byte Ordering ......................................................................................................... 682.2.3.4 Byte-Reverse Instructions .............................................................................................. 69

2.3 Multithreading .................................................................................................................................. 702.3.1 Thread Identification .............................................................................................................. 70

2.3.1.1 Thread Identification Register (TIR) ............................................................................... 702.3.1.2 Processor Identification Register (PIR) .......................................................................... 702.3.1.3 Guest Processor Identification Register (GPIR) ............................................................. 71

2.3.2 Thread Run State ................................................................................................................... 712.3.2.1 Thread Stop I/O Pin ........................................................................................................ 712.3.2.2 Thread Control and Status Register (THRCTL) ............................................................. 712.3.2.3 Core Configuration Register 0 (CCR0) ........................................................................... 722.3.2.4 Thread Enable Register (TENS, TENC) ......................................................................... 722.3.2.5 Thread Enable Status Register (TENSR) ....................................................................... 73

2.3.3 Wake On Interrupt .................................................................................................................. 742.3.3.1 Core Configuration Register 1 (CCR1) ........................................................................... 74

2.3.4 Thread Priority ....................................................................................................................... 752.3.4.1 Program Priority Register (PPR32) ................................................................................ 752.3.4.2 Instruction Unit Configuration Register 1 (IUCR1) .......................................................... 77

2.3.5 Resources Shared between Threads .................................................................................... 772.3.6 Shared Resources ................................................................................................................. 77

2.3.6.1 Accessing Shared Resources ........................................................................................ 782.3.7 Duplicated Resources ............................................................................................................ 782.3.8 Pipeline Sharing ..................................................................................................................... 79

2.3.8.1 Instruction Cache ............................................................................................................ 802.3.8.2 Instruction Buffer and Decode Dependency ................................................................... 802.3.8.3 Instruction Issue ............................................................................................................. 802.3.8.4 Ram Unit ......................................................................................................................... 812.3.8.5 Microcode Unit ................................................................................................................ 822.3.8.6 Integer Unit ..................................................................................................................... 82

2.4 Registers ......................................................................................................................................... 822.4.1 Register Mapping ................................................................................................................... 842.4.2 Register Types ....................................................................................................................... 84

2.4.2.1 General Purpose Registers ............................................................................................ 842.4.2.2 Special Purpose Registers ............................................................................................. 842.4.2.3 Condition Register .......................................................................................................... 852.4.2.4 Machine State Register .................................................................................................. 85

2.5 32-Bit Mode ..................................................................................................................................... 852.5.1 64-Bit Specific Instructions ..................................................................................................... 852.5.2 32-Bit Instruction Selection .................................................................................................... 85

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2.6 Instruction Categories ..................................................................................................................... 862.7 Instruction Classes .......................................................................................................................... 87

2.7.1 Defined Instruction Class ....................................................................................................... 872.7.2 Illegal Instruction Class .......................................................................................................... 882.7.3 Reserved Instruction Class .................................................................................................... 88

2.8 Implemented Instruction Set Summary ........................................................................................... 882.8.1 Integer Instructions ................................................................................................................ 89

2.8.1.1 Integer Storage Access Instructions ............................................................................... 892.8.1.2 Integer Arithmetic Instructions ........................................................................................ 912.8.1.3 Integer Logical Instructions ............................................................................................ 922.8.1.4 Integer Compare Instructions ......................................................................................... 922.8.1.5 Integer Trap Instructions ................................................................................................ 922.8.1.6 Integer Rotate Instructions ............................................................................................. 922.8.1.7 Integer Shift Instructions ................................................................................................. 932.8.1.8 Integer Population Count Instructions ............................................................................ 932.8.1.9 Integer Select Instruction ................................................................................................ 93

2.8.2 Branch Instructions ................................................................................................................ 942.8.3 Processor Control Instructions .............................................................................................. 94

2.8.3.1 Condition Register Logical Instructions .......................................................................... 942.8.3.2 Register Management Instructions ................................................................................. 952.8.3.3 System Linkage Instructions .......................................................................................... 952.8.3.4 Processor Control Instructions ....................................................................................... 95

2.8.4 Storage Control Instructions .................................................................................................. 952.8.4.1 Cache Management Instructions .................................................................................... 962.8.4.2 TLB Management Instructions ....................................................................................... 962.8.4.3 Processor Synchronization Instruction ........................................................................... 972.8.4.4 Load and Reserve and Store Conditional Instructions ................................................... 972.8.4.5 Storage Synchronization Instructions ............................................................................. 972.8.4.6 Wait Instruction ............................................................................................................... 98

2.8.5 Initiate Coprocessor Instructions ........................................................................................... 982.8.5.1 Cache Initialization Instructions ...................................................................................... 98

2.9 Branch Processing .......................................................................................................................... 992.9.1 Branch Addressing ................................................................................................................ 992.9.2 Branch Instruction BI Field .................................................................................................... 992.9.3 Branch Instruction BO Field ................................................................................................... 992.9.4 Branch Prediction ................................................................................................................ 100

2.9.4.1 Branch Decoder ........................................................................................................... 1002.9.4.2 Branch Direction Prediction .......................................................................................... 1012.9.4.3 Branch Prioritization ..................................................................................................... 1042.9.4.4 Branch Target Prediction .............................................................................................. 1042.9.4.5 Redirection ................................................................................................................... 105

2.9.5 Branch Control Registers .................................................................................................... 1052.9.5.1 Link Register (LR) ........................................................................................................ 1052.9.5.2 Count Register (CTR) ................................................................................................... 1062.9.5.3 Condition Register (CR) ............................................................................................... 107

2.10 Integer Processing ...................................................................................................................... 1102.10.1 General Purpose Registers (GPRs) .................................................................................. 1102.10.2 Integer Exception Register (XER) ..................................................................................... 110

2.10.2.1 Summary Overflow (SO) Field ................................................................................... 1122.10.2.2 Overflow (OV) Field .................................................................................................... 112


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2.10.2.3 Carry (CA) Field .......................................................................................................... 1122.10.2.4 Transfer Byte Count (TBC) Field ................................................................................ 113

2.11 Processor Control ........................................................................................................................ 1132.11.1 Special Purpose Registers General (SPRG0–SPRG8) ..................................................... 1142.11.2 External Process ID Load Context (EPLC) Register .......................................................... 1192.11.3 External Process ID Store Context (EPSC) Register ......................................................... 119

2.12 Privileged Modes ......................................................................................................................... 1202.12.1 Privileged Instructions ........................................................................................................ 121

2.12.1.1 Cache Locking Instructions ........................................................................................ 1212.12.2 Privileged SPRs ................................................................................................................. 122

2.13 Speculative Accesses ................................................................................................................. 1222.14 Synchronization ........................................................................................................................... 122

2.14.1 Context Synchronization .................................................................................................... 1222.14.2 Execution Synchronization ................................................................................................. 1242.14.3 Storage Ordering and Synchronization .............................................................................. 124

2.15 Software Transactional Memory Acceleration ............................................................................. 1252.15.1 Summary ............................................................................................................................ 1252.15.2 Implementation .................................................................................................................. 125

2.15.2.1 L1 D-Cache ................................................................................................................ 1262.15.3 Watch Operation Ordering Requirements .......................................................................... 1262.15.4 Impact on Existing Software .............................................................................................. 126

3. FU Programming Model .......................................................................................... 1273.1 Storage Addressing ....................................................................................................................... 127

3.1.1 Storage Operands ................................................................................................................ 1273.1.2 Effective Address Calculation .............................................................................................. 1283.1.3 Data Storage Addressing Modes ......................................................................................... 128

3.2 Floating-Point Exceptions .............................................................................................................. 1293.3 Floating-Point Registers ................................................................................................................ 129

3.3.1 Register Types ..................................................................................................................... 1303.3.1.1 Floating-Point Registers (FPR0–FPR31) ..................................................................... 1303.3.1.2 Floating-Point Status and Control Register (FPSCR) .................................................. 131

3.4 Floating-Point Data Formats ......................................................................................................... 1333.4.1 Value Representation .......................................................................................................... 1343.4.2 Binary Floating-Point Numbers ............................................................................................ 135

3.4.2.1 Normalized Numbers .................................................................................................... 1353.4.2.2 Denormalized Numbers ................................................................................................ 1363.4.2.3 Zero Values .................................................................................................................. 136

3.4.3 Infinities ................................................................................................................................ 1363.4.3.1 Not a Numbers ............................................................................................................. 136

3.4.4 Sign of Result ....................................................................................................................... 1373.4.5 Normalization and Denormalization ..................................................................................... 1383.4.6 Data Handling and Precision ............................................................................................... 1383.4.7 Rounding .............................................................................................................................. 139

3.5 Floating-Point Execution Models ................................................................................................... 1403.5.1 Execution Model for IEEE Operations ................................................................................. 1413.5.2 Execution Model for Multiply-Add Type Instructions ............................................................ 143

3.6 Floating-Point Instructions ............................................................................................................. 1433.6.1 Instructions by Category ...................................................................................................... 144

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3.6.2 Load and Store Instructions ................................................................................................. 1453.6.3 Floating-Point Store Instructions ......................................................................................... 1463.6.4 Floating-Point Move Instructions ......................................................................................... 1483.6.5 Floating-Point Arithmetic Instructions .................................................................................. 148

3.6.5.1 Floating-Point Multiply-Add Instructions ....................................................................... 1493.6.6 Floating-Point Rounding and Conversion Instructions ........................................................ 1493.6.7 Floating-Point Compare Instructions ................................................................................... 1503.6.8 Floating-Point Status and Control Register Instructions ...................................................... 151

4. Initialization ............................................................................................................. 1534.1 Core Reset .................................................................................................................................... 1534.2 A2 Core State After Reset ............................................................................................................. 1544.3 Software Initiated Reset Requests ................................................................................................ 160

4.3.1 Software Reset Requests .................................................................................................... 1604.3.1.1 From Debug ................................................................................................................. 1614.3.1.2 From Watchdog Timer .................................................................................................. 161

4.3.2 Reset Request Status .......................................................................................................... 1614.3.2.1 Debug Facility Reset Status ......................................................................................... 1624.3.2.2 Timer Facility Reset Status .......................................................................................... 162

4.4 Initialization Software Requirements ............................................................................................. 163

5. Instruction and Data Caches ................................................................................. 1695.1 Data Cache Array Organization and Operation ............................................................................ 1695.2 Instruction Cache Array Organization and Operation ................................................................... 1705.3 Cache Line Replacement Policy ................................................................................................... 1705.4 Instruction Cache Controller .......................................................................................................... 170

5.4.1 ICC Operations .................................................................................................................... 1715.4.2 Instruction Cache Coherency .............................................................................................. 171

5.4.2.1 Self-Modifying Code ..................................................................................................... 1725.4.2.2 Instruction Cache Synonyms ........................................................................................ 172

5.4.3 Instruction Cache Control and Debug ................................................................................. 1725.4.3.1 Instruction Cache Management and Debug Instruction Summary ............................... 1725.4.3.2 Instruction Cache Parity Operations ............................................................................. 1735.4.3.3 Simulating Instruction Cache Parity Errors for Software Testing ................................. 173

5.5 Data Cache Controller ................................................................................................................... 1735.5.1 DCC Operations .................................................................................................................. 174

5.5.1.1 Load and Store Alignment ............................................................................................ 1755.5.1.2 Load Operations ........................................................................................................... 1755.5.1.3 Store Operations .......................................................................................................... 1765.5.1.4 Data Read and Instruction Fetch Interface Requests .................................................. 1765.5.1.5 Data Write Interface Requests ..................................................................................... 1765.5.1.6 Storage Access Ordering ............................................................................................. 177

5.5.2 Data Cache Coherency ....................................................................................................... 1775.5.3 Data Cache Control ............................................................................................................. 177

5.5.3.1 Data Cache Management Instruction Summary .......................................................... 1775.5.3.2 dcbt and dcbtst Operation ............................................................................................ 1785.5.3.3 Cache Locking Mechanisms ........................................................................................ 1795.5.3.4 Data Cache Parity Operations ...................................................................................... 1835.5.3.5 Simulating Data Cache Parity Errors for Software Testing .......................................... 183


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5.5.3.6 Data Cache Disable ...................................................................................................... 183

6. Memory Management .............................................................................................. 1856.1 MMU Overview .............................................................................................................................. 185

6.1.1 Support for Power ISA MMU Architecture ........................................................................... 1866.2 Page Identification ......................................................................................................................... 186

6.2.1 Virtual Address Formation ................................................................................................... 1876.2.2 Address Space Identifier Convention ................................................................................... 1876.2.3 Exclusion Range (X-bit) Operation ...................................................................................... 1886.2.4 TLB Match Process .............................................................................................................. 189

6.3 Address Translation ...................................................................................................................... 1916.4 Access Control .............................................................................................................................. 193

6.4.1 Execute Access ................................................................................................................... 1936.4.2 Write Access ........................................................................................................................ 1936.4.3 Read Access ........................................................................................................................ 1946.4.4 Access Control Applied to Cache Management Instructions ............................................... 194

6.5 Storage Attributes .......................................................................................................................... 1956.5.1 Write-Through (W) ............................................................................................................... 1966.5.2 Caching Inhibited (I) ............................................................................................................. 1966.5.3 Memory Coherence Required (M) ....................................................................................... 1966.5.4 Guarded (G) ......................................................................................................................... 1966.5.5 Endian (E) ............................................................................................................................ 1976.5.6 User-Definable (U0–U3) ...................................................................................................... 1976.5.7 Supported Storage Attribute Combinations ......................................................................... 1976.5.8 Aliasing ................................................................................................................................ 197

6.6 Translation Lookaside Buffer ......................................................................................................... 1986.7 Effective to Real Address Translation Arrays ................................................................................ 203

6.7.1 ERAT Context Synchronization ........................................................................................... 2046.7.2 ERAT Reset Behavior .......................................................................................................... 2056.7.3 Atomic Update of ERAT Entries ........................................................................................... 2056.7.4 ERAT LRU Round-Robin Replacement Mode ..................................................................... 2056.7.5 ERAT LRU Replacement Watermark .................................................................................. 2066.7.6 ERAT (TLB Lookaside Information) Coherency and Back-Invalidation ............................... 2066.7.7 ERAT External PID (EPID) Context and Instruction Dependencies .................................... 208

6.8 Logical to Real Address Translation Array (Category E.HV.LRAT) .............................................. 2096.9 TLB Management Instructions (Architected) ................................................................................. 212

6.9.1 TLB Read and Write Instructions (tlbre and tlbwe) ............................................................. 2136.9.2 TLB Search Instruction (tlbsx[.]) ........................................................................................ 2156.9.3 TLB Search and Reserve Instruction (tlbsrx.) .................................................................... 2156.9.4 TLB Invalidate Virtual Address (Indexed) Instruction (tlbivax) ............................................ 2166.9.5 TLB Invalidate Local (Indexed) Instruction (tlbilx) ............................................................... 2186.9.6 TLB Sync Instruction (tlbsync) ............................................................................................ 218

6.10 ERAT Management Instructions (Non-Architected) .................................................................... 2196.10.1 ERAT Read and Write Instructions (eratre and eratwe) ................................................... 2196.10.2 ERAT Search Instruction (eratsx[.]) ................................................................................. 2206.10.3 ERAT Invalidate Virtual Address (Indexed) Instruction (erativax) ..................................... 2216.10.4 ERAT Invalidate Local (Indexed) Instruction (eratilx) ........................................................ 224

6.11 32-Bit Mode Memory Management Behavior .............................................................................. 2246.11.1 32-Bit Mode TLB Read and Write Instructions (tlbre and tlbwe) ...................................... 225

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6.11.2 32-Bit Mode TLB Search Instruction (tlbsx[.]) ................................................................. 2256.11.3 32-Bit Mode TLB Search and Reserve Instruction (tlbsrx.) ............................................. 2256.11.4 32-Bit Mode TLB Invalidate Virtual Address (Indexed) Instruction (tlbivax) ..................... 2266.11.5 32-Bit Mode TLB Invalidate Local (Indexed) Instruction (tlbilx) ........................................ 2266.11.6 32-Bit Mode TLB Sync Instruction (tlbsync) ..................................................................... 2266.11.7 32-Bit Mode ERAT Read and Write Instructions (eratre and eratwe) .............................. 2266.11.8 32-Bit Mode ERAT Search Instruction (eratsx[.]) ............................................................ 2276.11.9 32-Bit Mode ERAT Invalidate Virtual Address (Indexed) Instruction (erativax) ................ 2276.11.10 32-Bit Mode ERAT Invalidate Local (Indexed) Instruction (eratilx) ................................. 228

6.12 Page Reference and Change Status Management .................................................................... 2286.13 TLB and ERAT Parity Operations ............................................................................................... 229

6.13.1 Parity Errors Generated from tlbre or eratre .................................................................... 2306.13.2 Simulating TLB and ERAT Parity Errors for Software Testing .......................................... 231

6.14 ERAT-Only Mode Operation ....................................................................................................... 2326.15 TLB Reservations and TLB Write Conditional (Category E.TWC) .............................................. 2326.16 Hardware Page Table Walking (Category E.PT) ........................................................................ 237

6.16.1 Searching the TLB for Direct and Indirect Entries ............................................................. 2376.16.2 Indirect TLB Entry Page and Sub-Page Sizes ................................................................... 2386.16.3 Hardware Page Table Entry Format .................................................................................. 2396.16.4 Calculation of Hardware Page Table Entry Real Address ................................................. 2406.16.5 Hardware Page Table Errors and Exceptions ................................................................... 2416.16.6 Hardware Page Table Storage Control Attributes ............................................................. 2416.16.7 TLB Update After Hardware Page Table Translation ........................................................ 242

6.17 Storage Control Registers (Architected) ..................................................................................... 2446.17.1 Process ID Register (PID) ................................................................................................. 2446.17.2 Logical Partition ID Register (LPIDR) ................................................................................ 2456.17.3 External PID Load Context (EPLC) Register ..................................................................... 2466.17.4 External PID Store Context (EPSC) Register .................................................................... 2476.17.5 MMU Assist Register 0 (MAS0) ......................................................................................... 2486.17.6 MMU Assist Register 1 (MAS1) ......................................................................................... 2496.17.7 MMU Assist Register 2 (MAS2) ......................................................................................... 2516.17.8 MMU Assist Register 2 Upper (MAS2U) ........................................................................... 2526.17.9 MMU Assist Register 3 (MAS3) ......................................................................................... 2536.17.10 MMU Assist Register 4 (MAS4) ....................................................................................... 2556.17.11 MMU Assist Register 5 (MAS5) ....................................................................................... 2566.17.12 MMU Assist Register 6 (MAS6) ....................................................................................... 2576.17.13 MMU Assist Register 7 (MAS7) ....................................................................................... 2586.17.14 MMU Assist Register 8 (MAS8) ....................................................................................... 2596.17.15 MAS0_MAS1 Register ..................................................................................................... 2606.17.16 MAS5_MAS6 Register ..................................................................................................... 2616.17.17 MAS7_MAS3 Register ..................................................................................................... 2626.17.18 MAS8_MAS1 Register ..................................................................................................... 2636.17.19 MMU Configuration Register (MMUCFG) ........................................................................ 2646.17.20 MMU Control and Status Register 0 (MMUCSR0) .......................................................... 2656.17.21 TLB 0 Configuration Register (TLB0CFG) ....................................................................... 2666.17.22 TLB 0 Page Size Register (TLB0PS) .............................................................................. 2686.17.23 LRAT Configuration Register (LRATCFG) ...................................................................... 2696.17.24 LRAT Page Size Register (LRATPS) .............................................................................. 2706.17.25 Embedded Page Table Configuration Register (EPTCFG) ............................................. 2726.17.26 Logical Page Exception Register (LPER) ........................................................................ 273


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6.17.27 Logical Page Exception Register Upper (LPERU) ........................................................... 2746.17.28 MAS Register Update Summary ...................................................................................... 275

6.18 Storage Control Registers (Non-Architected) .............................................................................. 2776.18.1 Memory Management Unit Control Register 0 (MMUCR0) ............................................... 2776.18.2 Memory Management Unit Control Register 1 (MMUCR1) ............................................... 2806.18.3 Memory Management Unit Control Register 2 (MMUCR2) ............................................... 2876.18.4 Memory Management Unit Control Register 3 (MMUCR3) ............................................... 290

7. CPU Interrupts and Exceptions .............................................................................. 2937.1 Overview ....................................................................................................................................... 2937.2 Directed Interrupts ......................................................................................................................... 2937.3 Interrupt Classes ........................................................................................................................... 294

7.3.1 Asynchronous Interrupts ...................................................................................................... 2947.3.2 Synchronous Interrupts ........................................................................................................ 294

7.3.2.1 Synchronous, Precise Interrupts .................................................................................. 2947.3.2.2 Synchronous, Imprecise Interrupts ............................................................................... 295

7.3.3 Critical and Noncritical Interrupts ......................................................................................... 2967.3.4 Machine Check Interrupts .................................................................................................... 296

7.4 Interrupt Processing ...................................................................................................................... 2977.4.1 Partially Executed Instructions ............................................................................................. 299

7.5 Interrupt Processing Registers ...................................................................................................... 3007.5.1 Register Mapping ................................................................................................................. 3017.5.2 Machine State Register (MSR) ............................................................................................ 3017.5.3 Machine State Register Protect (MSRP) ............................................................................. 3037.5.4 Embedded Processor Control Register (EPCR) .................................................................. 3047.5.5 Save/Restore Register 0 (SRR0) ......................................................................................... 3057.5.6 Save/Restore Register 1 (SRR1) ......................................................................................... 3067.5.7 Guest Save/Restore Register 0 (GSRR0) ........................................................................... 3087.5.8 Guest Save/Restore Register 1 (GSRR1) ........................................................................... 3087.5.9 Critical Save/Restore Register 0 (CSRR0) .......................................................................... 3107.5.10 Critical Save/Restore Register 1 (CSRR1) ........................................................................ 3117.5.11 Machine Check Save/Restore Register 0 (MCSRR0) ....................................................... 3137.5.12 Machine Check Save/Restore Register 1 (MCSRR1) ....................................................... 3137.5.13 Data Exception Address Register (DEAR) ......................................................................... 3157.5.14 Guest Data Exception Address Register (GDEAR) ........................................................... 3167.5.15 Interrupt Vector Prefix Register (IVPR) .............................................................................. 3187.5.16 Guest Interrupt Vector Prefix Register (GIVPR) ................................................................ 3187.5.17 Exception Syndrome Register (ESR) ................................................................................. 3187.5.18 Guest Exception Syndrome Register (GESR) ................................................................... 3207.5.19 Machine Check Status Register (MCSR) ........................................................................... 322

7.6 Interrupt Definitions ....................................................................................................................... 3237.6.1 Critical Input Interrupt ........................................................................................................... 3267.6.2 Machine Check Interrupt ...................................................................................................... 327

7.6.2.1 Machine Check Status Register (MCSR) ..................................................................... 3297.6.3 Data Storage Interrupt ......................................................................................................... 3307.6.4 Instruction Storage Interrupt ................................................................................................ 3347.6.5 External Input Interrupt ........................................................................................................ 3367.6.6 Alignment Interrupt ............................................................................................................... 3377.6.7 Program Interrupt ................................................................................................................. 338

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7.6.8 Floating-Point Unavailable Interrupt .................................................................................... 3427.6.9 System Call Interrupt ........................................................................................................... 3427.6.10 Auxiliary Processor Unavailable Interrupt .......................................................................... 3437.6.11 Decrementer Interrupt ....................................................................................................... 3437.6.12 Fixed-Interval Timer Interrupt ............................................................................................ 3447.6.13 Watchdog Timer Interrupt .................................................................................................. 3447.6.14 Data TLB Error Interrupt .................................................................................................... 3457.6.15 Instruction TLB Error Interrupt ........................................................................................... 3467.6.16 Vector Unavailable Interrupt .............................................................................................. 3477.6.17 Debug Interrupt .................................................................................................................. 3477.6.18 Processor Doorbell Interrupt .............................................................................................. 3517.6.19 Processor Doorbell Critical Interrupt .................................................................................. 3527.6.20 Guest Processor Doorbell Interrupt ................................................................................... 3527.6.21 Guest Processor Doorbell Critical Interrupt ....................................................................... 3537.6.22 Guest Processor Doorbell Machine Check Interrupt ......................................................... 3537.6.23 Embedded Hypervisor System Call Interrupt .................................................................... 3547.6.24 Embedded Hypervisor Privilege Interrupt .......................................................................... 3547.6.25 LRAT Error Interrupt .......................................................................................................... 3557.6.26 User Decrementer Interrupt ............................................................................................... 3567.6.27 Performance Monitor Interrupt ........................................................................................... 356

7.7 Processor Messages ..................................................................................................................... 3577.7.1 Processor Message Handling and Filtering ......................................................................... 3577.7.2 Doorbell Message Filtering .................................................................................................. 3587.7.3 Doorbell Critical Message Filtering ...................................................................................... 3597.7.4 Guest Doorbell Message Filtering ....................................................................................... 3607.7.5 Guest Doorbell Critical Message Filtering ........................................................................... 3607.7.6 Guest Doorbell Machine Check Message Filtering ............................................................. 361

7.8 Interrupt Ordering and Masking .................................................................................................... 3627.8.1 Interrupt Ordering Software Requirements .......................................................................... 3637.8.2 Interrupt Order ..................................................................................................................... 364

7.9 Exception Priorities ....................................................................................................................... 3657.9.1 Exception Priorities for Integer Load, Store, and Cache Management Instructions ............ 3667.9.2 Exception Priorities for Floating-Point Load and Store Instructions .................................... 3677.9.3 Exception Priorities for Floating-Point Instructions (Other) .................................................. 3677.9.4 Exception Priorities for Privileged Instructions .................................................................... 3687.9.5 Exception Priorities for Trap Instructions ............................................................................. 3687.9.6 Exception Priorities for System Call Instruction ................................................................... 3687.9.7 Exception Priorities for Branch Instructions ......................................................................... 3697.9.8 Exception Priorities for Return From Interrupt Instructions .................................................. 3697.9.9 Exception Priorities for Reserved Instructions ..................................................................... 3697.9.10 Exception Priorities for All Other Instructions .................................................................... 370

8. FU Interrupts and Exceptions ................................................................................ 3718.1 Floating-Point Exceptions ............................................................................................................. 3718.2 Exceptions List .............................................................................................................................. 3728.3 Floating-Point Interrupts ................................................................................................................ 375

8.3.1 Floating-Point Unavailable Interrupt .................................................................................... 3758.3.2 Floating-Point Assist Interrupt ............................................................................................. 375

8.4 Floating-Point Exception Behavior ................................................................................................ 375


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8.4.1 Invalid Operation Exception ................................................................................................. 3758.4.1.1 Action ............................................................................................................................ 376

8.4.2 Zero Divide Exception .......................................................................................................... 3778.4.2.1 Action ............................................................................................................................ 377

8.4.3 Overflow Exception .............................................................................................................. 3788.4.3.1 Action ............................................................................................................................ 378

8.4.4 Underflow Exception ............................................................................................................ 3798.4.4.1 Action ............................................................................................................................ 379

8.4.5 Inexact Exception ................................................................................................................. 3808.4.5.1 Action ............................................................................................................................ 380

8.5 Exception Priorities for Floating-Point Load and Store Instructions .............................................. 3808.6 Exception Priorities for Other Floating-Point Instructions .............................................................. 3818.7 QNaN ............................................................................................................................................ 3818.8 Updating FPRs on Exceptions ...................................................................................................... 3828.9 Floating-Point Status and Control Register (FPSCR) ................................................................... 3828.10 Updating the Condition Register ................................................................................................. 385

8.10.1 Condition Register (CR) ..................................................................................................... 3858.10.2 Updating CR Fields ............................................................................................................ 3868.10.3 Generation of QNaN Results ............................................................................................. 386

9. Timer Facilities ........................................................................................................ 3879.1 Time Base ..................................................................................................................................... 388

9.1.1 Reading the Time Base ....................................................................................................... 3899.1.2 Writing the Time Base .......................................................................................................... 389

9.2 Decrementer (DEC) ....................................................................................................................... 3899.3 User Decrementer (UDEC) ........................................................................................................... 3919.4 Fixed Interval Timer (FIT) .............................................................................................................. 3929.5 Watchdog Timer ............................................................................................................................ 3939.6 Timer Control Register (TCR) ....................................................................................................... 3959.7 Timer Status Register (TSR) ......................................................................................................... 3979.8 Freezing the Timer Facilities ......................................................................................................... 3979.9 Selection of the Timer Clock Source ............................................................................................. 3989.10 Synchronizing Timers Across Multiple Cores .............................................................................. 398

10. Debug Facilities ..................................................................................................... 39910.1 Implications of Hypervisor on Debug Controls ............................................................................ 39910.2 Support for Development Tools ................................................................................................... 39910.3 Debug Modes .............................................................................................................................. 399

10.3.1 Internal Debug Mode ......................................................................................................... 40010.3.2 External Debug Mode ........................................................................................................ 40010.3.3 Trace Debug Mode ............................................................................................................ 401

10.4 Debug Events .............................................................................................................................. 40210.4.1 Instruction Address Compare (IAC) Debug Event ............................................................. 402

10.4.1.1 IAC Debug Event Fields ............................................................................................. 40310.4.1.2 IAC Debug Event Processing ..................................................................................... 404

10.4.2 Data Address Compare (DAC) Debug Event ..................................................................... 40510.4.2.1 DAC Debug Event Fields ............................................................................................ 40510.4.2.2 DAC Debug Event Processing ................................................................................... 407

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10.4.2.3 DAC Debug Events Applied to Instructions that Result in Multiple Storage Accesses 40710.4.2.4 DAC Debug Events Applied to Various Instruction Types ......................................... 408

10.4.3 Data Value Compare (DVC) Debug Event ........................................................................ 40910.4.3.1 DVC Debug Event Fields ........................................................................................... 40910.4.3.2 DVC Debug Event Processing ................................................................................... 41010.4.3.3 DVC Debug Events Applied to Instructions that Result in Multiple Storage Accesses 41010.4.3.4 DVC Debug Events Applied to Various Instruction Types ......................................... 41110.4.3.5 DVC Debug Events Applied to Floating-Point Loads and Stores ............................... 411

10.4.4 Instruction Complete (ICMP) Debug Event ....................................................................... 41110.4.5 Branch Taken (BRT) Debug Event .................................................................................... 41210.4.6 Trap (TRAP) Debug Event ................................................................................................ 41210.4.7 Return (RET) Debug Event ............................................................................................... 41210.4.8 Interrupt (IRPT) Debug Event ............................................................................................ 41310.4.9 Unconditional Debug Event (UDE) .................................................................................... 41410.4.10 Instruction Value Compare (IVC) Debug Event ............................................................... 41410.4.11 Debug Event Summary ................................................................................................... 415

10.5 Debug Reset ............................................................................................................................... 41510.6 Debug Timer Freeze ................................................................................................................... 41510.7 Debug Registers ......................................................................................................................... 415

10.7.1 Debug Control Register 0 (DBCR0) .................................................................................. 41610.7.2 Debug Control Register 1 (DBCR1) .................................................................................. 41810.7.3 Debug Control Register 2 (DBCR2) .................................................................................. 41910.7.4 Debug Control Register 3 (DBCR3) .................................................................................. 42110.7.5 Debug Status Register (DBSR) ........................................................................................ 42210.7.6 Debug Status Register Write Register (DBSRWR) ........................................................... 42310.7.7 Instruction Address Compare Registers (IAC1–IAC4) ...................................................... 42510.7.8 Data Address Compare Registers (DAC1–DAC2) ............................................................ 42610.7.9 Data Value Compare Registers (DVC1–DVC2) ................................................................ 42710.7.10 Instruction Address Register (IAR) .................................................................................. 42810.7.11 Instruction Match Mask Registers (IMMR) ...................................................................... 42910.7.12 Instruction Match Registers (IMR) ................................................................................... 429

10.8 Instruction Stuffing ...................................................................................................................... 42910.8.1 Ram Mode Overview ......................................................................................................... 43010.8.2 Ram Register Descriptions ................................................................................................ 43110.8.3 Example Ram Mode Procedures ....................................................................................... 434

10.8.3.1 SPR Read/Write Using GPR as Temporary Storage ................................................. 43410.8.3.2 Using Microcode Scratch Registers as Temporary Storage ...................................... 435

10.8.4 Supported Ram Instructions .............................................................................................. 43610.9 Direct Access to I-Cache and D-Cache Directories .................................................................... 437

10.9.1 General Read D-Cache Directory Sequence for L1 D-Cache ........................................... 43710.9.2 Instruction Unit Debug Register 0 (IUDBG0) ..................................................................... 43810.9.3 Instruction Unit Debug Register 1 (IUDBG1) ..................................................................... 43910.9.4 Instruction Unit Debug Register 2 (IUDBG2) ..................................................................... 43910.9.5 Execution Unit Debug Register 0 (XUDBG0) .................................................................... 44010.9.6 Execution Unit Debug Register 1 (XUDBG1) .................................................................... 44010.9.7 Execution Unit Debug Register 2 (XUDBG2) .................................................................... 441

10.10 Thread Control and Status ........................................................................................................ 44110.10.1 Using THRCTL Register to Stop Thread 0 ...................................................................... 44310.10.2 Using THRCTL Register to Start Thread 0 ...................................................................... 44310.10.3 Using THRCTL Register to Instruction Step Thread 0 .................................................... 443


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10.11 PC Configuration Register 0 (PCCR0) ...................................................................................... 44410.12 Trace and Trigger Bus ............................................................................................................... 445

10.12.1 Trace and Trigger Bus Overview ..................................................................................... 44510.12.2 Unit Level Trace and Trigger Bus Implementation ........................................................... 44610.12.3 Debug Select Registers ................................................................................................... 447

11. Performance Events and Event Selection ........................................................... 44911.1 Event Bus Overview .................................................................................................................... 44911.2 A2 Core Event Bus and PC Unit Controls ................................................................................... 450

11.2.1 Enabling Performance Event and Trace Bus Latches ....................................................... 45011.2.2 Performance Analysis Operating Modes ........................................................................... 45011.2.3 Core Performance Event Selection to External Event Bus ................................................ 45011.2.4 Core Event Select Register (CESR) .................................................................................. 452

11.3 Unit Level Performance Event Selection ..................................................................................... 45411.3.1 Unit Event Multiplexer Component .................................................................................... 45411.3.2 Performance Monitor Event Tags and Count Modes ......................................................... 45611.3.3 Unit Performance Event Tables ......................................................................................... 457

11.4 Unit Performance Event Tables .................................................................................................. 45811.4.1 FU Performance Events Table ........................................................................................... 45811.4.2 IU Performance Events Table ............................................................................................ 45811.4.3 XU Performance Events Table .......................................................................................... 46011.4.4 LSU Performance Events Table ........................................................................................ 46211.4.5 MMU Performance Events Table ....................................................................................... 465

11.5 Unit Event Select Registers ......................................................................................................... 46611.5.1 FU Event Select Register (AESR) ..................................................................................... 46611.5.2 IU Event Select Registers .................................................................................................. 46811.5.3 XU Event Select Registers ................................................................................................. 47011.5.4 LSU Event Select Registers ............................................................................................... 47211.5.5 MMU Event Select Registers ............................................................................................. 474

11.6 A2 Support for Core Instruction Trace ......................................................................................... 47611.6.1 Instruction Trace Mode Setup ............................................................................................ 47611.6.2 Instruction Trace Record Data ........................................................................................... 47611.6.3 Instruction Trace Record Formats and Ordering ............................................................... 47711.6.4 Debug Bus Control When in Instruction Trace Mode ......................................................... 478

11.6.4.1 FU Trace Records ...................................................................................................... 47911.6.4.2 XU Debug Bus Control ............................................................................................... 479

11.7 A2 Support for Instruction Sampling ............................................................................................ 479

12. Implementation Dependent Instructions ............................................................. 48112.1 Miscellaneous .............................................................................................................................. 481

12.1.1 Attention (attn) ................................................................................................................... 48112.2 TLB Management Instructions .................................................................................................... 482

12.2.1 TLB Read Entry (tlbre) ...................................................................................................... 48212.2.2 TLB Write Entry (tlbwe) ..................................................................................................... 48412.2.3 TLB Search Indexed (tlbsx[.]) ........................................................................................... 48612.2.4 TLB Search and Reserve Indexed (tlbsrx.) ....................................................................... 48812.2.5 TLB Invalidate Virtual Address Indexed (tlbivax) .............................................................. 49012.2.6 TLB Invalidate Local Indexed (tlbilx) ................................................................................. 493

12.3 ERAT Management Instructions ................................................................................................. 496

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12.3.1 ERAT Read Entry (eratre) ................................................................................................. 49612.3.2 ERAT Write Entry (eratwe) ............................................................................................... 49912.3.3 ERAT Search Indexed (eratsx[.]) ..................................................................................... 50212.3.4 ERAT Invalidate Virtual Address Indexed (erativax) ........................................................ 50412.3.5 ERAT Invalidate Local Indexed (eratilx) ........................................................................... 507

12.4 Software Transactional Memory Instructions .............................................................................. 50912.4.1 Load Doubleword and Watch Indexed X-Form (ldawx.) ................................................... 51012.4.2 Watch Check All X-Form (wchkall) ................................................................................... 51112.4.3 Watch Clear X-Form (wclr) ............................................................................................... 512

12.5 Coprocessor Instructions ............................................................................................................ 51312.5.1 Initiate Coprocessor Store Word Indexed (icswx[.]) ......................................................... 515

12.5.1.1 General Registers ...................................................................................................... 51612.5.1.2 Initial Execution .......................................................................................................... 517

12.5.2 Initiate Coprocessor Store Word External Process ID Indexed (icswepx[.]) .................... 51812.5.3 Execution ........................................................................................................................... 518

12.5.3.1 Condition Register 0 ................................................................................................... 51912.5.4 Coprocessor-Request Block .............................................................................................. 520

12.5.4.1 Available Coprocessor Register (ACOP) ................................................................... 52012.5.4.2 Hypervisor Available Coprocessor Register (HACOP) ............................................... 521

12.6 Data Cache Block Flush .............................................................................................................. 52312.6.1 Data Cache Block Flush (dcbf) ......................................................................................... 523

12.7 Data Cache Block Flush by External PID .................................................................................... 52412.7.1 Data Cache Block Flush by External PID (dcbfep) ........................................................... 524

13. Power Management Methods .............................................................................. 52513.1 Chip Power Management Controls ............................................................................................. 52513.2 Power-Saving Instructions .......................................................................................................... 525

13.2.1 Power-Saving Instruction Sequence ................................................................................. 526

14. Register Summary ................................................................................................ 52914.1 Register Categories .................................................................................................................... 52914.2 Reserved Fields .......................................................................................................................... 53514.3 Unimplemented SPRs ................................................................................................................. 53514.4 Device Control Registers ............................................................................................................ 53514.5 Alphabetical Register Listing ....................................................................................................... 537

14.5.1 ACOP - Available Coprocessor ......................................................................................... 53814.5.2 AESR - AXU Event Select Register ................................................................................... 53914.5.3 CCR0 - Core Configuration Register 0 .............................................................................. 54114.5.4 CCR1 - Core Configuration Register 1 .............................................................................. 54214.5.5 CCR2 - Core Configuration Register 2 .............................................................................. 54314.5.6 CCR3 - Core Configuration Register 3 .............................................................................. 54514.5.7 CESR - Core Event Select Register .................................................................................. 54614.5.8 CR - Condition Register ..................................................................................................... 54914.5.9 CSRR0 - Critical Save/Restore Register 0 ........................................................................ 55014.5.10 CSRR1 - Critical Save/Restore Register 1 ...................................................................... 55114.5.11 CTR - Count Register ...................................................................................................... 55314.5.12 DAC1 - Data Address Compare 1 ................................................................................... 55414.5.13 DAC2 - Data Address Compare 2 ................................................................................... 55514.5.14 DAC3 - Data Address Compare 3 ................................................................................... 556


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14.5.15 DAC4 - Data Address Compare 4 .................................................................................... 55714.5.16 DBCR0 - Debug Control Register 0 ................................................................................. 55814.5.17 DBCR1 - Debug Control Register 1 ................................................................................. 56014.5.18 DBCR2 - Debug Control Register 2 ................................................................................. 56214.5.19 DBCR3 - Debug Control Register 3 ................................................................................. 56414.5.20 DBSR - Debug Status Register ........................................................................................ 56514.5.21 DBSRWR - Debug Status Register Write Register .......................................................... 56714.5.22 DEAR - Data Exception Address Register ....................................................................... 56914.5.23 DEC - Decrementer ......................................................................................................... 57014.5.24 DECAR - Decrementer Auto-Reload ............................................................................... 57114.5.25 DVC1 - Data Value Compare 1 ........................................................................................ 57214.5.26 DVC2 - Data Value Compare 2 ........................................................................................ 57314.5.27 EPCR - Embedded Processor Control Register .............................................................. 57414.5.28 EPLC - External Process ID Load Context ...................................................................... 57614.5.29 EPSC - External Process ID Store Context ..................................................................... 57714.5.30 EPTCFG - Embedded Page Table Configuration Register .............................................. 57814.5.31 ESR - Exception Syndrome Register ............................................................................... 57914.5.32 GDEAR - Guest Data Exception Address Register ......................................................... 58114.5.33 GESR - Guest Exception Syndrome Register ................................................................. 58214.5.34 GIVPR - Guest Interrupt Vector Prefix Register ............................................................... 58414.5.35 GPIR - Guest Processor ID Register ............................................................................... 58514.5.36 GSPRG0 - Guest Software Special Purpose Register 0 ................................................. 58614.5.37 GSPRG1 - Guest Software Special Purpose Register 1 ................................................. 58714.5.38 GSPRG2 - Guest Software Special Purpose Register 2 ................................................. 58814.5.39 GSPRG3 - Guest Software Special Purpose Register 3 ................................................. 58914.5.40 GSRR0 - Guest Save/Restore Register 0 ........................................................................ 59014.5.41 GSRR1 - Guest Save/Restore Register 1 ........................................................................ 59114.5.42 HACOP - Hypvervisor Available Coprocessor ................................................................. 59314.5.43 IAC1 - Instruction Address Compare 1 ............................................................................ 59414.5.44 IAC2 - Instruction Address Compare

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for Blue Gene/Q - Argonne National Laboratory · for Blue Gene/Q Note: This document and the information it contains are provided on an as-is basis. There is no plan for providing