FONT4 Status Report

FONT4 Status Report

Glenn Christian

John Adams Institute, Oxford

for FONT collaboration

Glenn Christian - LCABD 12/04/07 2

IP Feedback system - concept

• Last line of defence against relative beam misalignment

• Measure vertical position of outgoing beam and hence beam-beam kick angle

• Use fast amplifier and kicker to correct vertical position of beam incoming to IR

FONT – Feedback On Nanosecond Timescales


FONT1,2,3 Analogue Feedback Tests

• FONT1&2 @ NLCTA: 2001-4, 170 ns train length, 87 ps bunch spacing– Achieved total latency of 67 (FONT1) & 54 ns

(FONT2)

• FONT3 @ ATF: 2004-5, 56 ns train length, 2.8 ns bunch spacing– Latency 23 ns– BPM processor resolution of 3-5 microns


FONT1,2,3: Summary67 ns

54 ns

23 ns


FONT4 motivation

• FONT1,2,3 – ultra-fast demonstration of feedback using analogue BPM processor originally driven by ‘warm’ bunch spacing

• FONT4 – demonstration of feedback on ILC-like bunches using digital processor– allows implementation of algorithms for luminosity recovery

• Now 3 bunch train at ATF produced from ~300 ns kicker pulse

• Later new extraction kicker - 20 bunches @ ~150 ns (FONT5?)


FONT4 system overview

KICKERBPM 11BPM 13 BPM 12

AMPAnalog FE Analog FE Analog FE

Witness BPMs

Digital processor

Feedback BPM

Machinetimingsystem

Scopes

∑

∆

BEAM

clks, triggers

LO

DAQ

I/O, digital DAQ


FONT4 goals/challenges

• Stabilise third bunch at micron level– Require latency < bunch spacing– Nominal bunch spacing 154 ns but can be altered in 2.8 ns

steps – must be able to work with this!– For this reason set latency target as 140 ns

• Max ADC sampling speed (14-bit device): 105 MHz– One sample per bunch – leads to rather complicated

arrangement for sampling at the peak for each bunch– Need timing synchronised to machine (357 MHz machine

clock, 2.16 MHz ring clock, and pre-beam trigger)– Want to sample as fast as possible (choose 357/4 MHz

adjusted using 357/5 MHz between bunches)


Digital Board

2 x Analog Input channels (single-ended)

2 x Analog Output channels (differential) 4 x General-purpose digital outputs

3 x external clock/trigger inputs

Xilinx Virtex4 FPGA

Analog Devices ADC/DACs

40 MHz oscillator

RS232 comms

JTAG port PROM

GP I/O Header


FONT4 Latency Budget/Estimate

Original Latency Budget• Time of flight kicker to BPM (assuming 2m

lever arm): 7 ns• Signal propagation delay BPM to kicker:

15 ns•

Irreducible latency: 22 ns• BPM analogue processor:

10 ns• Digital processor:

68 ns– ADC/DAC: ~40 ns– FPGA I/O: 3 ns– FPGA processing (8 clock cycles): 25 ns

• Amplifier: 40 ns Electronics latency: ~118 ns

• Total latency: ~140 ns

Digital board latency test

Minimum latency ~6.5 clock cycles

~70 ns @89.25 MHz


FONT4 firmware features

• System clock frequency 357 MHz – locked to ATF and hence bunches

• Free-running design - 14-bit ADCs/DACs – 105 MSPS• Use fact that harmonic number is 330 (ie 165 cycles of 357 per

DR clock period) and pre-beam trigger to select correct ring-clock cycle then count in steps of 2.8 ns (357 MHz) to sample at bunch peak

• Use BRAM(ROM) to output the ADC and DAC enables, sample at 357/4 at the bunches and 357/5 during quiescence to adjust the enable bitstreams to ring clock period. BRAM also outputs clk_en strobes

• Baseline is 4 clock cycle latency (@357 MHz) from input to output buffer


JTAG

INPUTSOUTPUTS

Clk_357

Clk_2.16

Clk_40

ILATrigger

VIO controls

FPGA – Timing & Data Processing

CTR1

RST

CTR2==

SYNC_DELAY

RST

BRAMADDR

Triggerprocessing

ADC_clk DAC_clk

&

Difference

Sum 1/Sum(LUT)

X X GAIN + & AOUT

DELAY ‘LOOP’

IDELAY


New Amplifier Design

• New design for “universal” FONT amplifier– Designed to have flexibility to

meet future requirements – Design for 10 us operation with

35 ns settling time at rep rate of 2 Hz

– Output current up to +/- 30 A– Manufactured by TMD

Technologies in UK– Two units delivered 1

December 2006


Amplifier Tests at ATF (Dec 2006)

• Two amplifier variants tested on ATF extraction line, using special version of FONT4 firmware– Second variant 5 ns faster – both now same build standard

• ‘Feedback loop’ closed in terms of hardware, cables, timing etc but amplifier driven with top-hat signal, not position-feedback signal

• Variable amplitude, polarity flip, and delay of top-hat wrt nominal output time

• Measured kick linearity, kick as a function of electrode gap (kicker inductance), kick as a function of output delay (slack) – system latency


Kick Linearity


System Latency (BS = 154ns)

Latency ~135ns


System Latency (BS = 154ns)

20ns slack to 80% full kick


Position Feedback Tests (Feb 2007)

• Ran with bunch spacing of 154 ns

• Firmware features: 8 left-shift gain settings (x1 – x128), delay loop, delay and feedback switches, output inversion, no saturation

• Took data at various positions and gain settings

• Checked functionality of gain and delay loop


Feedback in action (154 ns BS, gain x16)

Scopes

Integrated Logic Analyser


Current work

• Performance optimisation features still to include:– load ‘fixed’ gain curves into look-up tables

• BRAM(ROM) contents pre-computed and loaded using a partial reconfiguration technique

– real-time charge normalisation • Fast multiply-accumulate of gain-corrected difference and reciprocal-

sum signals + delay register

• Fastest results utilise on-chip resources but require pipelining (eg DSP blocks – requires 3 levels of pipelining to run at 357 MHz – entire register budget)

• Delicate trade-off between speed and #pipelines (latency) and maybe #bits (resolution)


Conclusions

• Demonstrated closed loop feedback at ATF with 3 bunches ~150ns spacing with digital feedback processor

• System latency ~135ns

• New amplifier manufactured by TMD Technologies and tested at ATF

• Further work to be done to optimise the performance of the system

Documents

FONT4 Status Report