10SETMVD0521 2015

MODULAR MULTI-VOLTAGE FLOORPLANNING USING SEQUENCE PAIR

REPRESENTATION

Under the guidance of Prof. John Reube

Abstract:

With the decreasing feature size, for a fixed area the amount of functionality on the chip is increasing. This increases the number of modules on the chip thereby increasing the power consumed by the modules. Power thus becomes a critical parameter to be handled at all levels of abstraction. Formation of voltage-islands is one of the best techniques of power reduction at the block level. It can be achieved both at the inter-block level and intra-block level. Modular floor planning is dividing the chip into various blocks according to their operating voltage and then optimizing it within the islands created. Along with power, the amount of dead space needs to be minimized to optimise the area constraint. Sequence pair representation of various blocks helps reducing the dead space thus optimising area. This project mainly aims at multi-objective floor planning for optimizing the area as well as the power constraint. The area is optimised by sequence pair representation of floor plan by reducing the dead space and multi-objective simulated annealing is used to jointly optimise both area and power.

Objective:

Given various blocks with different operating voltages, perform modular floor planning to optimize area within the created voltage island.

10SETMVD0521 2015

Jointly optimize area and power by multi-objective simulated annealing.

Expected outcome:

Final floor plan with voltage islands and optimized power and area.

Methodology:

Given the blocks with their sequence pair representation, aspect ratios and operating voltage, generate the initial floor plan using LCS algorithm.

Perform voltage islands as per their operating voltages.

Carry out intra- block area optimization.

Placement of the optimized voltage islands on the chip.

Multi-objective simulated annealing to optimize inter- block area and power of the chip.

Tools used:

The source code is written in java language and the results are viewed using java applets.

ECLIPSE

References:

10SETMVD0521 2015

[1] X. Tang, R. Tian, D.F. Wong, Fast evaluation of sequence pair in block placement by longest common subsequence computation, in: Design, Automation and Test in Europe, 2000, pp. 106–111.

[2] H. Murata, K. Fujiyoshi, S. Nakatake, and Y. Kajitani, “VLSI module

placement based on rectangle-packing by the sequence pair,” IEEE

Trans. on CAD, vol. 15, no. 12, pp. 1518–1524, 1996.