Flip-FlopsSection 4.3 Mano & Kime

D LatchQ !QCLK D !S!RSRNote that Q follows Dwhen the clock in high,and is latched when theclock goes to zero.

D Flip-FlopQ !Q!S!RSRNCK

Pulse-Narrowing Circuit

D Flip-FlopD gets latched to Q on the rising edge of the clock.Positive edge triggered

D Flip-FlopyCLK zpulse widthsetuptimehold timepropagationdelay

Making a positive edge-triggered D Flip-Flop from Master-Slave D LatchesCLK xzyDEQDEQCLK inputoutputxyzCLK CLK masterslave

SR Master-Slave Flip-FlopS R CLK Q !Q0 0 1 Q0 !Q0 Store 0 1 1 0 1 Reset1 0 1 1 0 Set1 1 1 1 1 DisallowedX X 0 Q0 !Q0 Store

CLK K Q !QJ J-K Flip-FlopJ K CLK Q !Q0 0 Q0 !Q00 1 0 11 0 1 01 1 ToggleX X 0 Q0 !Q0

Master-Slave J-K Flip-Flop

Master-Slave J-K Flip-Flop

D-Type Positive Edge-Triggered Flip-Flop

Positive Edge-Triggered J-K Flip-Flop