D Flip-FlopFlip-Flop

Lecture Overview D Flip-Flops

Logic Synchronization

Types of D Flip Flops

Sample Flip-Flop Applications

D Flip-FlopCLK

Q n+1

0

1

D

0

1

D Q

Q

CLK

D

Q

Positive Edge Triggered

Logic SynchronizingData enters

here at different times

Data goes out at the same

time on a clock pulse

Example:

Parallel Port

Types of D Flip-Flops

D Q

QPositive Edge Triggered

Negative Edge TriggeredD Q

Q

D Q

QNegative Level Triggered

D Q

QPositive Level Triggered

Types of D Flip-Flops

Asynchronous Inputs

D Flip-Flop w/ PresetD Q

Q

P-SET

D Flip-Flop w/ ClearD Q

QCLR

D Flip-Flop w/ Preset & ClearD Q

Q

P-SET

CLR

Asynchronous Inputs

D Flip-Flop w/ Preset & Clear

Q n+1

1 (preset)

0 (clear)

? (illegal)

0

1

CLK

X

X

X

D

X

X

X

0

1

CLR

1

0

0

1

1

P-SET

0

1

0

1

1

D Q

Q

P-SET

CLR

Application of D Flip-Flops

Data Storage

Counters & State Machine Designs

Logic Synchronizing

Divide By Circuits

Divide By Circuit with D Flip-Flop

Divide By Circuit - Simulation