Note: Within nine months from the publication of the mention of the grant of the European patent, any person may givenotice to the European Patent Office of opposition to the European patent granted. Notice of opposition shall be filed ina written reasoned statement. It shall not be deemed to have been filed until the opposition fee has been paid. (Art.99(1) European Patent Convention).

Printed by Jouve, 75001 PARIS (FR)

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(12) EUROPEAN PATENT SPECIFICATION

(45) Date of publication and mention of the grant of the patent: 13.06.2007 Bulletin 2007/24

(21) Application number: 95916649.7

(22) Date of filing: 13.04.1995

(51) Int Cl.:H01L 21/58 (2006.01) H01L 21/60 (2006.01)

(86) International application number: PCT/EP1995/001388

(87) International publication number: WO 1996/005614 (22.02.1996 Gazette 1996/09)

(54) FLIP CHIP BONDING WITH NON-CONDUCTIVE ADHESIVE

FLIP-CHIP-VERBINDUNG MIT NICHTLEITENDEM KLEBMITTEL

SOUDAGE DES PUCES A BOSSES AVEC UN ADHESIF NON-CONDUCTEUR

(84) Designated Contracting States: CH DE FR GB LI

(30) Priority: 12.08.1994 EP 94112626

(43) Date of publication of application: 29.10.1997 Bulletin 1997/44

(73) Proprietors: • Pac Tech - Packaging Technologies GmbH

14641 Nauen (DE)• Zakel, Elke

14612 Falkensee (DE)

(72) Inventors: • ASCHENBRENNER, Rolf

D-12055 Berlin (DE)

• GWIASDA, JörgD-13437 Berlin (DE)

• ZAKEL, ElkeD-12163 Berlin (DE)

• ELDRING, JoachimD-13355 Berlin (DE)

(74) Representative: Leonhard, Frank Reimund et alLeonhard - Olgemöller - Fricke Patentanwälte Postfach 10 09 6280083 München (DE)

(56) References cited: EP-A- 0 387 066 EP-A- 0 388 011EP-A- 0 528 171 EP-A- 0 596 393DE-A- 3 829 538

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Description

[0001] The invention concerns the field of microelec-tronics packaging technology. Various bonding methodsand mediums may be used to attach the IC die. Sincethe development of the flip chip mounting process usingsolder by IBM (C4 process) in the early 1960’s, the facedown bonding technology has become popular and man-ifold and original interconnection methods have been re-ported. At the same time the interest in flip chip bondingis being driven by demands for substrates accepted inthe consumer field. Therefore the substrates which areto be bonded by flip chip have been changing from inor-ganic to organic, such as polyimide foil and printed circuitboards (often FR-4). By using solder alloys it is possibleto attain low resistance as well as a good thermal contactbetween the chip and the packaging substrate, includingFR-4 and polyimide flex with the use of encapsulants.The result is an improvement in the thermal life cycle offlip chips mounted on high CTE packaging substrates.[0002] The interest in flip chip assemblies using adhe-sives for high density, fine pitch and high performanceinterconnections has increased rapidly. In this context anew flip chip technology is suggested using non-conduc-tive adhesives in place of the known stiffenable resin, cf.US-A 4,749,120 (Hatada, - Matsushita)[0003] EP-A 387 066 (Hitachi) provides a method formechanically attaching and electrically connecting chipswith almost rectangular bumps to a substrate which car-ries a conductive pattern (cf. page 4, lines 34 to 38). Sev-eral types of bump shapes are suggested, cf. said doc-ument in figures 3, 4, 5 and 6. An adhesive is provided,through which the bumps are pressed, to yield an elec-trical contact on the pattern. A different shape of bumpsis shown in DE-A 38 29 538 (Siemens), wherein contactbumps are shown in figure 1 of said document, having alarge base section and a very tiny peak section in shapeof a half sphere, directly adjoining the base section; forgreater detail of description of said "Höcker, sogenanntebumps" confer to said document in column 1, lines 57 to62. An adhesive foil or anything which is pierced by saidbump is not provided, instead the bump itself is providingthe electrical connection by means of a thermo-compres-sive method.[0004] The invention aims to provide an improvedbonding structure and an improved bonding method, em-ploying a certain shape of bump and an adhesive materialto connect the chip to the organic carrier substrate.[0005] The inventive concept is to simultaneously at-tach and electrically interconnect at least one bare chipwith (e.g. gold) stud bumps to many types of packagingsubstrates, the bumps having a certain shape to easethe piercing through the sheet or sheet-foil of adhesivematerial (claim 1).[0006] By this interconnection method, the chip isbonded face down and is electrically connected via com-pressed and deformed bumps with the organic substrate.The chip is fixed by the non-conductive adhesive film

which fills the entire gap between the die (the resp. barechip) and packaging substrate. The claimed method ob-tains greater compliance or flexibility, especially advan-tageous for organic substrates.[0007] Compared to US-A 4,749,120 the bonding byheat was extraordinarily accelerated although physicalbonding parameters were improved and flexibility (com-pliance) of the bonded microelectronic package was ob-tained.[0008] The adhesive is best to be applied in sheet foilform (claim 3) and in a blend of thermoplastic/thermoset-ting adhesive materials (claims 3,2).[0009] An exemplary non-conductive adhesive filmwas studied with an emphasis on the properties of COF(chip on flex) and COB (chip on board) interconnections.Electrical and mechanical performance of the adhesivebonds were studied by evaluating initial contact resist-ance and mechanical adhesion as a function of temper-ature and humidity.[0010] Both mechanical and electrical properties weremeasured before and after the environmental tests andcompared to soldered contacts. For flip chip intercon-nects with a pad size of 100Pm2 on the chip site and acontact area of approx. 60Pm round, the resistance isless than 8mΩ. This low contact resistance can be attrib-uted to the special process and materials applied accord-ing to the invention. Moreover, the bonding pressure(claim 4), bonding temperature and time (claim 1) in com-parison with the contact resistance were examined.[0011] The results of the inventive concept indicatethat the control of these process parameters will yieldgood bonding quality. Non-conductive adhesive flip chiptechnique offers several important advantages over sol-der filling materials, however, introduce other new prob-lems. The major disadvantages are that they do not allowrework, they have manufacturability problems such aslong cure time and they need high solder bumps. Theuse of adhesives instead of soldering in flip chip bondingon organic substrates however avoids the problems withsolder. Also there are potential cost benefits in the re-duction of processing steps if adhesive flip chip bondingis used.[0012] The invention uses "stud bumps" and non-con-ductive adhesive (claim 1). This technique allows qualityattachment of IC’s on low cost organic substrates andoffers numerous advantages in the assembly of electron-ic circuits. These include low processing temperatures,fluxless bonding, high density interconnections, replace-ability and high reliability, speeding up of the attachmentprocess and allowing for elastic movement of the bondedmicroelectronic package.[0013] The more detailed shape of the bumps is de-veloped in claim 5; they may be of gold, to yield bestresults (claim 6). To improve and ease the deformationduring bonding, the protruding front section is softer thanthe base part of the bumps, preferably shaped like a ball.[0014] Examples and test results will demonstrate theinvention in greater detail.

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Figure 1 is a schematic flow chart of the non-con-ductive adhesive flip chip process.

Table 1 is a summarized example organic boardspec. (FR-4; FLEX) .

Figure 2a

Figure 2b

Figure 3 show the ball bump geometry. The bumpshape showing a basic slightly flattenedbody with a protruding top or peak. Thethinner top part being softer than the bot-tom almost ball shaped part, to more eas-ily be deformed. Between the peak toppart and the ball shaped bottom part aconical section is established, being alsosofter than the bottom ball shaped part.Figure 3 demonstrates the dimensions ofthe bumps, here a gold bump of Au 98Pd. Figure 2b is an area configuration.

Figure 4

Figure 5 is a basic example of the inventive meth-od with temperature/pressure parame-ters for bonding.

Figure 6a

Figure 6b are representations of bonded IC to FR-4 substrate with deformed gold bumps,showing the gold, nickel and copper in-terface.

Table 2 is a summarized specification of the ad-hesive.

Figure 7 shows adhesive temperature vs. ther-mode temperature at bonding site.

Figure 8 is a representation of a temperature testcycle.

Figure 9a

Figure 9b show temperature test cycle results (FR-4; FLEX).

Figure 10a

Figure 10b show humidity test results (FR-4; FLEX).

Figure 11 shows temperature dependant resist-ance.

Figure 12 shows the influence of humidity and tem-

perature on bonding strength.

Testchip and testsubstrate:

[0015] The continuity test devices for most of this workhave a size of 5 and 7.5mm2, pitches of 200 and 300Pmand pad sizes of 80Pm octagonal (see Table 1). Themetallization is 1Pm AlSi 1% with a PSG-passivation.The substrates used for this flip chip bonding were 1mmthick printed circuit boards (FR-4) and 25Pm flexprint (Es-panex). The overall dimension of the substrates was2inch2 (see Table 1). The conductor patterns were gold/nickel coated copper in both cases. The printed circuitboard, which was also used for flip chip attachment usingsolder, carries a solder mask as a finishing layer. Themask has no influence on the non-conductive adhesiveprocess. Both test vehicles carry interconnection trackswhich allow monitoring of the electrical integrity by meas-uring the contact resistance (four-point-probe) and transitresistance (daisy chain).

Bump processing:

[0016] The gold ball bumps are fabricated with a flex-ible low cost bumping technique based on the conven-tional wire bonding procedure (cf. 1994, ITAP & Flip ChipProceedings, pages 74 to 79, by J. Eldring et al.). Estab-lished wire bonding machines can be used, therefore,expensive bumping process equipment for sputteringphotolithography and plating is not necessary. The sizesand geometry of ball bumps are principally dependenton the wire diameter, the geometry of the capillary aswell as on the bumping parameters.

Non-conductive adhesive:

[0017] The adhesive film suggested, consists of insu-lative thermosetting/thermoplastic blend adhesive with-out conducting particles and fillers. The adhesive wasfabricated in a dry film format with different film thickness-es of 25Pm and 50Pm. For repairing the interconnection,the whole flip chip joint is heated to a temperature ofapproximately 125°C to 130°C in order to debond the IC.Their detailed specifications as well as the bonding pa-rameters are summarized in Table 2.

Bonding Process:

[0018] The fundamental process flow for the non-con-ductive adhesive flip chip attachment is shown in Figure4.

This process is made up of three basic steps:

[0019]

Step 1: Non-conductive adhesive is applied to thesubstrate for the purpose of fixing the chip.

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Step 2: The gold ball bumps on the chip and theelectrodes on the substrate are aligned.Step 3: Bonding the chip on the substrate with anappropriate load (min. 20kg/cm2) and with a temper-ature up to 180°C for 15 to 20sec (see Figure 5).

[0020] Thus the IC is electrically connected to the sub-strate via compressed and deformed gold ball bumps(see Figures 6a, b).[0021] The pressure is maintained on the bond site,until the chip is fixed by cooling the thermode. The bond-ing process was performed with the semi-automatic flipchip bonder FC 950 from Carl Süß (France). This pieceof equipment utilizes two stage heating in the thermo-compression mode and allows cooling while pressure isbeing maintained. Because of the accuracy needed, thebonder consists of a split-field optic to locate the chip andthe substrate. The recommended temperature should bemaintained throughout the total bond cycle. Therefore,the actual adhesive temperature was measured by em-bedding a thermocouple in the adhesive during the bond-ing process.[0022] Figure 7 shows the measured temperature dif-ference between the thermode set point and the real bondtemperature in the adhesive. The significant differencedepends on the thermoconductivity of each material. Thecold chuck, where the substrate is fixed by vacuum, actsas a heat sink for the flip chip joint. The combined thick-ness of the adhesive and substrate plays an additionalrole for the heat exchange.

Reliability tests:

[0023] In order to clearly distinguish the failure modeand degradation mechanism of non-conductive adhesivejoints, both the mechanical adhesion by pull test and theelectrical performance were evaluated. To obtain thesedata, test samples were assembled and subjected to ac-celerated life testing. The test method includes thermalcycling and storage at high temperature and humidity.The applied acceleration test method for thermal cyclinginvolved 1000 cycles between -55 and +125°C, with acycle duration of 30 minutes. Samples were measuredafter 50, 100, 250, 500 and 1000 cycles. The cycle regimewas taken from a modification of the MIL standard 883thermal shock test. A schematic drawing of the actualthermal cycle profile is shown in Figure 8. The constanthumidity test was performed at a constant temperatureof 85°C and at a relative humidity of 85%. The total du-ration of the test was 1000 hours.[0024] Interconnection functionality was measured af-ter 50, 100, 250, 500 and 1000 hours.

Electrical Characteristics:

[0025] The electrical characteristics were studied bymonitoring the contact resistance and transit resistanceafter the reliability tests. Results are summarized in Fig-

ure 9 and 10. After 1000 temperature cycles no openjoints for the chips bonded to both substrates were ob-served. However, the degradation of the resistance ofthe 7.5mm square chip increased slowly with the numberof cycles, reaching a value twice as large as the initialcondition (see Figure 9a, 10a). In the case of the 5mmsquare chip, the connection resistance was nearly con-stant. The reason for the change in contact resistancecan be attributed to the stress-induced contact spacingchanges between the gold ball bumps and the electrodesof the substrate. In comparison with solder joints, wherereliability problems arise from fatigue failures during ther-mal cyclings (CTE differences), adhesive joints tend tobe more compliant and less susceptible to fatigue failure.In contrast to temperature cycling, humidity testingcaused higher contact resistance values (see Figure 9b,10b). In the case of the FR-4 board (see Figure 9b) thevalues after 1000 hours were independent of the chipsize. The measured value was approximately 27mΩ witha small standard deviation of 4.5mΩ. The results forthe flexible polyimide substrate (see Figure 10b) exhibita better stability, especially for the 5mm square chip. Pos-sible causes for the high contact resistance are thechange in volume when the adhesive swells in z-axisdirection due to moisture absorption or an oxidation ef-fect. To obtain excellent reliability and interconnectionstability, a bonding load was selected by the thicknessof the adhesive, by the bumpheight and by the givenbonding parameters of the adhesives. The force was ad-justed until there was no further reduction in contact re-sistance.[0026] The best results could be achieved with bondforces in the range of 80 to 100g/bump. Despite thesehigh bond forces no cracks occurred during bonding, nei-ther on chip nor on substrate.[0027] Another point to obtain high reliability is to havecompliance in the interconnection. This compliance isrequired to compensate for non-planarities of the sub-strate and thermal mismatch of the interconnection ma-terials. Under operating conditions the thermal mismatchdifference in z-direction between the gold ball bump andthe adhesive will expand the adhesive faster than thebumps. This leads to early failures when there is no com-pliance. Therefore, the behaviour of the flip chip inter-connects was checked by a temperature operating test.The specimen was heated up from 25°C to 125°C, inincrements of 25°C, and held at each temperature formeasuring the contact resistance.[0028] Figure 11 shows the relationship between thecontact resistance of the electrodes and the temperature.The resistance increases gradually for all devices from5mΩ to approximately 8mΩ. Compared to the first inves-tigation, which was performed at lower bond tempera-ture, no electrical contact failures were observed evenafter 125°C. The higher contact resistance disappearedwhen returned to room temperature.

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Mechanical Characteristics:

[0029] The adhesive strength was evaluated by a ten-sile tester (Instron 4502) on the rigid printed circuitboards. The board was clamped to a plate and the loadwas applied directly from above. The peel strength testswere carried out on the 7.5mm square chips employedin the two environmental tests, and compared with a sam-ple stored at room temperature. The results in Figure 12show the influence of the environmental tests on the flipchip joint. For all samples the failure mode was an ad-hesion failure at the interface between the adhesive andthe solder mask on the printed circuit board. Cohesivefailure was never observed in this test.[0030] Suggested is a flip chip technology using non-conductive adhesives and gold ball bumps or connectors.The concept is to simultaneously attach and interconnectbare chips with gold ball bumps to organic substrates.The chip is fixed by cooling the insulative adhesive. En-vironmental testing has demonstrated that performancecharacteristics were acceptable after 1000 hours of con-tinuous exposure to humidity, and were excellent after1000 temperature cycles. Such stable interconnectionscan only be realized by the compliance of the flip chipjoint. This stability can be achieved by precise control ofthe bonding parameters such as temperature and pres-sure. This bonding technique allows quality attachmentof bare chips on low cost organic substrates.

Claims

1. Method of simultaneous mechanically attaching andelectrically connecting at least one bare chip havingstud bumps (10) to a carrier organic substrate (30),comprising:

(a) covering the organic substrate (30), carryinga conductive printed pattern, with a film (20)comprising an insulative non conductive adhe-sive material;(b) aligning the bumps (10) of said chip or chipsto the conductive printed pattern on the organicsubstrate (30), whereby the stud bumps (10)have a base (10a), a conical (10c) and a peak(lOb) section, said peak section (10b) being soft-er than said base section (10a) and being sub-stantially deformed upon effecting a pressureduring bonding of the bumps to the conductiveprinted pattern;(c) bonding the chip or chips face down to theconductive printed pattern on the organic sub-strate (30) with a temperature of no more than180°C for about 15 sec to 20 sec and a minimumload of 20kg/cm2, the stud bumps (10) piercingthrough the film of adhesive material during saidbonding process step.

2. Method according to claim 1, wherein the non-con-ductive adhesive material is a thermosetting or athermoplastic blend adhesive or is a blend of ther-mosetting and thermoplastic adhesive materials.

3. Method according to any one of the precedingclaims, the adhesive material being a sheet foil (20)of a blend of thermoplastic and thermosetting adhe-sive materials.

4. Method according to any one of the precedingclaims, the bonding force being in the range of 80gto 100g per stud bump (10).

5. Method according to any one of the precedingclaims, wherin the conical section (10c) connectingthe base section (10a) and the peak (10b) section,is softer than the base section.

6. Method according to any one of the precedingclaims, the bumps (10;10a,10b) being of gold.

7. Method according to any one of the precedingclaims, the adhesive film (20) having a thickness of25 Pm or 50 Pm, and being manufactured in a dryfilm format.

Patentansprüche

1. Verfahren zum gleichzeitigen mechanischen An-bringen und elektrischem Verbinden von zumindesteinem Chip mit Kontaktbumps (stud bumps;10) anoder zu einem organischen Trägersubstrat (30), mitden Verfahrensschritten:

(a) Bedecken des organischen Substrats (30),welches ein leitfähiges gedrucktes Leiterbah-nenmuster trägt, mit einem Film oder einerSchicht (20), welcher einen isolierenden, nichtleitenden Kleberwerkstoff aufweist;(b) Ausrichten der Bumps (10) des oder derChips zu dem gedruckten Leitungsmuster aufdem organischem Substrat (30), wobei die Kon-taktbumps (10) eine Basis (10a), einen koni-schen (10c) und einen Spitzenabschnitt (10b)aufweisen, wobei der Spitzenabschnitt (10b)weicher ist als der Basisabschnitt (10a), und we-sentlich verformt wird, beim Aufbringen vonDruck während des Bondens der Bumps auf diekontaktfähigen Leiterbahnen (gedrucktes Lei-terbahnenmuster);(c) Bonden des Chips oder der Chips kopfüberauf des leitfähige gedruckte Leiterbahnmusterauf dem organischen Substrat (30), mit einerTemperatur von nicht mehr als 180°C für etwa15 sec bis 20 sec und einer Mindestlast von 20kg/cm2, wobei die Kontaktbumps (10) durch den

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Film oder die Schicht des leitfähigen Materialshindurch greifen oder ihn durchstoßen, dieswährend des Bondingprozesses.

2. Verfahren nach Anspruch 1, wobei die nicht-leitendeKleberschicht oder das Klebermaterial ein thermo-plastisches oder thermofixiertes (heiß- oder wärme-gehärtetes) Material aufweist, dass in einer Mi-schung Klebereigenschaft aufweist, oder eine Mi-schung eines thermofixierenden und thermoplasti-schen Klebstoffmaterials ist.

3. Verfahren nach einem der vorigen Ansprüche, wobeidas Klebermaterial als Folienschicht (20) eine Mi-schung von thermoplastischen und thermofixieren-den Klebstoffmaterial ist.

4. Verfahren nach einem der vorigen Ansprüche, wobeidie Bondingkraft in der Größenordnung von 80g bis100g pro Kontaktbump (10) liegt.

5. Verfahren nach einem der vorigen Ansprüche, wobeider konische Abschnitt (1 0c) den Basisabschnitt(10a) und den Spitzenabschnitt (10b) miteinanderverbindet und weicher ist, als der Basisabschnitt.

6. Verfahren nach einem der vorigen Ansprüche, wobeidie Bumps (10,10a,10b) aus Gold gestaltet sind.

7. Verfahren nach einem der vorigen Ansprüche wobeidie Kleberschicht oder der Kleberfilm (20) eine Dickevon 25 Pm oder 50 Pm aufweist, und in einem Trok-kenfilm-Format hergestellt ist oder hergestellt wor-den ist.

Revendications

1. Procédé de fixation mécanique et de connexion élec-trique simultanées d’au moins une puce nue com-portant des bosses à plot (10) sur un substrat orga-nique de support (30), comprenant les étapes con-sistant à :

(a) recouvrir le substrat organique (30), qui sup-porte une configuration imprimée conductrice,avec un film (20) qui comprend un matériau ad-hésif non conducteur isolant ;(b) aligner les bosses (10) de ladite puce ou des-dites puces sur la configuration imprimée con-ductrice sur le substrat organique (20), moyen-nant quoi les bosses à plot (10) comportent unebase (10a), une section conique (10c) et unesection de pointe (10b), ladite section de pointe(10b) étant plus molle que ladite section de base(10a) et étant sensiblement déformée lors de laréalisation d’une pression au cours de la liaisondes bosses à la configuration imprimée

conductrice ;(c) lier la puce ou les puces tournée(s) vers lebas à la configuration imprimée conductrice surle substrat organique (30) avec une températurenon supérieure à 180°C pendant environ 15 à20 secondes et une charge minimum de 20kg/cm2 les bosses à plot (10) perçant le film dematériau adhésif au cours de ladite étape deprocédé de liaison.

2. Procédé selon la revendication 1, dans lequel le ma-tériau adhésif non conducteur est un mélange ad-hésif thermodurcissable ou thermoplastique ou estun mélange de matériaux adhésifs thermodurcissa-bles et thermoplastiques.

3. Procédé selon l’une quelconque des revendicationsprécédentes, le matériau adhésif étant une feuille(20) d’un mélange de matériaux adhésifs thermo-plastiques et thermodurcissables.

4. Procédé selon l’une quelconque des revendicationsprécédentes, la force de liaison étant dans la plagede 80 g à 100 g par bosse à plot (10).

5. Procédé selon l’une quelconque des revendicationsprécédentes, dans lequel la section conique (10c)reliant la section de base (10a) et la section de pointe(10b) est plus molle que la section de base.

6. Procédé selon l’une quelconque des revendicationsprécédentes, les bosses (10 ; 10a, 10b) étant en or.

7. Procédé selon l’une quelconque des revendicationsprécédentes, le film adhésif (20) ayant une épaisseurde 25 Pm ou 50 Pm et étant fabriqué dans un formatde film sec.

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REFERENCES CITED IN THE DESCRIPTION

This list of references cited by the applicant is for the reader’s convenience only. It does not form part of the Europeanpatent document. Even though great care has been taken in compiling the references, errors or omissions cannot beexcluded and the EPO disclaims all liability in this regard.

Patent documents cited in the description

• US 4749120 A [0002] [0007]• EP 387066 A [0003]

• DE 3829538 A [0003]

Non-patent literature cited in the description

• J. ELDRING. ITAP & Flip Chip Proceedings, 1994,74-79 [0016]