Final Seminar Report Debashree

8/2/2019 Final Seminar Report Debashree

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Seminar Report

On

CLOCK-LESS CHIPS

By

DEBASHREE DEBASHRITA

DEPARTMENT OF COMPUTER SCIENCE & ENGINEERINGINDIRA GANDHI INSTITUTE OF TECHNOLOGY, SARANG

DHENKANAL, ORISSA-759146

2012-13


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CIRTIFICATE

This is to certify that Seminar Report entitledclock-less chip .This seminar was

presented satisfactorily at Department of Computer Science & Engineering,Indira

Gandhi Institute of Technology, sarang by Debashree Debashrita, 0901105043

in partial fulfillment of requirement for her 6th

semester B.Tech. This report has

not been submitted for any other examination and does not form part of any other

course undergone by the candidate.

GUIDE HOD,DEPT OF CSE

Professor S.N. Mishra Professor S.N. Mishra


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ACKNOWLEDEGEMENT

I express deep sense of gratitude to Professor S.N. Mishra, Head of the

Department, Computer Science & Engineering without whose valuable suggestions

and guidance, creation of this Seminar documentation wouldnt have been

possible. It was a great pleasure and honor to work under him and I hope many

more fruitful associations in the years to come. His kindness and affection will

remain with me forever. I also owe the gratitude due towards other faculty

members.

I would also like to thank Computer Science Branch, CSE for their help,

through provoking discussions invigorating suggestions extended to me with

immense care, zeal throughout the work.


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INDEX

TOPIC PAGE NO.

ABSTRACT 1

1. CHAPTER 1

INTRODUCTION 2

2. CHAPTER 2

CLOCKLESS APPROACH 5

2.1 Clock Limitations 5

2.1 Asynchronous View 5

3. CHAPTER 3

PROBLEMS WITH SYNCHRONOUS CIRCUITS 7

4. CHAPTER 4

ASYNCHRONOUS CIRCUITS 8

4.1 Merits of Asynchronous circuit 94.2 Speed Comparison 104.3 Power and Noise Characteristics 114.4 Other Benefits 13

5. CHAPTER 5

HOW CLOCKLESS CHIPS WORKS 14

6. CHAPTER 6

APPLICATIONS OF CLOCKLESS CHIPS 16

7. CHAPTER 7CHALLENGES 17

8. CHAPTER 8

CONCLUSION 18

9. CHAPTER 9


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REFERENCES 19

LIST OF FIGURES

1. A Brief history

2. Speed Comparison Diagram

3. Figure3

4. Figure4


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1

ABSTRACT

Clock-less chips are the electronic circuit which do not required a clock circuit or a

global clock signal, but instead need only wait for the signal that indicatecompletion of instruction and operation The clock-less chips are implemented in

the asynchronous circuit[1]. The problems with synchronous circuit such as low

performance, low speed, high power dissipation, electronic noise can be avoided

by implementing the clock-less chip in asynchronous circuit. To achieve

asynchronous as final goal one must throw away the global clock, standardize the

components and must implement a clock-less chip. This is a very new area of

research and design and testing but more scientists and engineers are dedicated to

this, then for surety it is the future technology for mobile electronic device [2].

Key word: global clock, asynchronous circuit, clocked circuit.


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THEORY

CHAPTER1

INTRODUCTION

---------------------------------------------------------------------------------------

How fast is your personal computer?

When people ask this question, they are typically referring to the frequency

of a minuscule clock inside the computer, a crystal oscillator that sets the basic

rhythm used throughout the machine. In a computer with a speed of one gigahertz,

for example, the crystal "ticks" a billion times a second. Every action of the

computer takes place in tiny steps, each a billionth of a second long. A simple

transfer of data may take only one step; complex calculations may take many steps.All operations, however, must begin and end according to the clock's timing

signals.

The use of a central clock also creates problems. As speeds have increased,

distributing the timing signals has become more and more difficult. Present-day

transistors can process data so quickly that they can accomplish several steps in the

time that it takes a wire to carry a signal from one side of the chip to the other.

Keeping the rhythm identical in all parts of a large chip requires careful design and

a great deal of electrical power. Wouldn't it be nice to have an alternative?

Clock-less approach, which uses a technique known as asynchronous logic,

differs from conventional computer circuit design in that the switching on and off

of digital circuits is controlled individually by specific pieces of data rather than by

a tyrannical clock that forces all of the millions of the circuits on a chip to march

in unison. It overcomes all the disadvantages of a clocked circuit such as slow

speed, high power consumption, high electromagnetic noise etc.

For these reasons the clock-less technology is considered as the technology which

is going to drive majority of electronic chips in the coming years.


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3

A BRIEF HISTORY


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4

CONCEPT OF CLOCKS

The clock is a tiny crystal oscillator that resides in the heart of every

microprocessor chip. The clock is what which sets the basic rhythm used

throughout the machine. The clock orchestrates the synchronous dance of electrons

that course through the hundreds of millions of wires and transistors of a modern

computer.

Such crystals which tick up to 2 billion times each second in the

fastest of todays desktop personal computers, dictate the timing of every circuit inevery one of the chips that add, subtract, divide, multiply and move the ones and

zeros that are the basic stuff of the information age.

Conventional chips (synchronous) operate under the control of a

central clock, which samples data in the registers at precisely timed intervals.

Computer chips of today are synchronous: they contain a main clock which

controls the timing of the entire chips.

One advantage of a clock is that, the clock signals to the devices of

the chip when to input or output. This functionality of the synchronous design

makes designing the chip much easier. There are problems that go along with theclock, however.

Clock speeds are now in the gigahertz range and there is not much

room for speedup before physical realities start to complicate things. With a

gigahertz clock powering a chip, signals barely have enough time to make it across

the chip before the next clock tick. At this point, speedup up the clock frequency

could become disastrous. This is when a chip that is not constricted by clock

speeds could become very valuable.


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CHAPTER2

CLOCKLESS APPROACH

---------------------------------------------------------------------------------------------------------------------

2.1CLOCK LIMITATIONS

There are problems that go along with the clock, however.

Clock speeds are now in the gigahertz range and there is not much room for

Speed up before physical realities start to complicate things. With a gigahertz

Clock powering a chip, signals barely have enough time to make it across the

Chip before the next clock tick. At this point, speedup up the clock frequency

could become disastrous. This is when a chip that is not constricted by clock

speeds could become very valuable.One can create a clock that is so fast and it sends its timing signals to the

logic circuits which are governed by the clock timing signals. These logic

circuits are supposed to respond to every tick of the clock and yet when they can

compile to match the speed then logic circuits will be not optimum according to

the speed of clock and hence the input and output can go incorrect. This will

result hardware problem since one has to assemble chips to achieve the speed of

clock and hence much more complicated situation arise.

2.2 ASYNCRONOUS VIEW

By throwing out the clock, chip makers will be able to escape from huge

Power dissipation. Clock-less chips draw power only when there is useful work

to do, enabling a huge savings in battery-driven devices.

Like a team of horses that can only run as fast as its slowest member, a

clocked chip can run no faster than its most slothful piece of logic; the answer

isnt guaranteed until every part completes its work. By contrast, the transistors

on an asynchronous chip can swap information independently, without needing

to wait for everything else. The result? Instead of the entire chip running at the

speed of its slowest components, it can run at the average speed of allcomponents. At both Intel and Sun, this approach has led to prototype chips that

run two to three times faster than comparable products using conventional

circuitry.

Another advantage of clock-less chips is that they give off very low levels of

Electromagnetic noise. The faster the clock, the more difficult it is to prevent a

device from interfering with other devices; dispensing with the clock all but


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Eliminates this problem. The combination of low noise and low power

consumption makes asynchronous chips a natural choice for mobile devices.


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CHAPTER3

CIRCUITS PROBLEMS OF SYNCHRONOUS

------------------------------------------------------------------------------------

One problem is speed. A chip can only work as fast as its slowest

component. Therefore, if one part of the chip is especially slow, the other parts of

the chip are forced to sit idle. This wasted computing time is obviously detrimental

to the speed of the chip.

New problems with speeding up a clocked chip are just around the

corner. Clock frequencies are getting so fast that signals can barely cross the chip

on one clock cycle. When we get to the point where the clock cannot drive the

entire chip, we'll be forced to come up with a solution. One possible solution is asecond clock, but this will incur overhead and power consumption, so this is a poor

solution. It is also important to note that doubling the frequency of the clock does

not double the chip speed, therefore blindly trying to increase chip speed by

increasing frequency without considering other options is foolish.

The other major problem with a clocked design is power consumption. The

clock consumes more power than another other component of the chip. The most

disturbing thing about this is that the clock serves no direct computational use. A

clock does not perform operations on information; it simply orchestrates the

computational parts of the computer.

New problems with power consumption are arising. As the number of

transistors on a chip increases, so does the power used by the clock. Therefore, as

we design more complicated chips, power consumption becomes an even more

crucial topic. Mobile electronics are the target for many chips. These chips need to

be even more conservative with power consumption in order to have a reasonable

battery lifetime.

The natural solution to the above problems, as you may have guessed,is to eliminate the source of these headaches: the clock.


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CHAPTER4

ASYNCHRONOUS CIRCUIT---------------------------------------------------------------------------------

Clock-less (also called asynchronous, self timed or event driven) chips dispense

with the timepiece. The figure below gives an idea of working of an asynchronous

circuit. In this particular scheme (which is called a duel rail circuit which will be

discussed later), data moves instead under the control of local "handshake" signals

(lines below) that indicate when work has been completed and is ready for the next

logic operation.

As we can see above there is the usual logical circuitry and instead of a

clock signal which controls the circuit, there are two lines on the top and bottom.

The wires are used to transfer the data bits and the control bits together. So there is

no separate control signal going across the circuit. The control signal is encoded

within the data that is being transferred. This control signals act as handshaking

and handoff signals which indicates when the component is ready for the next

logical operation.

There are different ways to implement an asynchronous circuit. The

next part is about various types of implementation.


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4.1MERITS OF ASYNCHRONOUS CIRCUITS

There are mainly three advantages of clockless design. They are

Increase in speed. Reduced power consumption. Less electromagnetic noise.

The first of these advantages is speed. Chips can run at the average

speed of all its components instead of the speed of the slowest component, as was

the case with a clocked design. The transistors on an asynchronous chip can swap

information independently, without needing to wait for everything else. At both

Intel and Sun micro systems, this approach has led to prototype chips that run twoto three times faster than comparable products using conventional circuitry.

Therefore the speed of an asynchronous design is not limited by the size of the

chip. An example of how much an asynchronous design can improve speed is the

asynchronous Pentium designed by Intel in 1997 that runs three times as fast as the

synchronous equivalent.

Another crucial advantage of clock-less chips is the reduction in

power consumption. The reason for this is that asynchronous chips use power only

during computations, while a clocked circuit is always running. The Intel Pentium

referred above ran three times faster than clocked equivalent with half the power.

The third advantage of the clock-less design is that it produces less

electromagnetic noise which interferes with the working frequencies of other

signals.


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4.2SPEED COMPARISON

The above figure of the bucket brigade can be used to describe the

flow of data in a computer. A synchronous computer system is like a bucket

brigade in which each person follows the tick tock rhythm of a clock. When the

clock ticks, each person pushes a bucket forward to the next person down the line(top). When the clock tocks, each person grasps the bucket pushed forward by the

preceding person (middle). An asynchronous system, in contrast, is like an

ordinary bucket brigade: each person who holds a bucket can pass it down the line

as soon as the next persons hands are free.

It is quite evident from the above metaphor, why the clock-less chip is

faster and effective. The clock-less chips can run on the average speed of all of its

components rather than adopting the speed of the slowest member. This is because

of the fact that an action is not restricted by the rules like those in a clocked design.


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4.3 POWER & NOISE CHARECTERISTICS

POWER

The above graphics is obtained from the Philips official website. It

illustrates the power saving character of the clockless chip. This is an experiment

to find out the heat emitted by a chip by placing it under special kind of light. The

chip on the left side is a synchronous chip and the one to the right is its

asynchronous equivalent. The red spots on the chip indicate the positions where

heat is dissipated. It is clear from the figure that the synchronous emit more heat asit has the more number of red spots on the light emission measurements.

It is clear that a chip which produces the more heat would consume

more power. Clearly synchronous chips consume more power than the

asynchronous equivalent.

The reason for this is that asynchronous chips use power only during

computations, while a clocked chip always consumes power because the chip is

always running. The clock together with its timing circuits not only take up a good

area of the chip, but also account for 30% of the total power consumed by the chip.

So removing this would surely give an increase in life of the battery. It is also

important to note that the idle parts of a clockless chip consume negligible amount

of power.


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The above said reason is more applicable in the case of mobile electronics where a

battery is used to drive the chip. One would think that it is not much of an issue

when we consider the case of a computer or other devices which can be plugged.

But in this case the chip can cut the cost needed in the design of these equipments

by reducing the need for cooling fans, air-conditioning and other cooling

equipments in order to prevent overheating. The amount of power saved will

depend on the machines pattern of activity. Systems with parts that actoccasionally benefit more than systems that act continuously. Most computers have

components, such as the floating-point arithmetic unit, that often remain idle for

long periods.

NOISE

Now a day the demand for mobile devices is getting higher and

higher. Everything around is becoming wireless. These devices work by sending

and receiving radio signals. When a clocked circuit is used in these types of

devices the noise generated by the large frequency of the clock interferes with the

working frequency of the mobile devices. In order to avoid errors caused by these

noise signals, designers would not be free to provide the scale of integration they

wish.

Asynchronous systems produce less radio interference than

synchronous machines. Because a clocked system uses a fixed rhythm, it

broadcasts a strong radio signal at its operating frequency and at the harmonics of

that frequency. Such signals can interfere with cellular phones, televisions and

aircraft navigation systems that operate at the same frequencies. Asynchronous

systems lack a fixed rhythm, so they spread their radiated energy broadly across

the radio spectrum, emitting less at any one frequency.


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4.4 OTHER BENEFITES

Yet another benefit of asynchronous design is that it can be used to

build bridges between clocked computers running at different speeds. Many

computing clusters, for instance, link fast PCs with slower machines. These

clusters can tackle complex problems by dividing the computational tasks among

the PCs. Such a system is inherently asynchronous: different parts march to

different beats. Moving data controlled by one clock to the control of another clock

requires asynchronous bridges, because the data may be "out of sync" with the

receiving clock.

Finally, although asynchronous design can be challenging, it can alsobe wonderfully flexible. Because the circuits of an asynchronous system need not

share a common rhythm, designers have more freedom in choosing the system's

parts and determining how they interact. Moreover, replacing any part with a faster

version will improve the speed of the entire system. In contrast, increasing the

speed of a clocked system usually requires upgrading every part.

A final advantage of the clockless chip is the ability to provide

superior encryption. This is because there is no way for a hacker to track regularly

timed signals, which are given away by the clock in a synchronous design. The

hackers do not know what to look at. This has significant potential as security

becomes an increasing priority. This becomes even more critical as computer all

over the world become more closely connected and are sharing confidential

material.

Improved encryption makes asynchronous circuits an obvious choice

for smart cardsthe chip-endowed plastic cards beginning to be used for such

security sensitive applications as storage of medical records, electronic funds

exchange and personal identification.


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CHAPTER5HOW CLOCKLESS CHIPS WORKS

----------------------------------------------------------------------------------------------------

Beyond a new generation of design-and-testing equipment, successful

development of clock-less chips requires the understanding of asynchronous

design. Such talent is scarce, as asynchronous principles fly in the face of the

almost every university teaches its engineering students. Conventional

chips can have values arrive at a register incorrectly and out of sequence; but in

a clock-less chip, the values that arrive in registers must be correct the first time.

One way to achieve this goal is to pay close attention to such details as the

lengths of the wires and the number of logic gates connected to a given register,

thereby assuring that signals travel to the register in the proper logical sequence.

But that means being far more meticulous about the physical design thansynchronous designers have been trained to be.

An alternative is to open up a separate communication channel on the chip.

Clocked chips represent ones and zeroes using low and high voltages on a single

wire, "dual-rail" circuits, on the other hand, use two wires, giving the chip

communications pathways, not only to send bits, but also to send "handshake"

signals to indicate when work has been completed. Fair additionally proposes

replacing the conventional system of digital logic with what known as "null

convention logic," a scheme that identifies not only "yes" and "no," but also "no

answer yet"-a convenient way for clock-less chips to recognize when anoperation has not yet been completed. All of these ideas and approaches are

different enough that executing them could confound the mind of an engineer

trained to design to the beat of a clock. Its no surprise that the two newest

asynchronous startups, Asynchronous Digital Devices and Self-Timed

Solutions, are populating now, and clock-less-chip research has been going on

the longest.

For a chip to be successful, all three elements-design tools, manufacturing

efficiency and experienced designers-need to come together. The asynchronous

cadre has very promising ideas.

There is now way one can obtain pure asynchronous circuits to be used in thecomplete design of the system and this is one of major barrier of clock-less

implementation but the circuits were successfully standardized and hence they

do not have to be in synchronous mode. And hence handshakes were the

solution to overcome synchronization. One component which needs to

communicate with the other uses the handshake signals to achieve the

establishment of connection and then with set up the time at which is going to


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send data and at the other side another component will also use the same kind of

handshakes to harden the connection and wait for that time to receive data.

In circuits implemented by clock less chips, data do not have to move at

Random and out of order as in synchronous in which the movement of data is no

essential. In asynchronous circuits data are treated as very important aspect

and hence do not move at any time they only and only move when are required

to move in case such as transmission between several components. This

technique has offered low power consumption and low electromagnetic noise

and also there will of course be smooth data streaming.


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CHAPTER6APPLICATIONS

----------------------------------------------------------------------------------------------------

Clock-less design is inevitable in the future of chip design because of the two

major advantages of speed and power consumption, but where will we first see

these designs in use?

The first place we'll see, clock-less designs in the lab. Many prototypes

will be necessary to create reliable designs. Manufacturing techniques must also be

improved so the chips can be mass-produced.

The second place we'll see these chips are in mobile electronics. This

is an ideal place to implement a clock-less chip because of the minimal powerconsumption. Also, low levels of electromagnetic noise creates less interference;

less interference is critical in designs with many components packed very tightly,

as is the case with mobile electronics.

The third place is in personal computers (PCs). Clock-less designs

will occur here last because of the competitive PC market. It is essential in that

market to create an efficient design that is reasonably priced. A manufacturing cost

increase of a couple cents per chip can cause an entire line of computers to fail

because of the large cost increase passed onto the customer. Therefore, themanufacturing process must be improved to create a reasonably priced chip.

A final place that asynchronous design may be used is encryption devices.

The reason for this is there are no regularly timed signals for hackers to look for.

This becomes even more critical as computer all over the world become more

closely connected and are sharing confidential material. They will be also used in

smart cars as they provide excellent security.


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CHAPTER7

CHALLENGES

----------------------------------------------------------------------------------------------------

1. Interfacing between synchronous and asynchronous

. Many devices available now are synchronous in nature.

. Special circuits are needed to align them.

2. Lack of expertise.

3. Lack of tools.

4. Engineers are not trained in these fields.

5. Academically, no courses available.


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CHAPTER8CONCLUSION

--------------------------------------------------------------------------------------------

Why isnt it popular?

Why doesnt industry currently use asynchronous designs (with ahandful of exceptions)? The main cause is risk. Asynchronous design techniques

are sometimes seen as unproven, despite a number of academic (and industry)

successes. Further, any asynchronous design will incur additional cost in training

engineers to use techniques they didnt learn in school. Finally, tool developmentis likely seen as an obstacle.

Moreover, at least up to now, industry has been getting by without

asynchronous design. So far, the clocked designs have been feasible (ifoccasionally expensive), and low power does not yet dominate demand.

Should it be used?My conclusion is an emphatic yes! Clocks are getting faster, while

chips are getting bigger, both of which make clock distribution harder. Chips are

also becoming more heterogeneous, with functions like memory and network

interfaces being considered, all of which complicates the global timing analysis

necessary for a synchronous design. Finally, we are entering an age when

processors will be just about everywhere, and this will require very low power

designs. Its just not practical to expect a clean, skew-free clock for every (say)

piece of clothing with a processing element.

But this can only happen if more focus, especially at the university level, is

given to asynchronous design. Most of todays designers dont understand it wellenough to use it, and may even regard it with suspicion. It is certainly a challenge,

but just as the software community is moving towards more concurrency, the

hardware community must move to incorporate asynchronous logic.


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CHAPTER9

REFERENCES

---------------------------------------------------------------------------------------

1. www.projects-forum.com: clock-less chip, accessed on 2.04.2012

2. www.seminarsonly.com: clock-less chip, accessed on15.03.2012

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Final Seminar Report Debashree