Final Report Sd

7/24/2019 Final Report Sd

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Design of a Fully On-Chip LDO with Improved

Transient Response for Analog Subsystems

Submitted in partial fulfillment of the requirements

of the degree of

Master of Technology

in

VLSI System Design

By

Saurabh Dixit

Roll No: 124570

Supervisor

Dr. Patri Sreehari Rao

Associate Professor

Department of Electronics and Communication Engineering

NATIONAL INSTITUTE OF TECHNOLOGY

WARANGAL - 506 004

2014


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Dissertation Approval for M. Tech.

This Project Work entitled Design of a Fully On-Chip LDO with Improved Transient

Response for Analog Subsystemsby Saurabh Dixit is approved for the degree of Master of

Technology in VLSI System Design.

Examiners

_________________________

_________________________

_________________________

Supervisor

Dr. Patri Sreehari Rao

Associate Professor

Chairman

Prof.N.V.S.N. Sarma

Date: ____________

Place: ___________


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Declaration

I declare that this written submission represents my ideas in my own words

and where others ideas or words have been included; I have adequately

cited and referenced the original sources. I also declare that I have adhered

to all principles of academic honesty and integrity and have not

misrepresented or fabricated or falsified any idea/data/fact/source in my

submission. I understand that any violation of the above will be cause for

disciplinary action of the institute and can also evoke penal action from thesources which have thus not been properly cited or from whom proper

permission has not been taken when needed.

_____________________

(Signature)

_____________________

(Name of the student)

_____________________

(Roll No.)

Date: ___________


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iii

Abstract

Modern power management System-on-a-Chip (SoC) design demands for fully

integrated solutions in order to decrease certain costly features such as the total chip area and

the power consumption while maintaining or increasing the fast transient response to signal

variations. Low-Dropout (LDO) voltage regulators, as power management devices, must

comply with these recent technological and industrial trends.

An ultra low power capless low-dropout voltage regulator with resistive feedback

network and a gain enhanced feed forward path compensation strategy is proposed. The

feedforward path used enhances the fast load and line LDO transient responses.

The designed LDO is for 1.2V output voltage and full load current of 100mA with a

load capacitance of 100pF, has a dropout voltage of .2V, quiescent current of 69 A. The

transient response is improved using the fast feed forward path and the compensation

capacitor. Reference voltage is generated by using an accurate band gap reference circuit

(.8V).


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Contents

Abstract ........................................................................................................................ iii

List of Figures .............................................................................................................. vi

List of Tables ............................................................................................................... vii

Chapter 1 Introduction ................................................................................................. 1

1.1

Role of regulators in power management ......................................................... 1

1.2 External v/s Internal Compensation ................................................................. 3

1.3

Internal Compensation ...................................................................................... 4

1.4

Problem Definition ........................................................................................... 4

1.5

Motivation ........................................................................................................ 5

1.6 Organisation of the Report ............................................................................... 5

Chapter 2 Review of Literature ................................................................................... 6

2.1

Capacitor-less LDO voltage regulator .............................................................. 6

2.2

State of the art ................................................................................................... 7

2.2.1 Slew-Rate Enhancement Compensation ................................................. 8

2.2.2

Buffered Flipped Voltage Follower Compensation ................................ 9

2.2.3

Reversed Nested Miller Compensation ................................................. 10

2.2.4 Q-Reduction Compensation .................................................................. 11

2.2.5

Pole-Zero Cancellation Compensation ................................................. 12

2.2.6

Multipath Miller Zero cancellation compensation (MMZCC) ............. 12

2.2.7 Gain-Enhanced feed-Forward path compensation (GFPC) .................. 13

Chapter 3 LDO Characterisation .............................................................................. 15

3.1 Conventional LDO topology .......................................................................... 15

3.2

Pass Device ..................................................................................................... 17

3.3 Error Amplifier ............................................................................................... 18

3.4

Comparator ..................................................................................................... 20

3.5

Band Gap Reference ....................................................................................... 24

3.6

Low Dropout Regulator Characterization ...................................................... 25


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3.6.1 Peak Overshoot and Undershoot ........................................................... 25

3.6.2

Dropout Voltage .................................................................................... 26

3.6.3

Line and Load Regulation ..................................................................... 26

3.6.4

Settling Time ......................................................................................... 26

3.6.5

Loop Gain ............................................................................................. 26

3.6.6

PSRR ..................................................................................................... 26

3.7 LDO Specifications ........................................................................................ 27

Chapter 4 Design and Implementation...................................................................... 28

4.1 Overview ........................................................................................................ 28

4.2

Pass Transistor Design ................................................................................... 28

4.3 Feedback Resistor Design .............................................................................. 30

4.4 Band Gap Reference Design .......................................................................... 31

4.5

Error Amplifier Design ................................................................................... 34

Chapter 5 Results and Discussion .............................................................................. 35

5.1 Loop Gain Simulations ................................................................................... 35

5.2 Transient response Simulations ...................................................................... 36

5.3

Load regulation simulation ............................................................................. 38

5.4 PSR simulations .............................................................................................. 38

5.5 Band Gap Reference TC simulation ............................................................... 39

5.6

Comparison with the Previous works ............................................................. 40

Chapter 6 Conclusions ................................................................................................ 41

6.1 Conclusion ...................................................................................................... 41

6.2

Future Scope ................................................................................................... 41

Literature Cited ........................................................................................................... 43

Acknowledgements ...................................................................................................... 46


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vi

List of Figures

Fig. 1.1 Typical cell (i.e. Nickel-Metal Hydride) voltage discharge curve over load,

considering the temperature and discharge rate to be constant. ................................................. 2

Fig. 2.1 Slew rate enhancement topology................................................................................... 8

Fig. 2.2 Buffered flipped voltage follower topology. ................................................................. 9

Fig. 2.3 Reverse Nested Miller Compensation Topology. ...................................................... 10

Fig. 2.4 Q-Reduction Compensation Topology. ..................................................................... 11

Fig. 2.5 Pole-Zero Cancellation Compensation Topology. ..................................................... 12

Fig. 2.6 MMZCC topology. ..................................................................................................... 13

Fig. 2.7 GFPC topology. .......................................................................................................... 13

Fig. 3.1 Conventional LDO topology. ..................................................................................... 16

Fig. 3.2 Error amplifier topology used in the proposed LDO design [2]. ............................... 19

Fig. 3.3 Example of Preamplifier and latch. ............................................................................ 22

Fig. 3.4 An improved Preamplifier. .......................................................................................... 22

Fig. 3.5 Comparator topology used as the feed forward path.................................................. 23

Fig. 3.6 Principle of BGR. ....................................................................................................... 25

Fig. 4.1 Schematic diagram of the proposed capless LDO regulator. ..................................... 29

Fig. 4.2 Pass Transistor design. ............................................................................................... 29

Fig. 4.3 Feedback resistor network design. ............................................................................. 31

Fig. 4.4 Schematic of Band Gap Reference Circuit. ............................................................... 32

Fig. 4.5 Band gap reference circuit with curvature compensation. ......................................... 33

Fig. 5.1 Loop gain and Loop phase plots. ................................................................................ 36

Fig. 5.2 Load transient response plot for load varying from 0 to 100mA (rise time of 1s). .. 37

Fig. 5.3 Load transient response plot for settling time measurement. ...................................... 37

Fig. 5.4 Load regulation plot .................................................................................................... 38

Fig. 5.5 Power Supply Rejection plot. ..................................................................................... 39

Fig. 5.6 Plot for Temperature Coefficient over temperature range -40 to 80 C. .................... 39


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List of Tables

Table 3.1 LDO Parameters. ..................................................................................................... 17

Table 3.2 Comparison of Pass element structures .................................................................... 18

Table 3.3 LDO Specifications. ................................................................................................ 27

Table 5.1 Comparison with the recent reported prior-art results .............................................. 40


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Chapter 1

Introduction

1.1 Role of regulators in power management

LDO's have become an essential part of many battery powered systems. Supplying

and conditioning power are the most fundamental functions of an electrical system. A loading

application, be it a cellular phone, pager, or wireless sensor node, cannot sustain itself without

energy, and cannot fully perform its functions without a stable supply. The fact is

transformers, generators, batteries, and other off-line supplies incur substantial voltage and

current variations across time and over a wide range of operating conditions. They are

normally noisy and jittery not only because of their inherent nature but also because high-

power switching circuits like central-processing units (CPUs) and digital signal-processing

(DSP) circuits usually load it. These rapidly changing loads cause transient excursions in the

supposedly noise-free supply, the end results of which are undesired voltage droops and

frequency spurs where only a dc component should exist. The role of the voltage regulator is

to convert these unpredictable and noisy supplies to stable, constant, accurate, and load-

independent voltages, attenuating these ill-fated fluctuations to lower and more acceptable

levels. Area is one of the biggest issues in portable devices, such as music players. Hence an

LDO, which is fully-integrated with no external capacitors, is in a great demand.


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The regulation function is especially important in high-performance applications

where systems are increasingly more integrated and complex. A system-on-chip (SoC)

solution, for instance, incorporates numerous functions, many of which switch simultaneously

with the clock, demanding both high-power and fast-response times in short consecutive

bursts. Not responding quickly to one of these load-current transitions (i.e., load dumps)

forces storage capacitors to supply the full load and subsequently suffer considerable transient

fluctuations in the supply. The bandwidth performance of the regulator, that is, its ability to

respond quickly, determines the magnitude and extent of these transient variations.

The important issue with any battery powered system is the power consumption. A

real-time clock, which is an important part of mobile phones, requires an extremely long

battery life, which implies an LDO in the mobile phone should use extremely low battery

power. This is only possible when the LDO uses extremely low quiescent current. Long

battery life is also important in many implantable electronic devices, such as pacemakers.

Once implanted in a body, it has battery power as its only source, which can last a long time

only if the LDO dissipates extremely low power. Furthermore as can be observed in Fig. 1.1,

the voltage supplied by a single cell is variable by nature. Thus, any battery, as a composition

of cells, also inherits this characteristic which makes this an important issue in power

management design.

Fig. 1.1 Typical cell (i.e. Nickel-Metal Hydride) voltage discharge curve over load,

considering the temperature and discharge rate to be constant.

Regulators also protect and filter integrated circuits (ICs) from exposure to voltages

exceeding junction-breakdown levels. The requirement is more stringent and acute in

emergent state-of-the-art technologies whose susceptibility to breakdown voltages can be less

than 2 V. The growing demand for space-efficient, single-chip solutions, which include SoC,

system-in-package (SiP), and system-on-package (SoP) implementations, drives process


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technologies to finer photolithographic and metal-pitch dimensions. Unfortunately, the

maximum voltage an IC can sustain before the onset of a breakdown failure declines with

decreasing dimensions and pitch because as the component density increases, isolation

barriers deteriorate.

References, like regulators, generate and regulate accurate and stable output voltages

that are impervious to variations in the input supply, loading environment, and various

operating conditions. Unlike regulators, however, references do not supply substantial dc

currents. Although a good reference may shunt positive and negative noise currents, its total

load-current reach is still relatively low. In practice, references supply up to 1 mA and

regulators from 5 mA to several amps.

1.2 External v/s Internal Compensation

The overriding advantages of externally compensated regulators are high output

capacitance CO and high error-amplifier bandwidth pA. High CO values, on one hand, increase

the regulators ability to suppress fast and high-power load dumps and high pA frequencies, on

the other, extend good low-frequency PSR performance to higher frequencies. Maintaining pA

at high frequencies to guarantee stable operating conditions, however, is challenging,especially when considering the error amplifier must drive the parasitic capacitance the

necessarily large power pass device presents. Internally compensated circuits reap the

integration benefits of lower output capacitances, more easily conforming to the total on-chip

integration demands of state-of-the-art portable, battery-powered solutions. The costs of on

chip integration, however, are lower output power and more stringent stability constraints, as

output pole PO has a tendency to migrate to lower frequencies during light loading conditions.

Low quiescent currents, when considering extended battery-life operation, necessarily

pull parasitic poles to lower frequencies, limiting the extent to which f0dBshould increase to

maintain stability. To aggravate matters, the presence of ZESR and pB extends f0dB and

decreases the number of decades the loop gain can drop at 20 dB per decade from its low-

frequency value, which results in relatively low loop gains when compared to standard op

amps, and by translation, limited load- and line-regulation performance. Therefore, generally

speaking, irrespective of the compensation strategy, increasing both loop-gain and bandwidth

under low quiescent-current restrictions compromises stability, which explains why loop

gains normally fall below 5060 dB and nominal unity-gain frequencies below 0.51 MHz .


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1.3 Internal Compensation

The need for higher power levels and quicker response times are as imminent as the

demand for higher integration, which is where internal compensation schemes thrive. The factis packing more features into a single IC introduces uncorrelated noise into the supply,

reducing, as a result, the signal-to-noise-ratio (SNR) performance of sensitive analog

electronics attached to that supply. Dedicated on-chip regulators help in this respect because

they decouple the otherwise common noise from sensitive loads. Having no external pad or

pin to rely on, though, the challenge in designing these point-of-load (PoL) regulators is the

unavailability of off-chip capacitors. Fortunately, the lower power levels these targeted loads

demand (and their smaller large-signal changes in load) offset some of the expense (i.e.,

silicon real estate) associated with on-chip capacitors, as lower capacitances may now satisfy

the relatively modest needs of a lighter load.

Low-dropout performance in dedicated on-chip supplies, as it turns out, is not always a

requirement because the power dissipated by the rest of the system, on average, often

overwhelms that of the particular load in question. If other considerations allow, using this

argument to ease dropout requirements is important because higher dropout n-type power

devices outperform their lower dropout p-type counterparts in speed and consequently in on-

chip capacitance silicon-area requirements. Headroom, by the way, may sometimes constrain

dropout voltages to low values, like when one switching regulator supplies the entire IC and

its output is already low to mitigate the losses associated with the high-power sectors of the

system.

1.4 Problem Definition

The idea is to design a Fully On-chip capacitorless Low Dropout Regulator having

fast transient response. The designed LDO should be stable for the entire range of load

variation i.e. 0 to 100mA. The LDO should be suitable to power analog subsystems utilizing

very low quiescent current. The LDO should provide constant output voltage with high load

regulation.


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1.5 Motivation

Knowing that the market demand for consumer electronics is growing exponentially the

electronic components used in the fabrication of these electronic devices will also growexponentially so ultimately this demand will also fall over the basic electronic components

such as the LDOs.

High-performance ultra low power LDOs are part of the response to this emerging need

of efficient and robust electronic components. Concerning LDOs, many researchers are

proposing different topologies with different compensation techniques.

The motivation of this dissertation is to better understand the compensation techniques

to enhance the transient characteristics and to propose an LDO compensation technique based

on a new multi-path feed forward topology, Gain Enhanced Feed Forward Path

Compensation.

1.6 Organisation of the Report

This report is started with the introduction of power management. Second chapter deals

with literature survey on LDO regulators. Third chapter deals with characterization of LDO.

Chapter 4 deals with design and implementation of the LDO. Simulation results of the LDO

are given in chapter 5. Chapter 6 discusses the conclusion and the future scope for this work.


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Chapter 2

Review of Literature

2.1 Capacitor-less LDO voltage regulator

Capacitor-less LDOs, are an alternative to the conventional LDO voltage regulator that

aim to circumvent some of the non-desirable characteristics of the latter voltage regulator.

The conventional voltage regulation has the advantage of lower voltage operation and higher

power efficiency. However, its high output impedance raises instability issues. To assure a

satisfactory transient response it requires an output capacitor in the microfarad range, large in

SoC context. This large capacitor creates a low frequency pole which becomes dominant and

severely slows down the LDO dynamic behaviour [8, 9]. This poses a problem and

contradicts the modern design trends.

Removing the large capacitor from the conventional LDO and replacing it by a smaller

one in the range of ten to hundreds of picofarad [10], easily implemented on-chip, a more

suitable LDO is achieved according to modern design trends. Furthermore, if the pole created

by this smaller capacitor is far higher, frequency wise, than the open loop Unit Gain

Frequency (UGF), a higher close loop bandwidth is achieved which is very advantageous. On

the other hand, removing the large capacitor leads to other constraints of the LDO responses

and performance. With the aforementioned replacement, some output filtering properties are


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lost, by comparison to the circuit response with the larger output capacitor. The small

capacitor acts as a charge source during fast transients as well but in a much smaller scale,

therefore the transient responses of the LDO degrade. The lower oscillations on the

conventional LDO output voltage are now higher oscillations in the capless LDO output

voltage, considering the same input signals for both the conventional and capless LDO.

The pole set by the smaller capacitor is no longer the dominant one. As this pole is now

located in higher frequencies, the LDO, seen from its output, is no longer a stable system. The

dominant pole now depends on each topology, being set usually by the error amplifier or

buffer connected to the pass device gate. The system stability will be regained as soon as the

dominant pole and zero are shifted back to locations well below the UGF and the non-

dominant poles are shifted forth to locations well beyond the UGF. To adapt this capless

topology and improve it dynamically, when possible, a frequency compensation technique is

required to shift the poles and zero back and forth.

2.2 State of the art

Since high-performance low power LDOs are growing in demand and popularity among

mixed-signal system designers, many researchers have been studying different compensationtopologies and techniques for LDO stabilization without the large external capacitor, a more

attractive implementation of LDOs for SoC applications.

Capacitorless LDOs, also known as capless LDOs, are a step forward in the LDO

evolution in a way that less materials are used, a fewer number of input/output pads are

required and thus the total silicon area of the LDO can be minimized while maintaining the

desired LDO responses.

The most recent compensations techniques and strategies to stabilize and improve the

capacitorless LDO responses, in other words, the response of LDOs without the large external

capacitor, are presented in this section. A brief analysis is also presented for each technique

and their advantages and disadvantages are also pointed out. All of the presented strategies

rely on at least one sensing loop of the ratio of output current, or voltage. The sensed

parameter is then fed-back to the error amplifier.


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2.2.1 Slew-Rate Enhancement Compensation

For LDO designers, it is a well known fact that the slew-rate at the gate of the pass

device limits the load transient response of the regulator [11]. The slew-rate enhancement

compensation circuit, used to overcome this issue, implements a technique that provides the

necessary dynamic current to quickly charge and discharge the gate capacitance of the pass

device, improving its transient response. The dynamic current, supplied by the enhancement

circuit, boosts the response of the pass device to signal variation but also incurs in a

temporary increase of quiescent current. In order to maintain the low overall consumption and

high efficiency of the LDO, this transient should be as narrower as possible and the slew-rate

enhancement circuitry should be completely turned off in steady state.

Slew-Rate (SR) enhancement compensation involves two types of electronic circuits:

the sensing circuit and the driving circuit. In Fig. 2.1 the sensing circuitry adopts a voltage

detection method based on capacitive coupling and is responsible for tapping the output node

voltage and detect undershoot and overshoot signal variations. If any, then the driving

circuitry is enabled acting on the pass device accordingly to the output node voltage detection.

Fig. 2.1 Slew rate enhancement topology

Note that VG is the pass devices gate voltage.

The core of this technique is the sensing circuit which must be able to detect and act

on signal variations. C1 and R1 implement a high-pass circuit responsible for the output

signal variation detection.


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2.2.2 Buffered Flipped Voltage Follower Compensation

Hua Chen and Ka Nang Leung proposed a buffered flipped voltage follower study

based on a single transistor-control LDO. This technique was built and supported by other

previous published studies on flipped voltage followers such as the cascaded and level shifted

flipped voltage follower.

The topology in Fig. 2.2 combines the best merits of the two referred compensations.

It alleviates the minimum loading requirements of the basic flipped voltage follower LDO,

provides a large driving force at the gate of the pass device and boosts the loop gain in order

to improve load regulation [12]. Moreover, others introduced the dynamic biasing technique

to the topology present in the Fig. 2.2 achieving improved load regulation results. The SR

issue was also improved by the push pull output stage [8].

Fig. 2.2 Buffered flipped voltage follower topology.

MShas a key role in the aforementioned vantages. MSis responsible for reducing the

impedance seen at the pass devices gate and for boosting the loop gain of the LDO, sufficient

conditions to stabilize the LDO. The drain voltage of MCis determined by the voltage biasing

at the gate of transistor, MB, and by Vgs (MB) which are independent of the uncertain loading

conditions. The minimum loading constraint is therefore inexistent. VCTRL holds relatively

constant over time as it follows the Band Gap output voltage, Vref, through a voltage follower

buffer, not present in Fig. 2.2. As to the VBconstraints, the biasing voltage cannot be set to

low or the IN transistor will enter the linear region and cannot be set to high or MBtransistor

will enter the linear region. With this topology and the restricted setting of parameters, a 20 to


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40 A quiescent current is easily achieved, which for ultra low-power applications is not

ideal.

2.2.3

Reversed Nested Miller Compensation

Nested Miller compensation topologies are usually a three stage amplifier topologies

that exploits feedback loops and Miller effects through capacitor compensation use. Fig. 2.3

represents a Reversed Nested Miller Compensation.

The stability is achieved by splitting the low frequency poles in the frequency domain

by using compensation capacitors CC1 and CC2 in the feedback loop. This technique achieves

the desired phase margin and required transient response. On the other hand, bandwidth and

slew-rate trade-offs take place [13].

Fig. 2.3 Reverse Nested Miller Compensation Topology.

Reversed active feedback frequency compensation and reversed nested Miller

compensation with nulling resistor are two evolutions of the topology shown in Fig. 2.3 and

operate with the same principles already introduced. The major differences between these two

topologies and the one presented in Fig. 2.3 are the feedback paths which includetransconductance blocks along with passive components, the second stage Operational

Transconductance Amplifier (OTA), which is the only inverting one, and finally the inherent

bandwidth improvement due to the fact that the inner compensation capacitor, CC2, does not

load from the output node. All these techniques require a 500 pF capacitor at the output node

for stability purposes which for low power environment is not ideal.


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2.2.4 Q-Reduction Compensation

With the removal of the large external capacitor and with the low power requirements,

both set by the latest SoC trends, the non-dominant poles start to suffer some changes such as,

higher Q values and locations closer the UGF [14]. A new compensation is shown in Fig. 2.4

that aims to reduce the high Q values of the poles and shift the poles locations to higher

frequencies moving them away from the UGF.

This topology consists in a three stage circuit. The first stage is the differential

amplifier, as input stage, the second stage is a non-inverting gain stage and finally the pass

device as the third stage. The first stage also has a current buffer to supply the required

current to the second stage.

This topology uses a Miller compensation capacitor, Cm1, a feed-forward capacitor to

introduce a left-half-plane zero, Ccf, and gate-drain capacitor, Cgd, to stabilize the LDO

regulator. With this technique higher values of phase margin are achieved for a given

bandwidth.

The current buffer in the first stage together with the feed-forward capacitor has a

crucial role reducing the Q value of the non-dominant poles. The M3 transistor is a low

transconductance transistor that is necessary to reduce the Q values of the poles. The second

stage is a rail-to- rail push-pull stage that forces the pass device to respond more quickly to

signal variations. The gate capacitance will be charged/discharged more quickly further

improving the transient response of the LDO.

Q-Reduction technique usually achieves higher bandwidths than the other techniques

presented for a given low quiescent current.

Fig. 2.4 Q-Reduction Compensation Topology.


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2.2.5 Pole-Zero Cancellation Compensation

The multi-stage amplifier topology represented in Fig. 2.5 seen on Surkantis study

[15] improves the capless LDO frequency response by cancelling the effect of the existing

output pole by determining its location and dynamically adding a zero over it, or near it. The

addition of the zero will be achieved by the ResistorCapacitor (RC) series connected to the

gate of the pass device.

Fig. 2.5 Pole-Zero Cancellation Compensation Topology.

With this technique a greater bandwidth can be achieved for a suitable phase margin.

This topology also permits a power device slew rate improvement. On the other hand, the

complexity, quiescent current and silicon area are significantly higher.

2.2.6 Multipath Miller Zero cancellation compensation (MMZCC)

The traditional solutions for RHPZ removal are all based on obstructing the direct path

through the Miller capacitor. Multipath Miller Zero Cancellation Compensation technique [4],

conversely, counteracts the RHPZ by a parallel path that compensates for the direct feed-

through. The technique improves the bandwidth by removing RHP zero that arises in a

Miller-compensated amplifier.

Further to MMZCC, other compensation techniques like multipath nested Miller

compensation (MNMC) [5] and hybrid nested Miller compensation (HNMC) [6] are reported

to extend the gain bandwidth of the amplifier. On the other hand, Nested Compensation

(NGCC) is also proposed to reduce the zeros, simplifying the transfer function of the nested-

Miller amplifier. All these techniques using polezero cancellation are effective. The

topologies are popular in terms of small area, bandwidth efficiency, and low power at driving


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small or moderate capacitive loads. The major advantage is that the positions of the poles are

not affected by the additional circuitry. The traditional techniques, such as voltage buffer,

current buffer, or nulling resistor for RHP zero removal, intend to obstruct the direct

feedforward path through the Miller capacitor. MMZCC, on the other hand, counteracts the

RHP zero by a parallel path that compensates for the direct feed-through effect.

Fig. 2.6 MMZCC topology.

2.2.7 Gain-Enhanced feed-Forward path compensation (GFPC)

A generic amplifier structure using GFPC technique [3] is depicted in Fig. 2.7.

Fig. 2.7 GFPC topology.

Contrasting to the feedforward topology in Fig. 2.6, a wide-band gain-enhanced

voltage amplifier, with low output impedance is added in the feedforward path. Hence, the

overall feedforward transconductance is given as mfVoverallmf gAg )( . The enhancement factor

is AVtimes for the transconductor stage.

This improved frequency compensation scheme is addressed in several key comments:

1) The transconductance gmf in Fig. 2.7 can be reduced by 1/AV times when compared with

that in Fig. 2.6 at driving identical capacitive load condition;


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2) The overall )(overallmfg boosted by the voltage gain amplifier reduces significant power

consumption of the entire amplifier;

3) The result of small compensation capacitor leads to smaller silicon area; and

4) The major non dominant parasitic LHP pole becomes the new second pole that defines the

phase margin of the operational amplifier; and note that this parasitic pole, arised from the

gain-enhanced voltage amplifier, is independent of the transconductance in the second gain

stage.


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Chapter 3

LDO Characterisation

3.1 Conventional LDO topology

LDO voltage regulators fall into the class of linear voltage regulators. The operation and

objectives of this class remain the same, so LDOs, like any other voltage regulator, must

provide a steady and clean voltage at their terminals independently of external variations. The

conventional LDO topology is presented in Fig. 2.1.

The main blocks of the conventional LDO topology are the error amplifier, the pass

device and the linear feedback network (R1 and R2). To operate, the LDO also needs a

voltage reference. This reference is established by an electric circuit known as Band Gap. The

difference between LDOs and Band Gaps, since both provide a steady voltage, is that an LDO

must be able to provide current and voltage to any indefinite number of load blocks. Band

Gaps, on the other hand, must provide a steady voltage to a single block with constant input

capacitance, which is usually a voltage regulator like an LDO. In short, Band Gaps dont

suffer from fan-out problems like LDOs.


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Fig. 3.1 Conventional LDO topology.

The error amplifier is responsible for the voltage comparison between the reference

and the scaled down output voltage obtained by the resistive feedback network. It is also

responsible for driving the pass device in function of the comparison result just stated. Due to

the advantages of the negative feedback (i.e., regulation and system control) and the signal

inversion on the pass device, the scaled down version of the output voltage needs to be fed to

the positive terminal of the amplifier and, by exclusion, the Band Gap has to be fed to the

negative terminal of the amplifier. As the positive and negative terminals assume roughly the

same value, then the output voltage is defined by the Band Gap through the negative terminal

and resistive divider. If the output voltage suffers from an undershoot, the positive terminal

will drop, forcing the error amplifier output voltage to drop as well thus increasing the pass

devices driving force. To finalize the cycle, the capacitor at the output node will be charged

more rapidly, raising the output voltage to the nominal value. The opposite process occurs

when the LDO output voltage suffers from an overshoot. The error amplifiers ability to drive

the pass device is asymmetrical [7] and depends greatly on the type of oscillation felt at the

LDOs output. Class-A operation, as core circuitry in conventional error amplifiers, can be

designed to push or pull a pass devices gate, charging or discharging it more quickly, but

never both [7]. Class-AB operation allows the symmetrical output oscillation, and time

response, with a small cost of complexity and silicon area.

The pass device is a power device whose only function is to control the amount of

current flow to the load. This device is extremely large; it can easily surpass 50% of the total

LDO design area in SoC context, as it needs to drive the total current the load. Typically,

while driving, a pass device supplies currents from 100 A to 100 mA, in low power context.


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17

Finally, a large capacitor exists at the LDO output in parallel to the load. This large

capacitor, in conventional LDO topologies, acts like a charge source during fast load

transients improving the response time of the regulator and its stability. However, as referred

earlier, this capacitor poses a problem due to the fact that it is too large to be an on-chip

capacitor and therefore goes against the modern design trends.

To better understand LDO regulators and follow the work proposed in this and the

next chapters a few parameters are introduced in Table 3.1.

Table 3.1 LDO Parameters.

Dropout Voltage VDO Difference between the minimum input voltage, necessary for the regulator

to operate, and the regulated output voltage.

Quiescent Current IQ Current drawn by the regulator when no load is applied.

Overshoot Output voltage peak that occurs in load and line transients when the signal

exceeds its target value.

Undershoot Output voltage negative peak that occurs in load and line transients when

the signal exceeds negatively its target value.

Load Regulation Measure of the circuits ability to maintain a constant output voltage despite

output current variations.

Line Regulation Measure of the circuits ability to maintain a constant output voltage despite

input voltage variations.

Load Transient Measurement of the systems speed response to an overshoot or undershoot

in the systems output current

Line Transient Measurement of the systems speed response to an overshoot or undershoot

in the systems input voltage

Power Supply Rejection or

Ripple Rejection

Measure of the circuits ability to regulate its output voltage against low to

high frequency variations in the input supply.

3.2 Pass Device

G. Rincn-Mora and P. Allen published a comparative study between LDO voltage

regulators with different pass devices [16] where the advantages and disadvantages of each

pass device were identified and its study deepened. This study results, summarized in Table

3.2, identified what is known and accepted today as the most suitable pass device for LDO

application, the P-type Metal-Oxide-Semiconductor (PMOS) device.


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18

The most important criterion for the pass device selection was the dropout voltage, VDO,

where the lower dropout voltages the better.

Table 3.2 Comparison of Pass element structures

NPN Darlington NPN PNP NMOS PMOS

Iload-max High High High Medium Medium

IQ Medium Medium Large Low Low

VDO Vsat+ 2Vbe Vsat+ Vbe Vec-sat Vsat+ Vgs Vsd-sat

Speed Fast Fast Slow Medium Medium

The NPN Darlington structure is not suited for low power LDOs for two main reasons.The lowest dropout voltage it can stand is given by (Vsat + 2Vbe) which is superior than 1 V.

The other reason is that, since it is composed by bipolar transistors, the quiescent current

increases greatly. Single NPN bipolar transistors are not the best option to LDO pass devices

because its lowest dropout voltage is given by Vsat + Vbe, superior than 1 V, when the base

of the transistor is fully pulled up to the supply voltage. Once more, quiescent current also

increases due to the large base current required. Single PNP bipolar transistors are preferred to

NPN bipolar transistors because the base of the PNP transistor can be pulled down to ground,

fully saturating the transistor where the dropout voltage is given by Vec sat. In PNP

transistors quiescent current is also increased due to the large base current required. On the

other hand, N-type Metal-Oxide-Semiconductor (NMOS) and PMOS transistors can operate

as pass devices without increasing the quiescent current and with dropout voltages beneath 1

V. The NMOS transistor can provide a minimal dropout voltage of Vsat + Vgs while the

PMOS transistor can be fully saturated providing a smaller dropout voltage of Vsd sat, being

this last candidate the optimal solution for the pass device of low-power LDOs.

3.3 Error Amplifier

The error amplifier present in the proposed topology has a key role in the fast voltage

regulation and compensation of the capless LDO. The error amplifier response is greatly

increased by its feeding damping loop and its derivative output voltage sensing block, hence

its name, derivative amplifier [18].


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19

The new multi-loop strategy is used to enhance the derivative voltage feedback

performance by applying a feed-forward path to it. Furthermore, due to this enhancement of

performance, the sensing of the fast output voltage variations will also be improved as well as

the quality of the load and line transient responses of the capless LDO. Finally, the

enhancement of the damping loop will contribute to, in addition with the aforementioned

enhancements, further improve the overall capless LDO response.

The error amplifier used in the proposed regulator is shown in figure 3.2.

Fig. 3.2 Error amplifier topology used in the proposed LDO design [2].

This error amplifier has the basic form of an op amp [2], a two-stage design for

driving low-conductance loads. Without the elements M2l (replaced by a short circuit), M22

and C1(removed), the circuit would be considered conventional.

At high frequencies the MOS resistor M21 isolates the gate of the output biasing

transistor M6 from the low impedance node of the bias-current mirror network (M4). This

makes it possible to drive M6with signals at high frequencies by means of capacitor C1and,

during negative slewing, by means of transistor M22.

Since M6can now sink much more than its bias current under transient conditions (and

even at dc with reduced loop gain), the transistor sizes and power dissipation of the output

stage can be greatly reduced for a specified output current capability.

The circuit in Fig. 3.2 is shown with an n-channel input differential stage placed in a

p-tub shorted to the source node. This has a supply-rejection advantage over the inverted

form, wherein the bulk material of the differential stage would be held at +VDD: there is no

backgate bias effect that would cause a threshold voltage variation in the input devices and,


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20

thus, produce a charge injection into the input nodes through the gate-source capacitance. This

feature is important when the gate of transistor M0is terminated in high impedance while the

gate of the transistor M1is grounded.

Two modifications to the circuit are noteworthy. First, for voltage-follower

applications, the p-tubs of M0and M1may be tied to-VSS. As the common-mode input swings

positive, the sources of those devices rise at a slower rate due to the backgate bias effect on

Vgs. Thus, the inputs can swing more positive before the drain voltages of M 0 and M1

approach the source voltage, and improved common-mode range is obtained. Second, if

maximum power supply rejection is needed, one may use a cascode input stage to eliminate

charge injection through the drain-gate capacitance.

The slew rate for no capacitive loading is primarily limited by the input stage current

and the main shaping capacitor. Even with relatively modest capacitive loading, the

conventional CMOS design becomes output limited in the negative direction if the bias

current in M6is low.

The circuit (Fig. 3.2) provides means for large transient signal components to drive the

pull-down transistor M6into strong action during negative slewing. A current nearly equal to

the full bias current 2I of the input stage is driven by transistor M3to the output node during

negative slewing, first mainly C1. The gate of the push-up transistor M5is driven quickly over

the relatively small voltage differential to its threshold. There is then a short, relatively slow

segment as the capacitances (including the load) charge up and the source of transistor M22

moves toward the positive supply, but not yet sufficiently far to turn M22on.

Actually the M6current has already risen moderately due to the presence of capacitor

C2; so the slewing is a little faster than this. After the threshold voltage of transistor M22 is

passed, the slew rate becomes limited by the total Miller capacitance then effectively across

M6rather than by the load capacitance.Note that the transistor M22, acting as a switch, has shorted the gates of the transistors

M5and M6.

3.4 Comparator

A high-speed comparator should have a propagation delay time as small as possible. In

order to achieve this goal, one must understand the requirements for a fast comparator. This

may be best understood by separating the comparator into a number of cascaded stages. If the


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21

input change is slightly larger than Vin(min), then the function of the stages is to amplify the

input with as little delay per stage as possible. We note that the signal swings in the initial

stages will be small. As the signal swing begins to approach the desired range, the amplifiers

will be limited by their slew rate. Thus, for initial stages, the important Parameter is to have a

high bandwidth so that there is little delay in amplifying the signal and passing it on to the

next stage. However, at the end of the cascade of amplifiers, it is more important to have a

high slew rate capability so that the voltage across the inter stage capacitors and the load

capacitor rises or falls quick enough. Therefore the stages at the beginning should be designed

differently than the stages at the end of the amplifier chain.

The basic principle behind the high-speed comparator is to use a preamplifier to build

up the input change to a sufficiently large value and then apply it to the latch [17]. This

combines the best aspect of circuits with a negative exponential response (the preamplifier)

with circuits with a positive exponential response (the latch).

The design of the preamplifier must be done in such a manner that the desired latch

input voltage is achieved in minimum time. Since the preamplifier is working in the linear

region, this means that the bandwidth must be as large as possible. We know that the gain

bandwidth of an amplifier is normally constant. Therefore, a single amplifier has a limited

capability. If a number of low-gain wide-bandwidth amplifiers are cascaded, the delay time

can be minimized. A high-speed comparator can be designed using three cascaded low-gain

amplifiers as the preamplifier and a latch at the output.

The low gain preamplifier must compromise between a high bandwidth and sufficient

gain. A simple preamplifier circuit is shown in figure 3.3. The connection with the latch (for

the last preamplifier) is shown.

There are several problems with this preamplifier of Fig. 3.3. One is that the gain is

very small even for large differences of W/L values. Another is that there is no isolationbetween the latch outputs and the inputs to the preamplifier. Rapid changes in the output of

the latch can propagate through the drain-gate capacitances of M1 and M2 and appear at the

input of the latch. Fig. 3.4 shows a preamplifier that solves these two Problems. Transistors

M5 and M6 are used to increase the current in M1 and M2 so that the gain is enhanced by the

square root of the difference of currents in Ml and M2 to the currents in M3 and M4.


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Fi

The use of a pream

offset voltage of the latch

22

g. 3.3 Example of Preamplifier and latch.

Fig. 3.4 An improved Preamplifier.

lifier before the latch also has the advantag

by the gain of the preamplifier. The inpu

of reducing the input

-offset voltage of the


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23

comparator will now become that of the preamplifier, which can be autozeroed, resulting in

small values of input-offset voltage.

When a comparator must drive a significant amount of output capacitance in very

short times, the latch is generally not sufficient. In this case it is advisable to follow the latch

by circuits that can quickly generate large amounts of current. A high-speed comparator

following these principles is shown in Fig. 3.5. The first stage is a low-gain, high-bandwidth

preamplifier that drives a latch. The latch outputs are used to drive a self-biased differential

amplifier [1]. The output of the self-biased differential amplifier drives a push-pull output

driver.

Fig. 3.5 Comparator topology used as the feed forward path.

The comparator circuit shown in figure 3.5 is used in the feed forward path of the low

dropout voltage regulator. In the latch portion of the comparator circuit, transistors M13 and

M14 are used to enable the latch to change its state, as without these the latch will remain in a

single state. Also, the resistor R1 in the preamplifier portion is used so as to track the signals

in both the branches.


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24

3.5 Band Gap Reference

An ideal voltage reference provides stable voltage independent of supply, process

and temperature. Reference voltages and/or currents with little dependence to temperatureprove useful in many analog circuits. As many process parameters vary with temperature, if a

reference is temperature-independent, it is usually process independent, as well. If two

quantities with opposite temperature coefficient are added with proper weighting, the

resultant quality theoretically exhibits zero temperature coefficients. Reference voltage

accuracy determines the maximum achievable performance of all IC systems. Bandgap

voltage reference, which was firstly proposed by Widlar and was further developed by

Kuijk and Brokaw, is the one commonly used in many advanced designs and

commercial products since it can provide a predictable reference voltage. Moreover, it is

also possible for low voltage and low temperature dependence.

A perfect voltage reference should contain no error. However, there are many sources

of error in the voltage reference such as error current from the current mirrors, error voltage

from the clamping circuit, as well as device mismatches. Undoubtedly, there are many well

developed circuits and layout techniques to minimize the errors. However, low supply

voltages limit the available methodologies and cause severe design problems. Moreover,

typical Bandgap references have non-zero temperature coefficient of typically around 40-

50ppm/oC. This is no doubt, an error. This error is no doubt significant in the past 5V and

10V systems, but is a fatal error in current 1.8V or even subs 1V systems. Solutions have been

proposed but are less useful in low voltage conditions.

By adding VBE to difference of VBE with proper scaling temperature coefficient of the

system can be made to zero. This is shown in figure 3.6 and it is called Band Gap Reference.

It is called as band gap reference because dVout/dT is zero when Vout= B.G of silicon.

Reference voltage circuitry is a very important block in the integrated circuit

such as A/D, D/A and other communication systems, which need high-accuracy

reference voltage to provide high-resolution and high speed data conversions in low

supply-voltage conditions, because the reference voltage accuracy determines the maximum

achievable performance of all IC system. The output voltage of conventional bandgap

reference voltage structures almost equals to 1.2V. With the development of CMOS

technology, low supply voltage becomes important in IC design. So the conventional


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25

architecture is improper for use in the latest deep submicron technologies whose power supply

is equal to or lower than 1.2V.

Fig. 3.6 Principle of BGR.

The typical current mode bandgap voltage circuit is built up by two currents, one

is proportional to VBE across the base-emitter of the parasitic BJT in CMOS process, the

other is proportional to VT . The negative temperature coefficient of the former term

compensates the positive temperature coefficient of the latter. But the temperature

dependence of VBE is not linear and therefore doesnt completely cancel the linear temperature

dependence of VBE, which is proportional to absolute temperature (PTAT). A curvature

compensated bandgap reference (BGR) with .8 V supply voltage is presented, which utilizes

the different temperature-dependent emitter of the BJT to obtain the nonlinear current INL to

cancel the nonlinear term of VBE.

3.6 Low Dropout Regulator Characterization

3.6.1 Peak Overshoot and Undershoot

The maximum tolerable transient supply overshoot and undershoot for analog

subsystems driven by low dropout regulator should not exceed 300mV. Therefore peak

overshoot and undershoot specification is taken as maximum 200mV.


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26

3.6.2 Dropout Voltage

The higher the dropout voltage the larger the power consumption of the circuit and the

smaller the dropout voltage, the larger the pass transistor required. Considering minimum

input voltage with a safety margin to be 1.4V, optimum dropout voltage is chosen as 200mV.

3.6.3 Line and Load Regulation

The accuracy constraint for the LDO output is defined by the following equation,

(3.1)

From accuracy constraint, the temperature coefficient, reference accuracy, the line and

load regulation are calculated. The temperature coefficient VTC=35ppm/0C*(Tmin-

Tmax)*Vo=35*120*1.2*10-6=5.04mV. Similarly, the reference accuracy is Vo,ref=20*120*0.8*10

-6=1.92mV. Thus, load regulation specification can be taken as

3V/mA.

3.6.4 Settling Time

Settling time of 2s is optimum for this purpose, as larger settling time corrupts the

frequency of oscillation of internal oscillators of the load driven by this LDO.

3.6.5

Loop Gain

Loop gain for the LDO is calculated based on the load regulation specification

obtained above using the following equation,

(3.2)

Here ropis the output resistance of the pass transistor, which is given by 1/out. From this we

get loop gain as 70dB. Loop gain is distributed between error amplifier, pass transistor, and

feedback resistor ratio. So the error amplifier as 55dB and the remaining gain will be provided

by the pass transistor.

3.6.6 PSRR

It is sufficient to choose -40dB at low frequencies since the audio sub systems that gets

excited by this LDO has a mechanism of rejecting all power supply ripple frequencies beyond

audio range.

o

TCorefoloadreglinreg

V

VVVVAccuracy

2

,

2

,

A

r

I

VLOR

op

o

o

1


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27

3.7 LDO Specifications

Table 3.3 LDO Specifications.

Parameters Specifications

Technology 180nm CMOS

Input Voltage(VIN) 1.4V

Output Voltage (VOUT) 1.2V

Output Load Capacitor (CL) 100pF

Quiescent Current (IQ) 1MHz

Settling Time


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Chapter 4

Design and Implementation

4.1 Overview

The proposed LDO design is divided in to 4 parts, pass transistor, error

amplifier, comparator and BGR design. The schematic of the proposed capless LDO is

shown in figure 4.1.

4.2 Pass Transistor Design

The dropout voltage of the LDO was selected to be 200mV for a maximum load current

of 100 mA based on current LDO regulator requirement. In device parameters, the pass

transistor is designed to deliver a drain current of 100mA while maintaining a saturation

voltage, VDS VGS VT, of 200 mV.


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Fig. 4.1 Sche

IMAX defines the

transistor, W/L, for a desir

29

atic diagram of the proposed capless LDO

Fig. 4.2 Pass Transistor design.

aximum output current, forcing the di

d minimum VDROP OUT.

egulator.

ensions of the pass


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30

First order approximations were used to find the rough device dimensions. This

relationship is shown in equation (4.1).

l

wC

I

VVoxp

DSATDROPOUT

max2

... ... ... ... ... ... ... ... ... ... ... (4.1)

The LDO is designed at maximum load current and minimum input voltage and such

that pass transistor is in saturation. To meet the requirements of maximum load current and

minimum dropout voltage the pass transistor of a very large dimension is required. Such a

large device introduces significant parasitic capacitances into the network, notably the gate-

source capacitance CGS. Large gate capacitance along with variable low-frequency load

impedance makes stabilizing a capacitor-less LDO difficult. The gate-source capacitance ofthis PMOS pass-transistor measured 26pF. The Miller effect with CGD further increases the

effective gate capacitance.

Pass transistor subthreshold operation is another major concern. For large variations in

the load current, the PMOS transistor will undergo a transition from operating in the

saturation region to operating in the subthreshold saturation region.

Subthreshold operation produces a significantly slower response. This may cause

significant degradation in the voltage regulation for applications where the load current drops

to low current levels in a short span of time. This degradation in load regulation can only be

counteracted by providing more current to the LDO, improving the speed of the circuit.

4.3 Feedback Resistor Design

The feedback resistors RF1 and RF2 are designed to draw a current IF. This current

through the series connected feedback resistors is solely determined by the output voltage.

Equation (4.2) shows the relationship of RF1and RF2with output voltage.


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31

Fig. 4.3 Feedback resistor network design.

F

outFF

I

VRR 21 ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... (4.2)

The values of RF1 and RF2 can be found by relation (4.3) shown below,

21

1Re

FF

Foutf

RR

RVV

... ... ... ... ... ... ... ... ... ... ... ... ... (4.3)

Assuming the value of IF and using the values for VRefand Vout, the values of RF1and

RF2can be obtained.

4.4 Band Gap Reference Design

The design of voltage reference mainly improves accuracy and rejects errors. Thus, the

errors in every part should be minimized by circuit and layout techniques. Considerations

should be focused on BJT ratio and resistor ratio matching, current mirror, as well as voltage

clamping. These considerations are discussed below.

Laser trimming can be used to optimize the performance of Band gap voltagereferences, but it is a costly procedure. As a result, layouts on BJTs and resistors should be

well planned and designed so that consistent performance can be achieved.

There are many reference topologies available for variety of applications and

process technologies. Currently, a large portion of market demand is driven by portable

electronic applications whose operating voltage range is very low and whose power

requirement is also low. Their temperature drift characteristics need to be tight. As a result

specifications became very tight. For RF section LDO of mobile phone where accuracy

is primary requirement, accuracy of BGR has to be very high.


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32

The principle of typical BGR can be illustrated by Fig. 4.4. The reference voltage is

formed by two currents I1 and I2. For I1it is a PTAT current formed by Q1, Q2and R1. VBE is

the VBE difference between Q1and Q2.

NVVVV TEBEBBE ln21 ... ... ... ... ... ... ... ... ... ... ... ... ... (4.4)

Where N is the emitter area ratio, VT is the thermal voltage, so I1= VTln N / R1, while

I2 is a current due to VEB and R2 as given by I2 = VEB /R2, and R2= R2A = R2B. Due to the

current mirror formed by M1, M2and M3, thus the output voltage of the band gap circuit is

given by,

NV

R

RV

R

RRIIV TEBf ln.

1

2

2

3321Re ... ... ... ... ... ... ... (4.5)

The compensation of the TCs of VT and VEB can be ensured by a proper choice of

the R2/R1 ratio and N. The TCs of resistors are cancelled if resistors are made with the same

resistive layer.

Fig. 4.4 Schematic of Band Gap Reference Circuit.

The minimum supply voltage of the circuit is determined by the VEBplus saturation

voltage of a Pchanneltransistor.

According to an empirical relationship, the VBE voltage in a BJT can be given by

equation (4.6),

000 ln T

T

VT

T

TVVVTV TEBBGBGEB ... ... ... ... ... (4.6)


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33

Where is a process-dependent constant and is around 4, while = 1 if the current in

the BJT is PTAT and = 0 when the current is temperature independent. From above

equation, VBE does not change linearly with the temperature. The simple bandgap architecture

shown in Fig. 4.4 only corrects the first term in Equation (4.6), thus leading to a second order

temperature dependence. Various approaches to compensate for the nonlinear term have been

proposed. The structure of curvature-compensated BGR is shown in Fig. 4.5. The basic idea is

to correct the nonlinear term by a proper combination of the VEB across a junction with a

temperature-independent current ( = 0) and the VEB across a junction with a PTAT current (

= 1). The current in Q1 and Q2 in Fig. 4.5 is PTAT ( = 1) while the current in the p-channel

MOS transistors is at first order temperature independent.

Therefore, if we mirror the current flowing in p-channel MOS transistors M1,2

and inject it into a diode connected bipolar transistor Q3, as shown in Fig., we produce a VEB

with =0.

Fig. 4.5 Band gap reference circuit with curvature compensation.

VNL= VBBQ1,2(T) - VBBQ3(T) = VTln (T/TO)... ... ... ... ... ... ... (4.7)

Curvature compensation current proportional to VNL can be achieved now by

subtracting from both I1 and I2. This is obtained by introducing resistors R4A and R4B

(equal), which drain from M1 and M2 the required current INL, thus leading to


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34

04

2

1

2

2

3

3

0421

lnln

lnln

TTV

RRNV

RRV

RR

RT

T

R

V

R

V

R

NVV

TTEB

TEBTREF

... ... ... ... ... ... ... .. (4.8)

When the resistors ratio R2/R4 = 1, the nonlinear voltage in VEB is cancelled. A

theoretical zero TC VREFcan be obtained. However, it cannot always be achieved due to the

non ideal PTAT and temperature dependence of resistors.

4.5 Error Amplifier Design

From load and line regulation specifications we get loop gain for the error amplifier.

Load Regulation is given by

A

r

I

VLR

op

O

Oload

1... ... ... ... ... ... ... ... ... ... ... ... ... (4.9)

From specifications load regulation is given by 3V/mA. ropis the output resistance of

pass transistor, which is given by 1/out. From this we get loop gain as 70dB. Loop gain is

distributed between error amplifier, pass transistor, and feedback resistor ratio. So the error

amplifier as 55dB and the remaining gain will be provided by the pass transistor. For the LDO

to respond in 1s, UGB should be atleast 1MHz. So the following specifications are taken for

the error amplifier.

Gain >= 55dB

UGB >= 1MHz

Slew rate = 2V/s

Phase margin >700.


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Chapter 5

Results and Discussion

In order to fully characterize the proposed capless LDO, the results of the performed

simulations are presented. The conditions of the simulations and its considerations are also

given as well as their validity. All simulations were executed for the minimum dropout

voltage across the pass device of 200 mV, Vin= 1.4 V regulating to Vout= 1.2 V. It is assumed

that the capacitance seen by the output node of the LDO forward is 100 pF; it includes the

power line distribution capacitances as well as parasitic capacitances.

The designed capless LDO circuit consumes a total biasing current (quiescent current)

of around 69 A with a total power consumption of 0.096 mW.

5.1 Loop Gain Simulations

The overall stability of the system is defined from its loop gain and phase response. Fig.

5.1 shows the AC response of the design where the loop gain, bandwidth and phase margin

can be obtained for Iout= 100 mA. As can be observed from the plots the obtained Loop Gain

is 68 dB, Bandwidth is 4.742 MHz and Phase Margin is 77.93 for the output load capacitor

of 100pF.


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36

Fig. 5.1 Loop gain and Loop phase plots.

5.2 Transient response Simulations

Fig. 5.2 presents the capless LDO load transient response of the proposed capless LDO.

The simulation was performed to the minimum dropout voltage where the output current

quickly (rise/fall time=1 s) varied from 0 mA to 100 mA.

As expected, the output voltage suffered from an undershoot of 153.79 mV to the 0 mA

100 mA output current transition, and an overshoot of 196.24 mV to the 100 mA 0 mA

output current transition.

The settling time, as shown in figure 5.3, is approximately 1.1 s for the output

voltage undershoot case (measured when the output voltage is within 10% of the regulation

value).


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37

Fig. 5.2 Load transient response plot for load varying from 0 to 100mA (rise time of 1s).

Fig. 5.3 Load transient response plot for settling time measurement.

The load transient results achieved are considered good results due to the fact that the

regulation is possible even with low quiescent current while the under and overshoot results

are kept relatively low.


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5.3 Load regulati

Simulated value of t

shown in Fig. 5.4.

5.4 PSR simulati

The behaviour of th

presented in Fig. 5.5.

The PSR values ac

frequency (1Hz and 20 kH

The PSR results achi

done to improve the resp

ripples at the supply node t

The line regulation v

mathematical relationship,

38

n simulation

he load regulation is: 2.77 V/mA at load

Fig. 5.4 Load regulation plot

ns

e proposed capless LDO to ripples in the

ieved with the proposed capless LDO t

) are 15.05 dB and 14.73 dB respectively.

eved are not according to the specifications

nse at issue, namely to improve the atte

roughout different segments of the frequenc

alue can also be obtained by the systems PS

LNR = 1/PSRDC.

current of 100 mA as

power supply node is

the usual values of

and much can still be

uation of undesirable

y range.

R response through its


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39

Fig. 5.5 Power Supply Rejection plot.

5.5 Band Gap Reference TC simulation

The proposed CMOS band gap reference with 1.4V operation has been presented,

which produces an output reference voltage VRef of 0.8V. The output reference voltage can

be varying by adjusting current mirror and the resistor. From the designed BGR, simulation

result predicts a temperature coefficient of at most 19.58 ppm/C over the temperature range

of -40 to 80 C.

Fig. 5.6 Plot for Temperature Coefficient over temperature range -40 to 80 C.


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40

5.6 Comparison with the Previous works

Table 5.1 shows the performance comparison of the proposed work with respect to the

recent prior-art works of capacitorless LDO. It indicates that the optimal trade-offperformance can be obtained in the proposed work.

Table 5.1 Comparison with the recent reported prior-art results

Ref. [19] [20] [21] [22] [23] [24] This work

Year 2009 2010 2011 2012 2013 2014 2014

Tech.[m] 0.35 0.35 0.18 0.35 0.11 0.18 0.18

VDrop[mV] 200 200 200 150 200 200 200

COUT(pf) 100 100 0-100 100 40 100 100

Cm(pf) 3 7 10 - - - 3

IMax[mA] 100 100 100 100 200 100 100

IMin[A] 50 0 0 0 500 0 0

IQ[A] 27-270 20 14-53.5 7 41.5 3.7 69

VOUT[mV] N.A.


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Chapter 6

Conclusions

6.1 Conclusion

This thesis presented a stable LDO voltage regulator with an improved gain enhanced

feed forward path compensation using a comparator. This structure enhanced the gain,

bandwidth and transient response of LDO without increasing power or area consumption as

the compensation capacitors involved are of low values. The topology is validated through

simulation results. The output voltage spike of the LDO with the proposed circuit decreases to

153.79 mV when the output current changes from 0 to 100 mA and 196.24 mV for the current

change from 100 mA to 0. This LDO presents a good stability with a phase margin of 77.93

for ILOAD of 100mA. The LDO consumes a total biasing current of around 69 A. This LDO

compares favourably with that of other published designs. The improved design will be

suitable for application to SoC to reduce power and cost consumption.

6.2 Future Scope

Some of the future enhancements that can be made for this project work are as follows:

1.

Error amplifier with PMOS current mirror load has good DC PSR at LDO output and

NMOS current mirror load will have a high PSR bandwidth at LDO output. These two


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error amplifiers can be connected in parallel to achieve both, but it comes at the

expense of power and silicon area.

2.

The improvement of the LDO PSR with the pole cancellation technique should be

achieved by introducing an internal zero that does not affect the signal path.


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[12] Hua Chen and Ka Nang Leung, A fast-transient LDO based on buffered flipped voltage

follower, IEEE Int. Conf. of Electron Devices and Solid-State Circuits, 2010.

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nested miller compensation, IEEE Trans. Circuits and Systems I: Regular Papers,

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[14] S. K. Lau, P. K. T. Mok, and K. N. Leung, A low-dropout regulator for SoC with q-

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Acknowledgements

I have been very fortunate to have Dr. Patri Sreehari Rao, Department of Electronics

and Communication Engineering, National Institute of Technology Warangal,as my advisor

and guide over this period of my masters program. So, at first, I would like to thank him for

allowing me to do this work with his constant support and encouragement throughout the

completion of the project. I am grateful to him for his invaluable guidance and motivation.

I would like to thank Prof. K.S.R. Krishna Prasad,Department of Electronics and

Communication Engineering, National Institute of Technology Warangal for his invaluable

guidance and motivation. His devotion in the field of VLSI has been a great inspiration in

finishing my masters studies.

I would like to thank the Head of Department, Prof.N.V.S.N Sarma and all my

faculty members in ECE department for their help during my M.Tech.

At last I would like to thank Mr. Suresh Alapati, research scholar, Mr. Sunil Kumar

Bhat and Mr. Debashish Dwibedy, for their constant help in the discussion of the problems

about this project. I am also grateful to my parents for their constant and much needed

priceless support.

Saurabh Dixit

Roll No. 124570

Documents

Final Report Sd