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Final report
DRAM data retention time characterization of and study of TID effects.
COST Action IC1103
Angelo Bacchini
31 May 2014
Contents
1 Introduction 1
2 DRAM Data Retention Faults 3
2.1 Test Platform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
3 Test Results 4
3.1 Retention time distribution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
3.2 Temperature dependence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
3.3 Data background dependence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
3.4 Previous charge level dependence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3.5 Thermal Characterization of Variable Retention Time . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
4 TID Effects on Retention Time 7
5 Conclusion 8
1 Introduction
Dynamic Random Access Memory (DRAM) is widely used in mass memory units for space applications; space
applications have particularly high reliability requirements therefore emerging reliability issues are quite important
in this field. A specific case study triggered this work: during the tests performed on an ESA satellite mission
several errors were detected on the SDRAM memory modules of the mass memory unit. These were Single Bit
1
Angelo Bacchini Final report COST Action IC1103
Errors (SBEs) always occurring at the same memory locations, and appearing and disappearing randomly over
time. As the weak bits failures seem related to the memory cells ability to retain their charge, an in depth study
of DRAM data retention time was carried out in the European Space Research and Technology Centre (ESTEC)
Avionics laboratory. In this short scientific mission, particular focus was given to the thermal characterization
of Variable Retention Time (VRT) phenomenon. In addiction, we performed Total Ionization Dose (TID) tests to
investigate radiation effects on DRAM data retention time.
List of Acronyms
DRAM Dynamic Random Access Memory
SDRAM Synchronous Dynamic Random Access Memory
SBE Single Bit Error
DRF Data Retention Fault
TID Total Ionization Dose
DUT Device Under Test
ESTEC European Space Technology and Research Center
VRT Variable Retention Time
FPGA Field Programmable Gate Array
PDF Probability density function
CDF Cumulative density function
CCDF Complementary Cumulative density function
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2 DRAM Data Retention Faults
A 1-transistor (1T) DRAM cell consists of a transistor and a capacitor, as shown in Figure 1. Data is stored as
charge on a capacitor. When the cell is accessed (by enabling the corresponding wordline), the capacitor shares
its charge with the bitline, causing a voltage change on it. The sense amplifier connected to the bitline detects
the voltage change and amplifies it so that it can be interpreted as 0 or 1 by an external driver. However, because
of off-state transistor leakage, the stored charge is gradually lost, thus introducing the need for periodical refresh
operation to prevent data corruption.
The retention time (tret) can be defined as the duration until the stored value can be correctly read. Each
memory cell experiences an individual mixture of leakage currents which lead to a wide distribution of tret. In
addition, the amount of charge stored can be minimized due to process defects that impacts the ability to store
maximum charge. If a cell exhibits a tret less than the DRAM refresh interval (customarily 64 ms [1]), a data
retention fault (DRF) can occur, resulting in a single bit error.
wordline
bitlineCcell
sense amp(a) Charge sharing
wordline
bitlineCcell
sense amp(b) Sensing
Figure 1: DRAM cell access.
2.1 Test Platform
We developed an ad-hoc test procedure to accurately measure DRAM cells retention times which consists of the
following steps:
1. Data is written to the DRAM. Refreshes are initially enabled, to ensure that no data corruption occurs during
the write.
2. When the write is completed, each row is refreshed 1.
3. Refreshes are disabled for a period of time tpause while the DRAM is left idle.
4. After the pause time, each row is refreshed again. After this step, each row has experienced a length of
time equal to tpause without being refreshed.
1As a minimum time in the order of tens of nanoseconds is required between two consecutive row refresh operations, refreshing all the
rows takes less than one millisecond. This additional time can be neglected when measuring retention time, as the lowest retention times
reported are in the order of tens of milliseconds.
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Tester Core
Pattern generator
BlockRAM
DLL
Soft Microcontroller
DLL
SDRAM
CLK IN
SDCLK
SDCLKFB
FPGA
UARTRX/TX
Figure 2: Test platform block diagram.
5. Data is read back from the DRAM and checked for corruption. Any cell that exhibits a bit upset is known to
have a retention time less than tpause.
6. Retention time is measured by repeating steps 2-5 with increasing tpause until the pass-fail boundary for
each cell is found.
The accuracy of the measurement is set by the resolution of the pause time increase.
We designed a FPGA-based temperature controlled test platform to accurately perform retention time mea-
surements. The test platform uses a custom developed IP-core to perform retention test, able to control the
SDRAM without the need of an external memory controller. For each cell not passing the retention test, informa-
tion about cell address and measured retention time is stored on the FPGA block memory and sent to the PC
host through a RS-332 serial interface. A block diagram of the test platform is shown in Figure 2.
3 Test Results
In this section we report the experimental results from data retention tests performed with our platform on com-
mercial DRAM devices. The data is analyzed to evaluate the impact of several factors on data retention time. In
the following subsections each of these analyses is reported.
3.1 Retention time distribution
Figure 3 shows the probability density function (PDF) of retention time measured from 8 DRAM chips from 2
different vendors.
Refresh characteristics and production yield of DRAM are dominated by the left tail of the log-normal distri-
bution, even if cumulative probabilities have proportions lower than 10−5. Many studies [2–5] assert trap assisted
GIDL as the most important leakage path responsible for the lower retention times in DRAMs: traps located
near oxide/silicon interface in the gate to drain overlap region enhance GIDL current causing anomalously low
retention times.
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Angelo Bacchini Final report COST Action IC1103
00 1000 2000 3000 4000 5000 6000 7000 8000 9000 10000
0.01
0.02
0.03
0.04
0.05
0.06
0.07
Retention time [ms]
Vendor AVendor B
Figure 3: Retention time PDF from 8 DRAM devices.
85◦C.
Retention time [ms]
0 1000 2000 3000 4000 5000 6000 7000 8000 9000 100000
0.01
0.02
0.03
0.04
0.05
0.06
85C80C75C
Figure 4: Retention time PDF at different tempera-
tures.
3.2 Temperature dependence
A DRAM cell retention time is determined by the leakage of its access transistor, which increases along with
the increase of the temperature. To evaluate the effect of temperature on DRAM cells retention time, retention
tests were performed with increasing operating temperature (45◦C, 55◦C, 65◦C, 75◦C, 85◦C). For temperature
control, a sub miniature controlled heater was attached to the DRAM chips under test. Retention time PDF from a
DRAM chip at three different temperatures is shown in Figure 4. Retention time follows a log-normal distribution.
When temperature is increased, the mean value of the distribution is reduced whilst the standard deviation is
increased.
The activation energy (Ea) provides information about the temperature dependence of retention time. Ea can
be extracted from the temperature dependence of the retention time given by
tret ∝ exp[
Ea
KbT
](1)
with Kb being Boltzmann constant. Results from our measurements show Ea ranging from 0.33 eV to 0.69 eV
suggesting correspondence to results from prior works [6] [4].
3.3 Data background dependence
The retention time of each DRAM cell is strongly affected by the value stored in nearby cells due to capacitive
bitline coupling [9]. We performed repeated retention tests with 4 different data backgrounds to evaluate the
effects of data background on retention time.
Liu et. al [10] showed how dynamic data background (i.e. a data background that change in each test round)
such as “random” and “walking” can improve test coverage with the disadvantage that many test rounds have to
be performed in order to achieve high test coverage. Our results show consistency with the results from Liu et.
Al as shown in Figure 5.
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0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1
solidchkboard
walking
randomrow stripe
col. stripe
Test coverage
(a) Vendor A.
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1
solidchkboard
walking
randomrow stripe
col. stripe
Test coverage
(b) Vendor B.
Figure 5: Test coverage for different data backgrounds.
3.4 Previous charge level dependence
When accessed, a 1T DRAM cell can be modelled as a first order RC circuit, where the access transistor is
modelled as a switch in series with a resistance.
When the charge-up process is over, retention time of a DRAM is given by the voltage on the capacitor:
Vc(t)=Vc(t0)−∫ t
t0
ILKG
Cdt (2)
Vc(t0) (i.e. the voltage stored on the cell after the writing process) in turn depends on the level of charge stored
on the cell prior to its being written. To present a quantitative evaluation of the effects of previous charge on
retention time, we discharged the cell before performing the retention test. By doing this, we observed a decrease
in retention time both in devices from vendor A and vendor B.
3.5 Thermal Characterization of Variable Retention Time
Variable retention time (VRT) was first observed in 1987 by Yaney [7], and then confirmed and investigated by
Restle [8]. This phenomenon causes the retention time of many DRAM cells to change randomly over time.
To evaluate the temperature effects on VRT, we performed retention tests for 6 hours (1 retention test each
minute) at 3 different temperatures (85◦C, 65◦C, 45◦C) with a solid data background. For each cell we measured
the retention time variation defined as follows:
∆tret =tret(max) − tret(min)
tret(max)(3)
Complementary cumulative distribution function (CCDF) for ∆tret at different temperatures is shown in Figure
6. As CCDF shows similar distribution of ∆tret at different temperatures, we conclude that the VRT amplitude
(i.e. retention time variation) is not significantly dependent on temperature.
We also measured the amount of time that the VRT cell spends without undergoing a transition to low reten-
tion time (which we refer to as τ) for each transition occurred in each tested cell at different temperatures. CCDF
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10 20 30 40 50 60 700
10−4
10−3
10−2
10−1
10 0
Retention time variation (%)
CCDF
85C65C45C
10−5
80
Figure 6: VRT Retention time variation CCDF. 85◦C.
0 50 100 150 200 250 300
10−3
10−4
10−2
10−1
10 0 CCDF
Time before a transistion to low retention time [min]
85C65C45C
Figure 7: VRT time before a transition CDFF. 85◦C.
for τ at different temperatures is shown in Figure 7, indicating that the probability of a transition to low retention
state increases with temperature.
VRT poses a major obstacle in data retention fault detection. Many cells spend very long times in the high
retention time before the transition to the low retention time. This implies that retention test may need to be con-
tinuously performed for periods of time on the order of hours in order to reliably detect VRT related data retention
faults (the cell has to be in its lowest retention time in order to be accurately tested for data retention faults).
Increasing test temperature will improve fault detection because the probability of a VRT transition increases with
temperature.
4 TID Effects on Retention Time
The SDRAM under test was exposed to three sequential irradiation session of about 20 krad each (Table 1).
Retention time was measured before and immediately after each exposure at an operating temperature of 85◦C.
Solid data background was used in each retention test. Irradiation was performed using the CO-60 source at
ESTEC. Device under test (DUT) was unbiased during the irradiation.
Figure 4 shows retention time PDF before and after the total 60 krad exposure. The mean value of the
distribution is reduced but the standard deviation is slightly increased. If the TID induced retention time reduction
had been homogeneous among the cells, the standard deviation would be reduced, as it happens for retention
time temperature dependence (Section 3.2). To investigate the nature of the retention time degradation we
measured retention time reduction after radiation exposure for the individual cells. The PDF in Figure 4 shows
how retention time reduction follows a folded gaussian distribution, with some cells exhibiting a reduction greater
than 90 %. Figure 10 shows the cumulative distribution of retention times up to 300 ms at several absorbed
doses. Results clearly show a gradual reduction of retention time proportional to the adsorbed dose.
After the three exposures, 11 cells failed to meet the 64 ms JEDEC refresh interval requirement, resulting in
data retention faults. It should be noted that retention time of these failing cells was greater than 300 ms prior
to the exposure. The failing cells still exhibit a retention time temperature dependence with activation energies
ranging from 0.45 eV to 0.60 eV, and they all belong to different rows and columns. This indicates that no sense
amplifier or logic failure is the origin of these faults and retention time degradation in general. We conclude that
the responsible factor is an increased leakage.
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Table 1: TID test exposure dose rates.
RUN DURATION TID (WATER) DOSE RATE (WATER)
1 1373 min 20.38 krad 1.272 krad/h
2 1050 min 22.33 krad 1.276 krad/h
2 1053 min 22.44 krad 1.278 krad/h
0 1000 2000 3000 4000 5000 6000 7000 8000 9000 100000
0.01
0.02
0.03
0.04
0.05
0.06PDF
Retention time (ms)
0 krad60 krad
Figure 8: Retention time PDF before and after radia-
tion exposure.
100806040200-20-40-60-80-1000
0.02
0.04
0.06
0.08
0.1
0.12
Retention time variation (%)
Figure 9: Radiation induced retention time reduction
PDF.
20 40 60 80 100 120 140 160 180 200 220 240 260 280 300100
101
102
103
104
105
106
107
Retention time [ms]
Cum
ulat
ive
fail
bit c
ount
60 krad40 krad20 krad0 krad
64 ms
Figure 10: Cumulative fail bit count before and after radiation exposures. 85◦C.
5 Conclusion
Within this study, experimental results on DRAM retention time were obtained using the developed test platform.
The obtained data was evaluated allowing for the identification of different factors impacting DRAM cells retention
time. Knowledge of retention time behavior, this is mandatory for the identification of the best test conditions for
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Angelo Bacchini Final report COST Action IC1103
early detection of retention time related faults.
TID effects on DRAM retention time was also investigated, clearly showing a significant retention time degra-
dation and the occurrence of TID related data retention faults.
Results have been submitted for publication at the annual International Symposium on Defect and Fault Tol-
erance in VLSI and Nanotechnology Systems (DFT) that will take place in Amsterdam, October 1-3.
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