FINAL REPORT Cryptography

7/31/2019 FINAL REPORT Cryptography

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CRYPTOGRAPHY USING RC6 ALGORITHM

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CHAPTER 1

INTRODUCTION

CRYPTOGRAPHY

The Cryptographic Algorithm which is most widely used throughout the world

for protecting information. Cryptography is the art of secret writing,

followed by the guarantee to authenticate data and messages and protect

the systems from valid attacks .It comprises of encryption and decryption

operations each associated with a key which is supposed to be kept secret. We have implement

RC6 Algorithm. Which is considered as a secured and

elegant choice for AES due to its simplicity, security, performance and

efficiency. RC6 supports 32 bit and 64 bit processing. An eight step

operation is used to encipher the 64 bit plain text block. The encrypted

data is then decrypted by performing the reverse operations on the same.

The hardware implementation of RC6 algorithm is done using VHDL

Hardware Description Language. For this implementation Xilinx foundation

series 9.2i software

1.1 RC6 ALGORITHM

We introduce the RC6 TM block cipher. RC6 is an

evolutionary improvement of RC5, designed to meet the requirements of

the Advanced Encryption Standard (AES). Like RC5, RC6 makes essential use of data-

dependent rotations. New features of RC6 include the use of four working registers instead

of two, and the inclusion of integer multiplication as an additional primitive operation. The use

multiplication greatly increases the diffusion achieved per round, allowing forgreater security, fewer rounds, and increased throughput.


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1.1.1 WHY WE HAVE SELECTED RC6 ALGORITHM

RC6 is considered as a secured and elegant choice due to its simplicity, security,

performance and efficiency. It appears that RC6 is best suited for implementation in the targeted

Xilinx FPGA (Spartan-3). Our studies reveal that multiplication and addition are the major

bottlenecks as far as speed of encryption in the RC6 cipher is Concerned. Nevertheless, up to a

great extent this shortcoming was Tackled using pipelining in our design.Consequently, since

RC6 works best in non-feedback mode, the highest Speed/Area ratio can be achieved in the same

RC6 is a symmetric key block cipher derived from RC5. It was designed by Ron Rivest,Matt

Robshaw, Ray Sidney, and Yiqun Lisa Yin to meet the requirements of the Advanced Encryption

Standard (AES) competition. The algorithm was one of the five finalists, and was also submitted

to the NESSIE and CRYPTREC projects. It is a proprietary algorithm, patented by RSA

Security.

RC6 proper has a block size of 64 OR 128 bits and supports key sizes of 128, 192 and

256 bits, but, like RC5, it can be parameterized to support a wide variety of word-lengths, key

sizes and number of rounds. RC6 is very similar to RC5 in structure, using data-dependent

rotations, modular addition and XOR operations; in fact, RC6 could be viewed as interweaving

two parallel RC5 encryption processes. However, RC6 does use an extra multiplication operation

not present in RC5 in order to make the rotation dependent on every bit in a word, and not just

the least significant few bits.

1.2 TYPES OF CRYPTOGRAPHIC ALGORIYTHM

1. Symmetric encryption algorithms (secret or private key algorithms) and

2. Asymmetric encryption algorithms (or public key algorithms).The difference is that symmetric encryption algorithms use the same key for encryption and

decryption (or the decryption key is easily derived from the encryption key), whereasasymmetric encryption algorithms use a different key for encryption and decryption,
http://en.wikipedia.org/wiki/Symmetric_keyhttp://en.wikipedia.org/wiki/Block_cipherhttp://en.wikipedia.org/wiki/RC5http://en.wikipedia.org/wiki/Ron_Rivesthttp://en.wikipedia.org/wiki/Matt_Robshawhttp://en.wikipedia.org/wiki/Matt_Robshawhttp://en.wikipedia.org/wiki/Advanced_Encryption_Standardhttp://en.wikipedia.org/wiki/Advanced_Encryption_Standardhttp://en.wikipedia.org/wiki/AES_competitionhttp://en.wikipedia.org/wiki/NESSIEhttp://en.wikipedia.org/wiki/CRYPTREChttp://en.wikipedia.org/wiki/RSA_Securityhttp://en.wikipedia.org/wiki/RSA_Securityhttp://en.wikipedia.org/wiki/RSA_Securityhttp://en.wikipedia.org/wiki/Block_size_(cryptography)http://en.wikipedia.org/wiki/Key_sizehttp://en.wikipedia.org/wiki/Modular_arithmetichttp://en.wikipedia.org/wiki/XORhttp://en.wikipedia.org/wiki/XORhttp://en.wikipedia.org/wiki/Modular_arithmetichttp://en.wikipedia.org/wiki/Key_sizehttp://en.wikipedia.org/wiki/Block_size_(cryptography)http://en.wikipedia.org/wiki/RSA_Securityhttp://en.wikipedia.org/wiki/RSA_Securityhttp://en.wikipedia.org/wiki/CRYPTREChttp://en.wikipedia.org/wiki/NESSIEhttp://en.wikipedia.org/wiki/AES_competitionhttp://en.wikipedia.org/wiki/Advanced_Encryption_Standardhttp://en.wikipedia.org/wiki/Advanced_Encryption_Standardhttp://en.wikipedia.org/wiki/Matt_Robshawhttp://en.wikipedia.org/wiki/Matt_Robshawhttp://en.wikipedia.org/wiki/Ron_Rivesthttp://en.wikipedia.org/wiki/RC5http://en.wikipedia.org/wiki/Block_cipherhttp://en.wikipedia.org/wiki/Symmetric_key


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1.2.1 SYMMETRIC CRYPTOGRAPHIC ALGORITHM

Symmetric encryption algorithms can be divided into stream ciphers and block ciphers.

Stream ciphers encrypt a single bit of plaintext at a time, whereas block ciphers take a number of

bits (typically 64 bits in modern ciphers), and encrypt them as a single unit.

Some examples of popular symmetric encryption algorithms:

DES (Data Encrytion Standard)

DES accepts a 64-bit key, the key setup routines effectively discard 8 bits, giving DES a

56-bit effective keylength.. DES was designed to be implemented only in hardware, and is

therefore extremely slow in software. A recent successful effort to crack DES took several

thousand computers several months.

RC5

RC5 is a group of algorithms designed by Ron Rivest of RSA Data Security that can take

on a variable block size, key size, and number of rounds. The block size is generally dependent

on the word size of the machine the particular version of RC5 was designed to run on; on 32-bit

processors (with 32-bit words), RC5 generally has a 64-bit block size. David Wagner, John

Kelsey, and Bruce Schneier have found weak keys in RC5, with the probability of selecting a

weak key to be 2-10r, where r is the number of rounds. For sufficiently large r values (greater than

10), this is not a problem as long as you are not trying to build a hash function based on RC5.Kundsen has also found a differential attack on RC5. RC5 is described in this RSA document.

RC5 is patented by RSA Security, Inc.

RC6

RC6 is Ronald Rivest's AES submission. Like all AES ciphers, RC6 works on 128 bit

blocks. It can accept variable length keys. It is very similar to RC5, incorporating the results of

various studies on RC5 to improve the algorithm. The studies of RC5 found that not all bits of

data are used to determine the rotation amount (rotation is used extensively in RC5); RC6 usesmultiplication to determine the rotation amount and uses all bits of input data to determine the

rotation amount, strengthening the avalanche effect.
http://www.interhack.net/pubs/des-key-crack/http://www.cs.berkeley.edu/~daw/http://www.counterpane.com/schneier.htmlhttp://www.cs.berkeley.edu/~daw/papers/keysched-crypto96.psftp://ftp.esat.kuleuven.ac.be/pub/COSIC/knudsen/rc5.ps.Zftp://ftp.rsa.com/pub/cryptobytes/crypto1n2.pdfhttp://www.rsa.com/http://www.rsa.com/ftp://ftp.rsa.com/pub/cryptobytes/crypto1n2.pdfftp://ftp.esat.kuleuven.ac.be/pub/COSIC/knudsen/rc5.ps.Zhttp://www.cs.berkeley.edu/~daw/papers/keysched-crypto96.pshttp://www.counterpane.com/schneier.htmlhttp://www.cs.berkeley.edu/~daw/http://www.interhack.net/pubs/des-key-crack/


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RIJNDEAL

Rijndael is an AES winner by Joan Daemen and Vincent Rijmen. The cipher has a

variable block and key length, and the authors have demonstrated how to extend the block length

and key length by multiples of 32 bits. The design of Rijndael was influenced by the SQUARE

algorithm. The authors provide a Rijndael specification and a more theoretical paper on

theirdesign principles. The authors have vowed to never patent Rijndael.

RC4

The RC4 algorithm is a stream cipher from RSA Data Security, Inc. Though RC4 was

originally a trade secret, the alleged source code was published anonymously in 1994. The

published algorithm performs identically to RC4 implementations in official RSA products. RC4is widely used in many applications and is generally regarded to be secure. There are no known

attacks against RC4. RC4 is not patented by RSA Data Security, Inc; it is just protected as a trade

secret. The 40-bit exportable version of RC4 has been broken by brute force!

RC4 is implemented in Kremlin.

MD5

While MD4 was designed for speed, a more conservative approach was taken in the

design of MD5. However, applying the same techniques he used to attack MD4, Hans Dobbertinhas shown that collisions can be found for the MD5 compression function in about 10 hours on a

PC. While these attacks have not been extended to the full MD5 algorithm, they still do not

inspire confidence in the algorithm. RSA is quick to point out that these collision attacks do not

compromise the integrity of MD5 when used with existing digital signatures. MD5, like MD4,

produces a 128-bit digest. An RFC describing MD5 in detail is available here. The use of MD5,

as well as MD4, is not recommended in new applications.
http://csrc.nist.gov/encryption/aes/http://www.esat.kuleuven.ac.be/~rijmen/index.htmlhttp://www.esat.kuleuven.ac.be/~rijmen/rijndael/rijndaeldocV2.ziphttp://www.esat.kuleuven.ac.be/~rijmen/rijndael/PropCorr.PDFhttp://www.rsa.com/http://www.funet.fi/pub/crypt/cryptography/symmetric/rc4/rc4.revealed.gzhttp://www.rsa.com/http://pauillac.inria.fr/~doligez/ssl/http://www.kremlinencrypt.com/kremlin.htmftp://ftp.rsasecurity.com/pub/cryptobytes/crypto2n2.pdfhttp://sunsite.auc.dk/RFC/rfc/rfc1321.htmlhttp://sunsite.auc.dk/RFC/rfc/rfc1321.htmlftp://ftp.rsasecurity.com/pub/cryptobytes/crypto2n2.pdfhttp://www.kremlinencrypt.com/kremlin.htmhttp://pauillac.inria.fr/~doligez/ssl/http://www.rsa.com/http://www.funet.fi/pub/crypt/cryptography/symmetric/rc4/rc4.revealed.gzhttp://www.rsa.com/http://www.esat.kuleuven.ac.be/~rijmen/rijndael/PropCorr.PDFhttp://www.esat.kuleuven.ac.be/~rijmen/rijndael/rijndaeldocV2.ziphttp://www.esat.kuleuven.ac.be/~rijmen/index.htmlhttp://csrc.nist.gov/encryption/aes/


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1.3.2 ASYMMETRIC CRYPTOGRAPHIC ALGORITHMS (Public Key

Algorithms):

Asymmetric encryption algorithms (public key algorithms) use different keys for

encryption and decryption, and the decryption key cannot (practically) be derived from the

encryption key. Public key methods are important because they can be used for transmitting

encryption keys or other data securely even when the parties have no opportunity to agree on a

secret key in private.

1.3.3 DIFFERENCE BETWEEN SYMMETRIC AND ASYMMETRIC

ALGORITHMS

Symmetric encryption algorithms encrypt and decrypt with the same key.Main advantages

of symmetric encryption algorithms are its security and high speed. Asymmetric encryption

algorithms encrypt and decrypt with different keys. Data is encrypted with a public key, and

decrypted with a private key. Asymmetric encryption algorithms (also known as public-key

algorithms) need at least a 3,000-bit key to achieve the same level of security of a 128-bit

symmetric algorithm. Asymmetric algorithms are incredibly slow and it is impractical to use

them to encrypt large amounts of data. Generally, symmetric encryption algorithms are much

faster to execute on a computer than asymmetric ones. The keys used in public-key encryption

algorithms are usually much longer than those used in symmetric encryption algorithms. This is

caused by the extra structure that is available to the cryptanalyst. There the problem is not that of

guessing the right key, but deriving the matching private key from the public key .In practice

they are often used together, so that a public-key algorithm is used to encrypt a randomly

generated encryption key, and the random key is used to encrypt the actual message using a

symmetric algorithm. This is sometimes called hybrid encryption.


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CHAPTER 2

BACKGROUND INFORMATION

2.1 BASICS OF RC6 ALGORITHM

2.1.1 RC6 BLOCK DIAGRAM


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FIG.2.1

2.1.2 BASIC OPERATIONS

RC6-w/r/b operates on units of four w-bit words using the

following six basic operations. The base-two logarithm of wwill be denoted by lg w.

a + b integer addition modulo 2w a - b integer subtraction modulo 2w a XOR b bitwise exclusive-or of w-bit words


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a X b integer multiplication modulo ab rotate the w-bit word a to the right by theAmount given by the least significant lg w bits of b

2.1.3 BASIC STEPS FOR RC6 ALGORITHM

\

2.2 ENCRYPTION

FIG 2.2 ENCRYPTION BLOCK DIAGRAM


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2.2.1 SIGNAL SPECIFICATION

A block diagram of the 16-bit RC6 encryptor and decryptor is shown in Figure 1. Control

signals are active high. The following gives a description of the input and output signals for the

encryptor.

1. Plaintext_e: This 16-bit data input signal corresponds to a word of plaintext data that isto be encrypted. Four consecutive 16-bit plaintext_e values form a 64-bit block that is to

be encrypted.

2. Round_keys_e: This 16-bit data input signal corresponds to one encryption round key. Atotal of 44 round keys are used to encrypt and decrypt the data. Although the encryptor

and decryptor use identical round keys for a given block of data, separate encryptor and

decryptor round keys are provided, since they receive the round keys at different times

and processor the round keys in reverse order. This also allows the decryptor to be

deciphering one block, while the encryptor is ciphering the next.

3. Start_e : This 1-bit control input signal tells the encryptor that it will start receivingplaintext_e during the next cycle. This signal should only go high for one cycle.

4. Reset: This 1-bit control input signal resets both the encryptor and decryptor. When resetoccurs, all registers are cleared and the controllers go to a known state.

5. Clock : This 1-bit input signal corresponds to the system clock for the encryptor anddecryptor. Values are to be latched into registers at the positive edge of the clock.

6. Ciphertext : This 16-bit data output signal corresponds to a word of ciphertext data thathas been encrypted and needs to be decrypted. Four consecutive 16-bit ciphertext values

form a 64-bit block that has been encrypted. The same signal is used as an input to the

decryptor.

7. Ready_e : This 1-bit control output signal indicates that the encryptor is ready to receivenew plaintext. It goes high following a reset signal and stays high until the start_e goes

high. Once the encryptor has finished encrypting the data ready_e goes high, until the

next time start_e goes high.

8. Start_d : This 1-bit control output signal tells the decryptor that the encryptor will startsending ciphertext during the next cycle. This signal should only go high for only one

cycle. This same signal is used as an input to the decryptor


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2.2.2 RC6 ENCRYPTION ALGORITHM

Input:

Plain text stored in four w-bit input registers A, B, C,D

Number r of rounds

w-bit round keys S[0, ,2r + 3]

Output:

Cipher text stored in A, B, C, D

Procedure:

B = B + S [0]

D = D + S [1]

for i = 1 to r do

{ t = (B X (2B + 1))


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The following gives a description of the input and output signals for the

decryptor.

1. Plaintext_d : This 16-bit data output signal corresponds to a word of plaintext data thathas been decrypted. Four consecutive 16-bit plaintext_d values form a 64-bit block thathas been decrypted. When the same round_keys are used, the plaintext_d produced

should be equivalent to the plaintext_e that was originally input.

2. Round_keys_d : This 16-bit data input signal corresponds to one decryption round key.(see the description of round_key_e for further details).

3. Start_d : (see previous description)4. Reset : (see previous description)5. Clock : (see previous description)6. Ciphertext : (see previous description)7. Ready_d : This 1-bit control output signal indicates that the decryptor is ready to

receive new ciphertext. It goes high following a reset signal and stays high until the

start_d goes high. Once the decryptor has finished decrypting the data ready_d goes

high, until the next time start_d goes high.

Input:

Cipher text stored in four w-bit input registers A, B,C, D

Number r of rounds

w-bit round keys S[0; ; 2r + 3]

Output:

Plaintext stored in A, B, C, D

Procedure:

C = CS [2r + 3]

A = AS [2r + 2]

for i = r down to 1 do

{

(A, B, C, D) = (D, A, B, C)

u = (D X (2D + 1))


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t = (B X (2B + 1)) > t) u

A = ((AS [2i]) >>> u) t

}

D = DS [1]

B = BS [0]


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CHAPTER 3

THEORITICAL ANALYSIS

3.1 MODULES BLOCK DIAGRAMS

FIG 3.1 DIGITAL CIRCUIT BLOCK DIAGRAM FOR ENCRYPTION

FIG 3.2 DIGITAL CIRCUIT BLOCK DIAGRAM FOR DECRYPTION


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3.3.1 KEY SCHEDULING

The key schedule of RC6-w/r/b is practically identical to the key schedule of RC5-w/r/b.

Indeed, the only difference is that for RC6-w/r/b, more words are derived from the user-supplied

key for use during encryption and decryption. isThe user supplies a key of b bytes, where 0 _ b _ 255. From this key, 2r + 4 words (w bits

each) are derived and stored in the array S[0; : : : ; 2r + 3]. This array is used in both encryption

and decryption.

The user supplies a key of b bytes. Sufficient zero bytes are appended to give a key

length equal to a non-zero integral number of words; these key bytes are then loaded in little-

endian fashion into an array of c w-bit (w = 32 bits in our case) words L [0], , L [c - 1]. Thus

the first byte of key is stored as the low-order byte of L [0], etc., and L [c - 1] is paddedWith high-order zero bytes if necessary. The number of w bit (32 bit) words that will be

generated for the additive round keys is 2r + 4 and these are stored in the array S [0; ;2r +

3]. the constants P32 = B7E15163 and Q32 = 9E3779B9 (hexadecimal) are the same magic

constants" as used in the RC5.

You may have wondered why there is array of 44. Because in encryption and decryption

process we add round keys to A and C in

A = ((A ^ t)


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s(0)


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FIG.3.3 FINITE STATE MACHINE FOR INPUT ENCRYPTION


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FIG 3.4 FINITE STATE MACHINE FOR INPUT DECRYPTION


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FIG.3.5 STATE MACHINE FOR OUTPUT ENCRYPTION

FIG.3.6 STATE MACHINE FOR OUTPUT DECRYPTION


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3.3 MULTIPLIER

The multiplier is used to compute the operation B*(2B+1). It is implemented as 2B 2+B.

so we need to do a squaring and a addition. the partial product array for a parallel square using a

multiplier The boxes indicate which terms may be combined using the equivalence aij+aji=2aij. In

the lower portion of figure 2aij is represented by placing aij one column to the left which has a

weighting of two times that of the current column. The square of operand a can be computed

with the reduced partial product array. So for 2b2 we place whole product one place to left which

has weighting 2 times that of previous. Our product is reduced to 9 from 16 due to this technique.

In product1 (p1) we have value of B for +B operation in 2B2+B operation and normal 16

products formed are reduced to 8 products due to partial product reduction array. Now you may

have wondered that why there are only 16 products while we are multiplying 16*16 so 32products of 32 bits should be there. But there are only 16 bits and 16 products because we are

using only lower 16 bits. This is so because we are having 20 rounds so for 20 rounds we are

multiplying b*b so if we use all 32 bits and multiply at end of 20 rounds our product will be too

large so we are using only lower 16 bits .

These 9 products formed are then input of Wallace tree multiplier. Wall ace tree will take

9 inputs and will produce final 16 bits one product. This is required by us to use as output of

2B2+B.


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3.3.1 WALLACE TREE

Figure below show the diagram of Wallace tree. Wallace tree have 2 components.

1. Carry save adder-CSA2. Carry look ahead-CLA

A Wallace tree is an efficient hardware implementation of a digital circuit that multiplies two

integers.

The Wallace tree has three steps:

1. Multiply (that is - AND) each bit of one of the arguments, by each bit of the other,yielding n2 results. Depending on position of the multiplied bits, the wires carry different

weights, for example wire of bit carrying result ofa2b3 is 32 (see explanation of weights

below).2. Reduce the number of partial products to two by layers of full and half adders.3. Group the wires in two numbers, and add them with a conventional adder.

FIG 3.8 WALLACE STRUCTURE
http://en.wikipedia.org/wiki/Computational_complexity_theoryhttp://en.wikipedia.org/wiki/Computer_hardwarehttp://en.wikipedia.org/wiki/Computer_hardwarehttp://en.wikipedia.org/wiki/Computational_complexity_theory


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3.3.1.1 CARRY SAVE ADDER

The carry-save unit consists ofn full adders, each of which computes a single sum and carry

bit based solely on the corresponding bits of the three input numbers. Given the three n - bit

numbers a, b, and c, it produces a partial sum ps and a shift-carry sc:

The entire sum can then be computed by:

1. Shifting the carry sequence sc left by one place.2. Appending a 0 to the front (most significant bit) of the partial sum sequence ps.3. Using a ripple carry adder to add these two together and produce the resulting n + 1-bit

value.

A ripple carry adder cannot compute a sum bit without waiting for the previous carry bit

to be produced, and thus has a delay equal to that ofn full adders. A carry-save adder

produces all of its output values in parallel. we have seven full adder in our carry save adder.

FIG. 3.9 CARRY SAVE ADDER
http://en.wikipedia.org/wiki/Adder_(electronics)#Full_adderhttp://en.wikipedia.org/wiki/Logical_shifthttp://en.wikipedia.org/wiki/Most_significant_bithttp://en.wikipedia.org/wiki/Adder_(electronics)#Ripple_carry_adderhttp://en.wikipedia.org/wiki/Adder_(electronics)#Ripple_carry_adderhttp://en.wikipedia.org/wiki/Most_significant_bithttp://en.wikipedia.org/wiki/Logical_shifthttp://en.wikipedia.org/wiki/Adder_(electronics)#Full_adder


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3.3.1.2 CARRY LOOK AHEAD METHOD

Carry look ahead logic uses the concepts of generating and propagating carries.

Although in the context of a carry look ahead adder, it is most natural to think of generating and

propagating in the context of binary addition, the concepts can be used more generally than this.

In the descriptions below, the word digitcan be replaced by bitwhen referring to binary addition.

FIG 3.10 CARRY LOOK AHEAD ADDER

The addition of two 1-digit inputs A andB is said to generate if the addition will always

carry, regardless of whether there is an input carry (equivalently, regardless of whether any less

significant digits in the sum carry). For example, in the decimal addition 52 + 67, the addition of

the tens digits 5 and 6 generates because the result carries to the hundreds digit regardless of

whether the ones digit carries (in the example, the ones digit does not carry (2+7=9)). In the case

of binary addition, A + B generates if and only if both A and B are 1. If we write G(A,B) to

represent the binary predicate that is true if and only ifA +B generates, we have:


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The addition of two 1-digit inputs A andB is said topropagate if the addition will carry

whenever there is an input carry (equivalently, when the next less significant digit in the sum

carries).. In the case of binary addition, A +B propagates if and only if at least one ofA orB

is 1. If we write P(A,B) to represent the binary predicate that is true if and only ifA + B

propagates, In the case of binary addition, this definition is expressed by:

Carry is given by,

Implementation details

Here we add sum and carry which are the output of carry save adder series and 3rd digit is

taken as 0 as we have only two 16 bit arrays to add. We add individual bits for example

P0(A,B)=A0 XOR B0

G0=A0 AND B0

C1=G0+(P0.C0)

C0=0

3.4 SWAP OPERATION

FIG.3.11 BLOCK DIAGRAM FOR SWAPING


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As shown in block diagram, first we perform XOR operation between two inputs then

store the result into temporary variable. After that temporary variable is further XORed with any

of two inputs.so we get swapped output.In RC6 algorithm by performing swap operation we get,

(A,B,C,D)=(B,C,D,A)

Formula for swapping can be written as,

temp_AB:= tempA xor tempB;

A


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CHAPTER 4

SOFTWARE INFORMATION

4.1 ABOUT XILINX 9.2

`We have used xilinx 9.2 for designing and verifying RC6 algorithm for

cryptography.

4.1.1 OVERVIEW OF XILINX

Integrated Software Environment (ISE) is the Xilinx design software suite that

allows you to take your design from design entry through Xilinx device programming. The ISE

Project Navigator manages and processes your design through the following steps in the ISE

design flow.

Design Entry

Design entry is the first step in the ISE design flow. During design entry, you create your

source files based on your design objectives. You can create your top-level design file using a

Hardware Description Language (HDL), such as VHDL, Verilog, or ABEL, or using aschematic. You can use multiple formats for the lower-level source files in your design.

Note If you are working with a synthesized EDIF or NGC/NGO file, you can skip design entry

and synthesis and start with the implementation process.

Synthesis

After design entry and optional simulation, you run synthesis. During this step, VHDL,

Verilog, or mixed language designs become netlist files that are accepted as input to the

implementation step.


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Implementation

After synthesis, you run design implementation, which converts the logical design into a

physical file format that can be downloaded to the selected target device. From Project

Navigator, you can run the implementation process in one step, or you can run each of the

implementation processes separately. Implementation processes vary depending on whether you

are targeting a Field Programmable Gate Array (FPGA) or a Complex Programmable Logic

Device (CPLD).

Verification

You can verify the functionality of your design at several points in the design flow. You

can use simulator software to verify the functionality and timing of your design or a portion of

your design. The simulator interprets VHDL or Verilog code into circuit functionality and

displays logical results of the described HDL to determine correct circuit operation. Simulation

allows you to create and verify complex functions in a relatively small amount of time. You can

also run in-circuit verification after programming your device.

Device Configuration

After generating a programming file, you configure your device. During configuration,

you generate configuration files and download the programming files from a host computer to a

Xilinx device.

4.1.2 MAIN STEPS FOR DESIGNING AND VERIFICATION IN RC6

USING XILINX

1) Write a program in VHDL or verilog code and check syntax..2) A diagram showing the logical hierarchy of your modules including module names and

brief descriptions of what each module does.

3) Detailed block diagrams for the encryptor and decryptor, which show registers,functional units, multiplexers, control signals, etc.


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4) State transition graphs or ASM charts for the finite state machines that control yourencryptor and decryptor.

5) Vhdl code for your encryptor, decryptor, key scheduler, and testbench. This code shouldbe commented well.

6) Pre-synthesis simulation results for the modules from part 5. Include comments andannotated waveform for ease of interpretation of results. Also indicate whether or not

results are correct and any known bugs.

4.2 ABOUT VHDL

The VHSIC Hardware Description Language (VHDL) is an industry standard languageused to describe hardware from the abstract to concrete level

4.2.1 INTRODUCTION

The language not only defines the syntax but also defines very clear simulation semanticsfor each language construct

It is strong typed language and is often verbose to write Provides extensive range of modeling capabilities, it is possible to quickly assimilate a

core subset of the language that is both easy and simple to understand without learning themore complex features

4.2.2 WHY USE VHDL?

Quick Time-to-Market Allows designers to quickly develop designs requiring tens of thousands of logic gates Provides powerful high-level constructs for describing complex logic Supports modular

design methodology and multiple levels of Hierchy One language for design and simulation Allows creation of device-independent designs that are portable to multiple vendors. Good

for ASIC Migration Allows user to pick any synthesis tool, vendor, or device

4.2.3 BASIC FEATURES OF VHDL

Supports for vendor defined libraries Concurrency Supports sequential statements Support for test and simulation


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Strongly typed language Supports hierchies Supports multivalued logic

4.2.4 BASIC TERMINOLOGY

To describe an entity, VHDL provides five different types of primary constructs, called" designunits. They are

Entity declaration Architecture body Configuration declaration Package declaration Package body

4.3 STEPS FOR DESIGNING RC6 ALGORITHM

STEP I) You will come to the blank project (next time will have the most-recent project loaded

by default).Click on File > New Project to start a new project

STEP II) Be sure to select HDL as the top-level module type. You can name your project in this

window.


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STEP III) In the next window, Be sure to select VHDL for Generated Simulation Language.

we can also select FPGA & CPLD family like VIRTEX , SPARTAN etc..

STEP IV) While making a new project then You may add new source file later also. ADD

SOURCE is used for adding previous VHDL files. REMOVE is used to remove previously

added source.


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STEP V) Now add existing source (a pointer) or add Copy of Source (create a new file from the

source). Source is usually a .vhd file. We have made in our project ENCRYP.vhd and

DECRYP.vhd.

STEP VI) In the next window ,.vhd file is ready to design our phogram.after designing an

algorithm we check it using CHECK SYNTAX from processes/ synthesis-xst.if it is successfullychecked then RTL schematic can be shown in the simulation.


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CHAPTER 5

IMPLEMENTATION & SIMULATION RESULT

5.1 HOW TO SIMULATE & IMPLEMENT RC6 ALGORITHM?

We have implemented cryptography in Xilinx 9.2i edition software.We have seen how to

make a program in Xilinx now we will see the results. And we will also come to know that how

to give inputs and how to check test bench and see output. RTL schematic shows a functional

digital circuit having inputs and outputs. Test bench waveform is used to check whethre our

digital circuit works perfectly or not.for that specific steps must be followed as described in this

section.

5.2 TESTING METHODOLOGY

We can test our project by two ways.

i)Design project using RTL SCHEMETIC

ii) Simulate project using TEST BENCH WAVEFORM

5.2.1 ABOUT RTL SCHEMATIC

Our design can be viewed using RTLschematic that,

1) A diagram showing the logical hierarchy of your modules including module names and brief

descriptions of what each module does.

2) Detailed block diagrams for the encryptor and decryptor, which show registers, functional

units, multiplexers, control signals, etc.

3) State transition graphs or ASM charts for the finite state machines that control your encryptor

and decryptor.4) VHDL code for your encryptor, decryptor, key scheduler, and testbench. This code

should be commented well.


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5.2.1.1 RTL SCHEMATIC FOR ENCRYPTORAfter checking syntex successfully, RTL schematic can be viewed from

PROCESSES/ VIEW RTL SCHEMATIC .It shows digital circuit input and output

diagram for RC6 ENCRYPTION algorithm.

5.2.1.2 RTL SCHEMATIC FOR DECRYPTOR

After checking syntex successfully, RTL schematic can be viewed from PROCESSES/

VIEW RTL SCHEMATIC .It shows digital circuit input and output diagram for RC6

DECRYPTION algorithm.


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5.2 ABOUT TEST BENCH WAVEFORM

Our design should be tested by developing a testbench that ,

(1) Reads in plaintext, user-supplied keys, and expected ciphertext from a file.

(2) Uses the key scheduler to take the user-supplied keys and generate the round keys.

(3) Send the appropriate the control signals, plaintext, and round keys to the encryptor and

decryptor.

(4) Tests to ensure that the ciphertext is correctly generated and that the plaintext from the

decryptor matches the plaintext to the encryptor. If discrepancies occur between the

expected results and actual results, errors should be reported.

Now steps for TEST BENCH WAVEFORM are as follows.

STEPI:-For giving the inputs we change from synthesis and implementation to behavioral

simulation and add a new source by right clicking on project name


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STEP II) then the screen appears as shown below . in that screen select a test bench waveform

and write the name we want to give to test bench .

STEP III) then in clock input window select single clock and give clock high and low time as

10ns and all other parameters as shown below.


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STEP IV)In fig below we can see how to give inputs to encryptor .inputs are given after delay of

20ns staring from 50ns and giving 16 bit input after every 20ns. 16 bit round keys are also given

as shown and a start_e signal is made high so that program takes inputs.

STEP V)In fig below we can see the output test bench of encryptor the cipher text is available

after 1800ns. The cipher text is available after ready_e signal goes high.this cipher text is given

to decryptor


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STEP VI:-Similarly output of encryptor is given to decryptor after same time delay as in

encryptor and start signal and round keys are also given

STEP VII:-When simulation is done we can see output of decryptor as shown below. The plain

text which was given in encryptor is obtained in decryptor output.


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TABLE 1 SYNTHESIS REPORT FOR ENCRYPTOR

States 12

Transitions 14

Inputs 2

Outputs 11

Clock rising edge

Reset positive

|Reset type asynchronous

Reset State 000001

Encoding automatic

Implementation automatic

TABLE 2 MACRO STATISTICS FOR ENCRYPTOR

FSMs 1

Adders/Subtractors 135

16-bit adder 135

Counters 1

7-bit up counter 1

Registers 197

Flip-Flops 197


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Latches 1

16-bit latch 1

Multiplexers 2

16-bit-16-to-1

multiplexer

2

Xors 16

16-bit xor2 2

16-bit xor3 14

TABLE 3 FINAL RESULTS FOR ENCRYPTOR

RTL Top Level Output File Name encryptor.ngr

Top Level Output File Name encryptor

Output Format NGC

Optimization Goal Speed

Keep Hierarchy YES

Target Technology SPARTAN 3

Macro Preserve YES

YES YES

YES YES

wysiwyg NO

Design Statistics # IOs 52


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TABLE 4 CELL USAGES FOR ENCRYPTOR

AND1 9915

AND2 4468

AND3 89

AND4 19

AND5 3

GND 1

INV 1587

OR2 3635

OR3 78

OR5 1

VCC 1

XOR2 33

FlipFlops/Latches 200

FDC 68

FDCE 112

FTC 4

LD 16

IO Buffers 52

IBUF 35


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OBUF 17

CPU:66.77 / 66.91 s

|Elapsed : 67.00 / 67.00s

Total memory usage is

265560 kilobytes

TABLE 5 SYNTHESIS REPORT FOR DECRYPTOR

States 12

Transitions 14

Inputs 2

Outputs 12

Clock clock (rising_edge)

Reset reset (positive)

Reset type asynchronous

Reset State 000001

Encoding automatic

Implementation automatic

TABLE6 MACRO STATISTICS FOR DECRYPTOR

# Adders/Subtractors 135

16-bit adder 129


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16-bit subtractor 6

# Counters 1

7-bit up 1

# Registers 12

1-bit register 1

16-bit register 11

# Comparators 1

# Logic shifters 2

16-bit shifter logical right 2

# Xors 78

1-bit xor2 62

16-bit xor2 2

16-bit xor3 14

TABLE 7 FINAL RESULTS FOR DECRYPTOR

RTL Top Level Output

File Name

decryptor.ngr

Top Level Output File

Name

decryptor

Output Format NGC

Optimization Goal Speed

Keep Hierarchy YES


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Target Technology SPARTAN 3

Macro Preserve YES

XOR Preserve YES

Clock Enable YES

wysiwyg NO

TABLE 8 CELL USAGE FOR DECRYPTOR

# BELS 10352

# AND2 4470

# AND3 181

# AND5 2

# GND 1

# INV 1957

# OR2 3480

# OR3 228

# OR4 1

# XOR2 32

# FlipFlops/Latches 191

# FDC 84

# FDCE 103

# FTC 4


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# IO Buffers 52

# IBUF 35

# OBUF 17

CPU : 66.24 / 67.56 s Elapsed : 66.00 /

67.00 s

Total memory usage is

261464 kilobytes


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CHAPTER 6

CONCLUSION AND FUTURE WORK

6.1 APPLICATION AREA

1. INTERNET E-COMMERCE2. MOBILE TELEPHON ENETWORKS3. BENK AUTOMATED TELLER MACHINE4. SECRET COMMUNICATION


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6.2 CONCLUSION

RC6 Is considered as secured and elegant choice due to its simplicity, security, performance and

efficiency

RC6 is best suited for implementation in FPGA and XILINX

Multiplication and addition are the major bottleneck as far as speed of encryption in RC6 cipher

is concerned. Nevertheless up to a great extent this short coming was tackled using pipelining in

our design

RC6 works best in non feedback mode. The highest speed/area ratio can be achieved in the same


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6.3 FUTURE SCOPE

1. Length of key can be made variable

2.

Word size can be increased

3. Smart card, mobile, digital camera and ATM can adopt this scheme by far greater extent4. This cryptography algorithm can be implemented on FPGA SPARTAN-3 KIT by user

defined functions. And hardware gives better results than software.


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CHAPTER 7

REFERENCE AND BIBLIGRAPHY

7.1 APPENDIX

7.1.1 ENCRYPTOR CODE

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

-- encryptor module declaration

entity encryptor is

port (

plaintext_e :in std_logic_vector(15 downto 0);-- 16 bit Plaintext output of decryptor

round_keyse :in std_logic_vector(15 downto 0);-- 16 bit roundkeys given to decryptor

start_e:in std_logic; --1 bit ready signal for encryptor

reset :in std_logic; --resetclock :in std_logic ; --clock

ready_e :out std_logic; -- 1 bit ready output of decryptor

ciphertext: out std_logic_vector(15 downto 0)) ;

end encryptor;

Architecture arch_encryptor of encryptor is

-------wallace tree

component multiplierport( B :in std_logic_vector(15 downto 0);

Product :out std_logic_vector(15 downto 0)

);

end component;


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-------- constant for key generation.

constant p:std_logic_vector(15 downto 0):= "1011011111100001";------constant value p

constant q:std_logic_vector(15 downto 0):= "1001111000110111";------constant value q

type s_tp is array(43 downto 0) of std_logic_vector(15 downto 0);--array of 44 * 16

signal s :s_tp;

type l_tp is array(42 downto 0) of std_logic_vector(15 downto 0);--array of 43 *16

signal l :l_tp;

--constant round_keyse : std_logic_vector(15 downto 0):= "0000000000000000";

--------- constants for the plain text fsm

constant out_idle:std_logic_vector(3 downto 0):= "0000";

constant out_A :std_logic_vector(3 downto 0):= "0001";

constant out_B :std_logic_vector(3 downto 0):= "0010";constant out_C :std_logic_vector(3 downto 0):= "0011";

constant out_D :std_logic_vector(3 downto 0):= "0100";

--------- signals needed for internal connections

signal cleanup_A,cleanup_C ,start_d1,last_round: std_logic;

signal next_state_out: std_logic_vector( 3 downto 0);

signal state:std_logic_vector(5 downto 0); --state of primary fsm

signal state_out:std_logic_vector(3 downto 0); -- state of plaintext fsm

signal utemp1,ttemp1:std_logic_vector(15 downto 0);

signal sig3,sig4:INTEGER RANGE 0 TO 15;

signal A_final,B_final,C_final,D_final:std_logic_vector(15 downto 0);

signal A,B,C,D : std_logic_vector(15 downto 0);

signal product1,product2 : std_logic_vector(15 downto 0);

begin

--------fsm for input --------

a1: multiplier port map (B,product1);

b1: multiplier port map (D,product2);

sig3


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--------key generation operation------

s(0)


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state


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--t= (D * (2D+1))

u_pre := product2;

t:= t_pre(11 downto 0)& t_pre(15 downto 12);

ttemp1


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temp_BC:= tempB xor tempC;

B


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--rounds are over

--now do the cleanup

if (cleanup_A='1') then

A_final


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state_out


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next_state_out


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component multiplier

port( B :in std_logic_vector(15 downto 0);

Product :out std_logic_vector(15 downto 0)

);

end component;

-- constants for the plain text fsm

constant idle:std_logic_vector(3 downto 0):= "0000";

constant out_A :std_logic_vector(3 downto 0):= "0001";

constant out_B :std_logic_vector(3 downto 0):= "0010";

constant out_C :std_logic_vector(3 downto 0):= "0011";

constant out_D :std_logic_vector(3 downto 0):= "0100";

--ct1, ttemp and utemp are temprary registers to hold the values of t, u and C.--signal round_keys_d_saved:std_logic_vector(15 downto 0);

signal ready_d_pre: std_logic; -- ready_d_pre is used to trigger the plaintext fsm (earlier version

of ready_d)

signal state:std_logic_vector(5 downto 0); --state of primary fsm

signal state_out:std_logic_vector(3 downto 0); -- state of plaintext fsm

signal sig3,sig4:integer range 0 TO 15;

signal last_round ,cleanup : std_logic;

signal A_final,B_final,C_final,D_final:std_logic_vector(15 downto 0);

signal utemp1,ttemp1 :std_logic_vector(15 downto 0);-------a_new

signal A, B, C, D :std_logic_vector(15 downto 0);

signal product1,product2 : std_logic_vector(15 downto 0);

---key constant------

constant p:std_logic_vector(15 downto 0):= "1011011111100001";

constant q:std_logic_vector(15 downto 0):= "1001111000110111";

type s_tp is array(43 downto 0) of std_logic_vector(15 downto 0);

signal s :s_tp;

type l_tp is array(42 downto 0) of std_logic_vector(15 downto 0);


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signal l :l_tp;

begin

a1: multiplier port map (B,product1);

b1: multiplier port map (D,product2);

sig3


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B '0');

C '0');

D '0');

ready_d '0');

TEMPB:=(others=>'0');

TEMPC:=(others=>'0');

TEMPD:=(others=>'0');

temp_AD:= (others=>'0');

temp_BA:= (others=>'0');

temp_CB:= (others=>'0');

temp_DC:= (others=>'0');elsif(clock'event and clock='1') then

case state is --synopsys parallel_case

when"000001"=>

if (start_d = '0') then

state


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C


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utemp1

state


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state


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if (reset='1') then

state_out


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7.2 BIBILOGRAPHY

www.google.com

www.wikipedia.com

http:/theory.csail.mit.edu/~rivest/RC6.pdf
http://www.wikipedia.com/http://www.wikipedia.com/

Documents

FINAL REPORT Cryptography