UCLA Extension Course: “Power Integrity and Noise Coupling in Integrated Circuits” Instructor: Cosmin Iorga, Ph.D.

Design Project Student name: ______________________________

Project Overview In this project you are part of an architectural exploration team for a sub-system board consisting of an integrated circuit mounted on a printed circuit board. The integrated circuit is manufactured in flip-chip technology and it is mounted on a Ball-Grid-Array (BGA) package. Further more, this integrated circuit contains a digital core, operating at 500 MHz clock frequency, and an analog block. Your task is to evaluate the power distribution network (PDN) in the overall chip/package/PCB sub-system. Part of this work you will estimate the frequency characteristics of the power distribution impedance as seen by the digital core, you will analyze the power distribution decoupling function and will recommend a set of capacitors that will reduce the PDN impedance, you will estimate the power distribution and substrate noise in the analog block, and you will make recommendations for the floorplan location of a voltage controlled oscillator (VCO) in this analog block. This VCO is a critical performance part of a phase-locked-loop (PLL) circuit and it is very sensitive to substrate and power supply noise, so you will choose a location that would minimize this noise.

Part 1: Power Distribution Network (PDN) Analysis and Modeling A. PDN Analysis Figure 1 shows a cross section diagram of the sub-system board. This board contains the BGA package with the flip-chip mounted on it, decoupling capacitors, and a voltage regulator module (VRM).

Figure 1 – Cross section of the chip/package/PCB sub-system board

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To simplify this project, the VRM is considered to have an ideal internal impedance, which is equal to zero at all frequencies. Additionally, only the power supply distribution to the digital core and analog block will be analyzed. All the other power domains including the power supplied to the input/output (I/O) cells will not be considered. Figure 2 shows a top view of the sub-system board. The dimensions of the board, package, VRM, and the spacing between components are listed in the figure.

Figure 2 – Top view drawing of the sub-system board The majority of supply current is assumed to flow between the VRM and the BGA package thorough the corresponding power/ground planes inside the PCB. For simplicity, this current is assumed to be uniformly distributed on the 1 inch wide cross-section of each of the power/ground planes. (Notice that 1 inch is the width of the VRM and BGA sides, and thus it is assumed to be the with of the current flow; notice additionally that 1 inch is also the spacing between the VRM and BGA, and the length of the current flow is assumed to be 1 inch) Chip Details The chip is fabricated in 0.13m CMOS process on a lightly doped p-type substrate. The chip dimensions are 3.4 mm x 3.4 mm and it has 16 x 16 connection pins (bumps) spaced at 200um center-to-center. Part of this chip is occupied by the analog block, which had the size 1.6 mm x 1.6 mm and 7 x 7 connection bumps. The rest of the chip is occupied by the digital core and I/O buffers. As I have mentioned above, we will not include the I/O buffers in this project work.

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The total number of pins for the entire chip is 16 x 16 = 256. Out of these pins, 80 are assigned to the digital core positive supply, 80 to the digital core ground, 8 to the analog block positive supply, and 8 to the analog block ground. The rest of pins are assigned to active signals. Package Details: The package is a 2.54 cm x 2.54 cm plastic flip-chip BGA type with decoupling capacitors, as shown in Figure 3.

Figure 3 – Top view of the BGA package Each capacitor array contains 8 independent capacitors connected to the package through “bump” type pins similar to the flip-chip interconnect. Three of these arrays are connected on the digital core supply and other three arrays are connected on the analog block supply. The remaining two arrays are connected to the I/O ring supply, which we will not cover in this project. Decoupling Capacitors The decoupling capacitors have predefined locations and sizes, which have been already defined based on design constraints; however, their values have not been determined yet. These locations are listed below:

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PCB capacitors: Digital Core Supply: 8 pads on the TOP side for 6032 size Tantalum capacitors; located at 3 cm from the center of

the package 8 pads on the TOP side for 0805 size ceramic capacitors: located at 2 cm from the center of

the package 8 pads on the BOTTOM side for 0805 size ceramic capacitors: located at 2 cm from the

center of the package Analog Block Supply: 8 pads on the TOP side for 6032 size Tantalum capacitors; located at 3 cm from the center of

the package 8 pads on the TOP side for 0805 size ceramic capacitors; located at 2 cm from the center of

the package 8 pads on the BOTTOM side for 0805 size ceramic capacitors; located at 2 cm from the

center of the package Package Capacitors: Digital Core Supply: 3 pads for 4x4 pins LICA (Low Inductance Capacitor Array); located at a distance of 1cm

from the center of the die Analog Core Supply: 3 pads for 4x4 pins LICA (Low Inductance Capacitor Array); located at a distance of 1cm

from the center of the die B. PDN Modeling In this section you will build models for the significant elements in the power distribution paths to the digital core and analog block. You will analyze these elements one by one and calculate their inductance, resistance, and for some of them also the capacitance.

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Interconnects chip to package and package to PCB Figure 4 shows a detailed drawing of the chip to package and package to PCB interfaces for the digital core and for the analog block.

Figure 4 - Detailed drawing of the chip to package and package to PCB interfaces There are four calculations that need to be done, chip-to-package interconnects on the digital core and on the analog block, and package to PCB interconnects also on the digital core and on the analog block. For each case, the interconnect path is approximated as two cylindrical wires of diameter, length, and spacing as shown in the figure. Consider each of these four paths isolated (one path = one pair of interconnect wires), and neglect the interaction with the other paths.

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Neglect the internal inductance of the wires and express the inductance as the sum of self-inductance and mutual inductance; use equation (1.15) for self-inductance and equation (1.17) for mutual inductance. Consider the relative permeability of the wires and surrounding materials = 1, and the permeability of free air = 4*π*10^-7 H/m, and resistivity = 1.7*10^-8 Ohms/m Calculations and results Chip-to-Package Digital Supply Interconnect Resistance and Inductance

Chip to Package Digital Supply Interconnect

R via (Ohms) L via (pH)

VDDD 0.000226 8.63

VSSD 0.000226 8.63 Chip-to-Package Analog Supply Interconnect Resistance and Inductance

Chip to Package Analog Supply Interconnect

R via (Ohms) L via (pH) VDDA 0.000902 34.52

VSSA 0.000902 34.52 Package-to-PCB Digital Core Interconnect Resistance and Inductance Package to PCB Digital Supply Interconnect R via (Ohms) L via (pH) VDDD 0.000136 344.96 VSSD 0.000136 344.96

Package-to-PCB Analog Core Interconnect Resistance and Inductance Package to PCB Analog Supply Interconnect R via (Ohms) L via (pH) VDDA 0.000192 487.78

VSSA 0.000192 487.78

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Package Plane Capacitance, Resistance, and Inductance Figure 5 shows the Package stack-up definition and the dimensions and electric parameters of each layer.

Figure 5 - Package stack-up definition Both the digital core and analog block share the same power plane in the package. Notice that the digital core power and ground planes are assigned next to each other, however, the analog block power plane is further down, below the I/O power plane. Notice that this stack-up definition is for the purpose of this project only and it is not intended to optimize the power distribution network. (in other words, in this project we want to see some noise that we further try to reduce) So the only plane capacitance that we need to calculate is the capacitance between the VDDD and VSSD planes. The inductance, however, needs to be calculated for both digital and analog paths: digital includes the VDDD – VSSD planes and analog includes VDDA – VSSD planes. The resistance needs to be calculated for all power/ground planes. Use the following formula for calculating the plane inductance: L = *t*l/w, where is the magnetic permeability, t is the dielectric thickness between the two planes, l is the length of the electric current through the plane, and w is the width of the electric current through the plane. Consider the relative permeability of the conductive materials and surrounding materials = 1, and the permeability of free air = 4*π*10^-7 H/m, the permitivity of free space = 8.854*10^-12 F/m) and resistivity = 1.7*10^-8 Ohms/m. Approximate the current width as the package side dimension = 25400 m, current length as 100 m.

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Calculation and Results

Layer Signal/Power Thickness (um) Dk

Plane inductance (pH)

Plane capacitance (pF)

Plane resistance (Ohms)

TOP Signal 15 1 4.46E-06 D1 30 4 M1 VDDD 15 1 4.46E-06 D2 30 4 0.148 666.128 M2 VSSD 15 1 4.46E-06 D3 30 4 M3 Signal 15 1 4.46E-06 Dcore 300 4 2.152 45.940 M4 Signal 15 1 4.46E-06 D4 30 4 M5 VDDIO 15 1 4.46E-06 D6 30 4 0.148 666.128 M6 VDDA 15 1 4.46E-06 D7 30 4

BOTTOM Signal 15 1 4.46E-06 PCB Plane Capacitance, Resistance, and Inductance Figure 6 shows the Package stack-up definition and the dimensions and electric parameters of each layer.

Figure 6 - Package stack-up definition

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Notice that there are two ground planes labeled VSS, and we assume that there are both connected together. The inductance and resistance need to be calculated for the effective current path, which is 1 inch wide and 1 inch long, and the capacitance needs to be calculated for the entire plane area, of 3 inches x 4 inches. Also notice that the dimensions are now expressed in inches / mils. (1000mils in 1 inch) Use the following formula for calculating the plane inductance: L = *t*l/w, where is the magnetic permeability, t is the dielectric thickness between the two planes, l is the length of the electric current through the plane, and w is the width of the electric current through the plane. Consider the relative permeability of the conductive materials and surrounding materials = 1, and the permeability of free air = 4*π*10^-7 H/m, the permitivity of free space = 8.854*10^-12 F/m) and resistivity = 1.7*10^-8 Ohms/m. Approximate the current width as the package side dimension = 1 inch (25400 m), current length as the distance to VRM = 1 inch. Calculation and Results PCB

Layer Signal/Power Thickness (mils) Dk

Plane inductance (pH)

Plane capacitance (pF)

Plane resistance (Ohms)

TOP Signal 1.4 1 0.0004781 D1 40 5 M1 VDDD 1.4 1 0.0004781 D2 20 5 638.372 606.933 M2 VSS 1.4 1 0.0004781 D3 10 5 M3 Signal 1.4 1 0.0004781 Dcore 10 5 1046.929 370.081 M4 Signal 1.4 1 0.0004781 D4 10 5 M5 VSS 1.4 1 0.0004781 D6 20 5 638.372 606.933 M6 VDDA 1.4 1 0.0004781 D7 40 5

BOTTOM Signal 1.4 1 0.0004781 Mounting Inductance and Resistance of the Package Decoupling Capacitors The package mounting inductance will be calculated for each capacitor in the LICA array, and for simplicity we will assume that there is no mutual inductance coupling between different capacitor interconnects/vias in the same array. Figure 7 shows a detailed drawing of the LICA capacitor array mounting on the package.

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Figure 7 - LICA capacitor array mounted on the package For each capacitor, the interconnect path is approximated as two cylindrical wires of diameter, length, and spacing as shown in the figure (neglect any horizontal current for these type of capacitors). Consider each capacitor’s paths isolated (one path = one pair of interconnect wires), and neglect the interaction with the other capacitors in the same array. Neglect the internal inductance of the wires and express the inductance as the sum of self-inductance and mutual inductance; use equation (1.15) for self-inductance and equation (1.17) for mutual inductance. Consider the relative permeability of the wires and surrounding materials = 1, and the permeability of free air = 4*π*10^-7 H/m, and resistivity = 1.7*10^-8 Ohms/m Calculations and results Package Decoupling Capacitors Mounting Inductance and Resistance Package Decoupling Capacitors

Resistance one via (Ohms)

L_self one via pair (pH)

Mutual Inductance one via pair (pH)

Inductance single path (pH)

Total Mounting Inductance (pH)

1.22E-03 21.55 -65.07 21.55 479.70

3.38E-02 2260.73 1802.59 458.15 Mounting Inductance and Resistance of the PCB Decoupling Capacitors Figure 8 shows a detailed drawing of the three cases of decoupling capacitor mounting on the PCB.

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Figure 8 - Decoupling capacitor mounting on the PCB (digital core) Assume for simplicity that the transient current has a circular cross-section having a diameter equal to the via diameter. Neglect the internal inductance of the current flow and express the inductance as the sum of self-inductance and mutual inductance on all four sides of the loop; assume current flows in a rectangular loop like the one shown in Fig.1.13 of the textbook. Use equation (1.15) for self-inductance and equation (1.17) for mutual inductance. Set negative mutual inductances to zero, as we discussed for homework problem 2 in week 2. Consider the relative permeability of the conductive material and surrounding dielectric materials = 1, and the permeability of free air = 4*π*10^-7 H/m, and resistivity = 1.7*10^-8 Ohms/m. Calculations and results Top side 0805 Capacitor Mounting Inductance and Resistance 0805 top layer PCB Decoupling Capacitor 2

Resistance one via (Ohms)

L_self one via pair (pH)

Mutual Inductance one via pair (pH)

Inductance single path (pH)

Total Mounting Inductance (pH)

3.31E-01 663.87 -347.40 663.87 5064.25

8.17E-01 2316.36 448.11 1868.25

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Bottom side 0805 Capacitor Mounting Inductance and Resistance 0805, bottom layer PCB Decoupling Capacitor 1

Resistance one via (Ohms)

L_self one via pair (pH)

Mutual Inductance one via pair (pH)

Inductance single path (pH)

Total Mounting Inductance (pH)

6.35E-01 1652.49 -285.78 1652.49 7937.70

8.17E-01 2316.36 -41.03 2316.36 Top side 6032 Tantalum Capacitor Mounting Inductance and Resistance Tantalum (pH)

Resistance one via (Ohms)

L_self one via pair (pH)

Mutual Inductance one via pair (pH)

Inductance single path (pH)

Total Mounting Inductance (pH)

3.31E-01 663.87 -790.23 663.87 16475.73

3.31E+00 13656.99 6082.99 7574.00 Notice due to symmetry that for the analog block decoupling capacitors, the top 0805 has the same mounting inductance and resistance as the bottom 0805 digital core capacitor. Similarly, the analog block bottom 0805 capacitor has the same mounting inductance and resistance as the top 0805 digital core capacitor. For the analog region assume that the tantalum capacitors are mounted on the bottom side of the PCB and have the same mounting inductance and capacitance as the digital core Tantalum capacitors.

Part 2: Simulate the Digital Core PDN Frequency Profile In this part we will insert the calculated values form part 1 into the ChipQuake Power Integrity Explorer software tool and we will simulate the digital core power delivery network impedance frequency profile. Frequency sweep without decoupling capacitors Start ChipQuake and load all the values calculated in Part 1 of the project. Disable all decoupling capacitors by un-checking the “Enable” check box on each capacitor. Run a frequency sweep simulation.

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ChipQuake settings:

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Simulation Results: Digital Core PDN Impedance:

Each time you select a signal to be displayed you also need to click on the “Update” button on the waveform viewer. Notice that in this setup no decoupling capacitors have been enabled. Adding Decoupling Capacitors Enable the default decoupling capacitors on the PCB digital core section also by checking the “Placed/OPEN” checkbox for each of them. Simulate the impedance characteristics and compare with the initial case (without capacitors). Comment on the differences observed. Save the state file and include a screenshot of the ChipQuake window here.

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The PCB decoupling capacitors lowered the PDN impedance within a frequency range from 100kHz to 100MHz. The impedance peak at around 700MHz is still there and a second peak at around 200MHz showed up. Enable the default decoupling capacitors on the package digital core section (C1 to C3) by checking the “Placed/OPEN” checkbox for each of them.

The package decoupling capacitors suppressed the impedance peak at 200MHz but the peak at 700MHz is still there.

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This concludes Part 2. We will come back to this setup later and optimize the values of the capacitors.

Part 3: Estimation of power/ground and substrate noise in the analog block Mapping the Substrate and Power Supply Noise in the Analog Block Region Start ChipQuake and load the “func.txt” state file. Enable the default decoupling capacitors on the package digital core section for both analog and digital supplies by checking the “Placed/OPEN” checkbox for each of them (if they are not already enabled). Enable the default decoupling capacitors on the PCB digital and analog sections also by checking the “Placed/OPEN” checkbox for each of them (if they are not already enabled). This time the substrate trace shows the coupled substrate noise within the swept frequency range at the defined (x,y) location in the analog block. The power supply trace shows the noise on the power supply in the analog region at the same (x,y) location. The two-dimensional maps below show the power supply and substrate noise distribution across the analog block region. Notice that these values are for the defined frequency in the simulation control section of the ChipQuake window. For other frequencies set the frequency value and re-simulate. In this project the digital core runs a clock at 500Mhz, so we are interested to evaluate the noise coupling into the analog region at this frequency. Set the frequency to 500MHz and re-simulate. Notice the noise variations across the analog block region. Insert the ChipQuake window screenshot here.

Power supply voltage in the analog region:

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Part 4 – A. Optimize the Decoupling Capacitors Use Kemet Spice program (the same we used in a previous homework assignment) to select decoupling capacitors. For the PCB use Kemet type 0805 X7R ceramic capacitors and Kemet 6032-28 type Tantalum Commercial SM capacitors, rated for 6.3V. You can place up to eight capacitors of each type on the PCB. Add the ESL to the mounting inductance and ESR to the mounting capacitance. Each type of capacitor has a specific ESL and ESR (use the value at the resonance peak). Since this process is time consuming, for simplification you may use the same ESL = 1nH and ESR = 0.06 Ohms for all ceramic capacitors, and ESL = 2.2 nH and ESR = 0.15 Ohms for Tantalum capacitors. For the package use LICA capacitors (don’t need to look for datasheet), with ESL=15pH and ESR=0.2 Ohms, and values between 100pF and 220nF. You can use up to three values on the package, each value having the multiplicity = 8 since there are 8 capacitors in a package. Start ChipQuake software program and load the digital core positive supply measurement state. Simulate the impedance characteristic and notice the 1kHz to 1GHz frequency range. This is the range where we want to minimize the impedance. Place 1 to 3 capacitors on the package digital core supply (C1 to C3) by checking the “Placed/OPEN” checkbox for each of them. Enter the ESL value as the sum of capacitor ESL and the mounting inductance. Enter the ESR as the sum of the capacitor’s ESR and the resistance of the mounting resistance. The distance should be preset and you do not to change it (C3 on the PCB is the Tantalum capacitor. Simulate the impedance characteristics and compare with the initial case (without capacitors). Change capacitor values, re-simulate, and notice the effect. You may need to try various combinations of capacitors to reduce the impedance at all frequencies. (hint: you may not be able to reduce significantly the impedance spike at about 500 MHz, so do not spend excessive time trying to reduce that one) When you consider that you have finished reducing the impedance in the above mentioned frequency range, 1kHz – 1GHz, save the state file and include a ChipQuake window screenshot here.

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B. Recommend the Location of a VCO Circuit in the Analog Block Floorplan Analyze the noise distribution in the substrate and power supply and determine a location for the 100m x 100 m VCO circuit. This VCO is a critical performance part of a phase-locked-loop (PLL) circuit and it is very sensitive to substrate and power supply noise, so you will choose a location that would minimize this noise. Use as criteria the sum of substrate and power supply noise, considering that the VCO is equally sensitive to both substrate and power supply noise. Mark the approximate location for the VCO on a screenshot (using Microsoft Paint or any other image processing software). Insert the ChipQuake window screenshot here.

VCO location was chosen based on the minimum power supply noise (VCCA – VSSA) that also had reasonable low substrate noise.

C. Evaluate the Effects of Implementing a Shunting Guard Ring Suppression Technique The chip manufacturing technology allows the insertion of either a shunting guard ring or an isolation moat around the analog block region. You will now evaluate the effects of each of this technique and make your recommendation if to use any of these techniques and which one to use.

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Implement a shunting guard ring surrounding the analog block. Technology and floorplan allow the implementation of a 1 m wide p+ substrate guard ring biased from the VSSA negative supply of the analog block. The vertical resistance of the p+ diffusion is 25000 Ohms/um^2. The analog block dimensions are 1.6 mm x 1.6 mm. Calculate the total vertical resistance (shunting resistance) of the guard ring and insert this value in the ChipQuake tool. Re-simulate and analyze the guard ring effects on the coupled noise into the analog block. Insert a ChipQuake window screenshot here. (Hint: the analog block is located in a corner of the chip, so the guard ring will be placed only on two sides. Calculate the guard ring area as two sections each of 1 um x 1600 um, thus a total of 2 * (1 um * 1600 um). The vertical resistance then will be equal to R= 25000Ohms/um^2 divided by 3200um^2 = 7.8 Ohms).

Adding a shunting guard ring reduced the substrate noise at the edge of the analog region from 31mV to 18mV (red colored edges). The substrate noise inside the analog region did not change significantly. The power supply noise did not change at all. D. Evaluate the Effects of Implementing a High Resistive Guard Ring (Moat) Suppression Technique Implement a high-resistive moat surrounding the analog block. The technology allows 50um wide moat, with a resistance of 500 kOhms-µm. The analog block dimensions are 1.6 mm x 1.6 mm. Calculate the total series resistance of the surrounding moat and insert this value in the ChipQuake tool. Re-simulate and analyze the moat effects on the coupled noise into the analog block. Insert the ChipQuake window screenshot here.

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(Hint: the analog block is located in a corner of the chip, so the moat will be placed only on two sides. Calculate the total length of the moat as two sections each of 1600 um each, thus a total of 2 * 1600 um = 3200 um. Approximate the moat length with this value: 3200 um. The total moat resistance will then be equal to R=500kOhms / 3200 um = 156 Ohms)

Comment on the effects of each of these suppression techniques and make your recommendation if to use any of these techniques and which one to use. Adding a high resistive moat around the analog region reduced the substrate noise from 31mV to 2mV. The maximum substrate noise in the analog region is now 8mV around the VDDA pins (this is unchanged from the case without isolation moat). Between the two techniques the high resistive isolation moat gives better results at suppressing the substrate noise in the analog region.

Conclusions This project helped me understand and analyze various aspects of power integrity and noise coupling. The calculation of decoupling capacitors mounting inductance and the power planes inductance, resistance, and capacitance was a good exercise of paying attention to units. Package parameters are typically expressed in standard units (micrometer) while PCB parameters are typically expressed in mils. Using the wrong units create errors that may or may not be immediately noticed.

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Capacitors optimization was a good exercise that stimulated my intuitive and analytical skills. However, even after optimization there were still left ranges of frequency with relatively high impedance. I have noticed that the decoupling capacitors do not lower the impedance at very low and very high frequency values. PCB capacitors lowered the impedance at medium frequency range and package capacitors lowered the impedance at higher frequency values. The task to choose a location for the VCO showed that there is no "ideal" location so a tradeoff between power supply and substrate noise had to be made. I have chosen to minimize the power supply noise since I think the VCO circuit may be more sensitive to power supply noise than to substrate noise. The high resistive moat around the analog region has suppressed the substrate noise almost completely at the edge with the digital region (31mV to 2mV). The substrate noise in the analog region around the VDDA pins remained unchanged. The shunting guard ring has suppressed the substrate noise to about half at the edge with digital region. Between the two techniques the high resistive isolation moat gives better results at suppressing the substrate noise in the analog region. Further work may look into changing the chip decoupling capacitors and technology parameters to see if we can lower the PDN impedance at higher frequencies.