Figure 81 A 2-bit asynchronous binary counter. Open file F08-01
to verify operation. Thomas L. Floyd Digital Fundamentals, 9e
Copyright 2006 by Pearson Education, Inc. Upper Saddle River, New
Jersey 07458 All rights reserved. Slide 2 Figure 82 Timing diagram
for the counter of Figure 81. As in previous chapters, output
waveforms are shown in green. Thomas L. Floyd Digital Fundamentals,
9e Copyright 2006 by Pearson Education, Inc. Upper Saddle River,
New Jersey 07458 All rights reserved. Slide 3 Figure 83 Three-bit
asynchronous binary counter and its timing diagram for one cycle.
Open file F08-03 to verify operation. Thomas L. Floyd Digital
Fundamentals, 9e Copyright 2006 by Pearson Education, Inc. Upper
Saddle River, New Jersey 07458 All rights reserved. Slide 4 Figure
84 Propagation delays in a 3-bit asynchronous (ripple-clocked)
binary counter. Thomas L. Floyd Digital Fundamentals, 9e Copyright
2006 by Pearson Education, Inc. Upper Saddle River, New Jersey
07458 All rights reserved. Slide 5 Figure 85 Four-bit asynchronous
binary counter and its timing diagram. Open file F08-05 and verify
the operation. Thomas L. Floyd Digital Fundamentals, 9e Copyright
2006 by Pearson Education, Inc. Upper Saddle River, New Jersey
07458 All rights reserved. Slide 6 Figure 86 An asynchronously
clocked decade counter with asynchronous recycling. Thomas L. Floyd
Digital Fundamentals, 9e Copyright 2006 by Pearson Education, Inc.
Upper Saddle River, New Jersey 07458 All rights reserved. Slide 7
Figure 87 Asynchronously clocked modulus-12 counter with
asynchronous recycling. Thomas L. Floyd Digital Fundamentals, 9e
Copyright 2006 by Pearson Education, Inc. Upper Saddle River, New
Jersey 07458 All rights reserved. Slide 8 Figure 88 The 74LS93
4-bit asynchronous binary counter logic diagram. (Pin numbers are
in parentheses, and all J and K inputs are internally connected
HIGH.) Thomas L. Floyd Digital Fundamentals, 9e Copyright 2006 by
Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All
rights reserved. Slide 9 Figure 89 Two configurations of the 74LS93
asynchronous counter. (The qualifying label, CTR DIV n, indicates a
counter with n states.) Thomas L. Floyd Digital Fundamentals, 9e
Copyright 2006 by Pearson Education, Inc. Upper Saddle River, New
Jersey 07458 All rights reserved. Slide 10 Figure 810 74LS93
connected as a modulus-12 counter. Thomas L. Floyd Digital
Fundamentals, 9e Copyright 2006 by Pearson Education, Inc. Upper
Saddle River, New Jersey 07458 All rights reserved. Slide 11 Figure
811 A 2-bit synchronous binary counter. Thomas L. Floyd Digital
Fundamentals, 9e Copyright 2006 by Pearson Education, Inc. Upper
Saddle River, New Jersey 07458 All rights reserved. Slide 12 Figure
812 Timing details for the 2-bit synchronous counter operation (the
propagation delays of both flip-flops are assumed to be equal).
Thomas L. Floyd Digital Fundamentals, 9e Copyright 2006 by Pearson
Education, Inc. Upper Saddle River, New Jersey 07458 All rights
reserved. Slide 13 Figure 813 Timing diagram for the counter of
Figure 811. Thomas L. Floyd Digital Fundamentals, 9e Copyright 2006
by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All
rights reserved. Slide 14 Figure 814 A 3-bit synchronous binary
counter. Open file F08-14 to verify the operation. Thomas L. Floyd
Digital Fundamentals, 9e Copyright 2006 by Pearson Education, Inc.
Upper Saddle River, New Jersey 07458 All rights reserved. Slide 15
Figure 815 Timing diagram for the counter of Figure 814. Thomas L.
Floyd Digital Fundamentals, 9e Copyright 2006 by Pearson Education,
Inc. Upper Saddle River, New Jersey 07458 All rights reserved.
Slide 16 Figure 816 A 4-bit synchronous binary counter and timing
diagram. Points where the AND gate outputs are HIGH are indicated
by the shaded areas. Thomas L. Floyd Digital Fundamentals, 9e
Copyright 2006 by Pearson Education, Inc. Upper Saddle River, New
Jersey 07458 All rights reserved. Slide 17 Figure 817 A synchronous
BCD decade counter. Open file F08-17 to verify operation. Thomas L.
Floyd Digital Fundamentals, 9e Copyright 2006 by Pearson Education,
Inc. Upper Saddle River, New Jersey 07458 All rights reserved.
Slide 18 Figure 818 Timing diagram for the BCD decade counter (Q 0
is the LSB). Thomas L. Floyd Digital Fundamentals, 9e Copyright
2006 by Pearson Education, Inc. Upper Saddle River, New Jersey
07458 All rights reserved. Slide 19 Figure 819 The 74HC163 4-bit
synchronous binary counter. (The qualifying label CTR DIV 16
indicates a counter with sixteen states.) Thomas L. Floyd Digital
Fundamentals, 9e Copyright 2006 by Pearson Education, Inc. Upper
Saddle River, New Jersey 07458 All rights reserved. Slide 20 Figure
820 Timing example for a 74HC163. Thomas L. Floyd Digital
Fundamentals, 9e Copyright 2006 by Pearson Education, Inc. Upper
Saddle River, New Jersey 07458 All rights reserved. Slide 21 Figure
821 The 74F162 synchronous BCD decade counter. (The qualifying
label CTR DIV 10 indicates a counter with ten states.) Thomas L.
Floyd Digital Fundamentals, 9e Copyright 2006 by Pearson Education,
Inc. Upper Saddle River, New Jersey 07458 All rights reserved.
Slide 22 Figure 822 Timing example for a 74F162. Thomas L. Floyd
Digital Fundamentals, 9e Copyright 2006 by Pearson Education, Inc.
Upper Saddle River, New Jersey 07458 All rights reserved. Slide 23
Figure 823 A basic 3-bit up/down synchronous counter. Open file
F08-23 to verify operation. Thomas L. Floyd Digital Fundamentals,
9e Copyright 2006 by Pearson Education, Inc. Upper Saddle River,
New Jersey 07458 All rights reserved. Slide 24 Figure 824 Thomas L.
Floyd Digital Fundamentals, 9e Copyright 2006 by Pearson Education,
Inc. Upper Saddle River, New Jersey 07458 All rights reserved.
Slide 25 Figure 825 The 74HC190 up/down synchronous decade counter.
Thomas L. Floyd Digital Fundamentals, 9e Copyright 2006 by Pearson
Education, Inc. Upper Saddle River, New Jersey 07458 All rights
reserved. Slide 26 Figure 826 Timing example for a 74HC190. Thomas
L. Floyd Digital Fundamentals, 9e Copyright 2006 by Pearson
Education, Inc. Upper Saddle River, New Jersey 07458 All rights
reserved. Slide 27 Figure 827 General clocked sequential circuit.
Thomas L. Floyd Digital Fundamentals, 9e Copyright 2006 by Pearson
Education, Inc. Upper Saddle River, New Jersey 07458 All rights
reserved. Slide 28 Figure 828 State diagram for a 3-bit Gray code
counter. Thomas L. Floyd Digital Fundamentals, 9e Copyright 2006 by
Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All
rights reserved. Slide 29 Figure 829 Examples of the mapping
procedure for the counter sequence represented in Table 87 and
Table 88. Thomas L. Floyd Digital Fundamentals, 9e Copyright 2006
by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All
rights reserved. Slide 30 Figure 830 Karnaugh maps for
present-state J and K inputs. Thomas L. Floyd Digital Fundamentals,
9e Copyright 2006 by Pearson Education, Inc. Upper Saddle River,
New Jersey 07458 All rights reserved. Slide 31 Figure 831 Three-bit
Gray code counter. Open file F08-31 to verify operation. Thomas L.
Floyd Digital Fundamentals, 9e Copyright 2006 by Pearson Education,
Inc. Upper Saddle River, New Jersey 07458 All rights reserved.
Slide 32 Figure 832 Thomas L. Floyd Digital Fundamentals, 9e
Copyright 2006 by Pearson Education, Inc. Upper Saddle River, New
Jersey 07458 All rights reserved. Slide 33 Figure 833 Thomas L.
Floyd Digital Fundamentals, 9e Copyright 2006 by Pearson Education,
Inc. Upper Saddle River, New Jersey 07458 All rights reserved.
Slide 34 Figure 834 Thomas L. Floyd Digital Fundamentals, 9e
Copyright 2006 by Pearson Education, Inc. Upper Saddle River, New
Jersey 07458 All rights reserved. Slide 35 Figure 835 State diagram
for a 3-bit up/down Gray code counter. Thomas L. Floyd Digital
Fundamentals, 9e Copyright 2006 by Pearson Education, Inc. Upper
Saddle River, New Jersey 07458 All rights reserved. Slide 36 Figure
836 J and K maps for Table 811. The control input, Y, is treated as
a fourth variable. Thomas L. Floyd Digital Fundamentals, 9e
Copyright 2006 by Pearson Education, Inc. Upper Saddle River, New
Jersey 07458 All rights reserved. Slide 37 Figure 837 Three-bit
up/down Gray code counter. Thomas L. Floyd Digital Fundamentals, 9e
Copyright 2006 by Pearson Education, Inc. Upper Saddle River, New
Jersey 07458 All rights reserved. Slide 38 Figure 838 Two cascaded
counters (all J and K inputs are HIGH). Thomas L. Floyd Digital
Fundamentals, 9e Copyright 2006 by Pearson Education, Inc. Upper
Saddle River, New Jersey 07458 All rights reserved. Slide 39 Figure
839 Timing diagram for the cascaded counter configuration of Figure
838. Thomas L. Floyd Digital Fundamentals, 9e Copyright 2006 by
Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All
rights reserved. Slide 40 Figure 840 A modulus-100 counter using
two cascaded decade counters. Thomas L. Floyd Digital Fundamentals,
9e Copyright 2006 by Pearson Education, Inc. Upper Saddle River,
New Jersey 07458 All rights reserved. Slide 41 Figure 841 Three
cascaded decade counters forming a divide-by-1000 frequency divider
with intermediate divide-by-10 and divide- by-100 outputs. Thomas
L. Floyd Digital Fundamentals, 9e Copyright 2006 by Pearson
Education, Inc. Upper Saddle River, New Jersey 07458 All rights
reserved. Slide 42 Figure 842 Thomas L. Floyd Digital Fundamentals,
9e Copyright 2006 by Pearson Education, Inc. Upper Saddle River,
New Jersey 07458 All rights reserved. Slide 43 Figure 843 A
divide-by-100 counter using two 74F162 decade counters. Thomas L.
Floyd Digital Fundamentals, 9e Copyright 2006 by Pearson Education,
Inc. Upper Saddle River, New Jersey 07458 All rights reserved.
Slide 44 Figure 844 A divide-by-40,000 counter using 74HC161 4-bit
binary counters. Note that each of the parallel data inputs is
shown in binary order (the right-most bit D 0 is the LSB in each
counter). Thomas L. Floyd Digital Fundamentals, 9e Copyright 2006
by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All
rights reserved. Slide 45 Figure 845 Decoding of state 6 (110).
Open file F08-45 to verify operation. Thomas L. Floyd Digital
Fundamentals, 9e Copyright 2006 by Pearson Education, Inc. Upper
Saddle River, New Jersey 07458 All rights reserved. Slide 46 Figure
846 A 3-bit counter with active-HIGH decoding of count 2 and count
7. Open file F08-46 to verify operation. Thomas L. Floyd Digital
Fundamentals, 9e Copyright 2006 by Pearson Education, Inc. Upper
Saddle River, New Jersey 07458 All rights reserved. Slide 47 Figure
847 A basic decade (BCD) counter and decoder. Thomas L. Floyd
Digital Fundamentals, 9e Copyright 2006 by Pearson Education, Inc.
Upper Saddle River, New Jersey 07458 All rights reserved. Slide 48
Figure 848 Outputs with glitches from the decoder in Figure 847.
Glitch widths are exaggerated for illustration and are usually only
a few nanoseconds wide. Thomas L. Floyd Digital Fundamentals, 9e
Copyright 2006 by Pearson Education, Inc. Upper Saddle River, New
Jersey 07458 All rights reserved. Slide 49 Figure 849 The basic
decade counter and decoder with strobing to eliminate glitches.
Thomas L. Floyd Digital Fundamentals, 9e Copyright 2006 by Pearson
Education, Inc. Upper Saddle River, New Jersey 07458 All rights
reserved. Slide 50 Figure 850 Strobed decoder outputs for the
circuit of Figure 849. Thomas L. Floyd Digital Fundamentals, 9e
Copyright 2006 by Pearson Education, Inc. Upper Saddle River, New
Jersey 07458 All rights reserved. Slide 51 Figure 851 Simplified
logic diagram for a 12-hour digital clock. Logic details using
specific devices are shown in Figures 852 and 8 53. Thomas L. Floyd
Digital Fundamentals, 9e Copyright 2006 by Pearson Education, Inc.
Upper Saddle River, New Jersey 07458 All rights reserved. Slide 52
Figure 852 Logic diagram of typical divide-by-60 counter using
74F162 synchronous decade counters. Note that the outputs are in
binary order (the right-most bit is the LSB). Thomas L. Floyd
Digital Fundamentals, 9e Copyright 2006 by Pearson Education, Inc.
Upper Saddle River, New Jersey 07458 All rights reserved. Slide 53
Figure 853 Logic diagram for hours counter and decoders. Note that
on the counter inputs and outputs, the right-most bit is the LSB.
Thomas L. Floyd Digital Fundamentals, 9e Copyright 2006 by Pearson
Education, Inc. Upper Saddle River, New Jersey 07458 All rights
reserved. Slide 54 Figure 854 Functional block diagram for parking
garage control. Thomas L. Floyd Digital Fundamentals, 9e Copyright
2006 by Pearson Education, Inc. Upper Saddle River, New Jersey
07458 All rights reserved. Slide 55 Figure 855 Logic diagram for
modulus-100 up/down counter for automobile parking control. Thomas
L. Floyd Digital Fundamentals, 9e Copyright 2006 by Pearson
Education, Inc. Upper Saddle River, New Jersey 07458 All rights
reserved. Slide 56 Figure 856 Parallel-to-serial data conversion
logic. Thomas L. Floyd Digital Fundamentals, 9e Copyright 2006 by
Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All
rights reserved. Slide 57 Figure 857 Example of parallel-to-serial
conversion timing for the circuit in Figure 856. Thomas L. Floyd
Digital Fundamentals, 9e Copyright 2006 by Pearson Education, Inc.
Upper Saddle River, New Jersey 07458 All rights reserved. Slide 58
Figure 858 The 74HC163 4-bit synchronous counter. Thomas L. Floyd
Digital Fundamentals, 9e Copyright 2006 by Pearson Education, Inc.
Upper Saddle River, New Jersey 07458 All rights reserved. Slide 59
Figure 859 Example of a failure that affects following counters in
a cascaded arrangement. Thomas L. Floyd Digital Fundamentals, 9e
Copyright 2006 by Pearson Education, Inc. Upper Saddle River, New
Jersey 07458 All rights reserved. Slide 60 Figure 860 Example of a
failure in a cascaded counter with a truncated sequence. Thomas L.
Floyd Digital Fundamentals, 9e Copyright 2006 by Pearson Education,
Inc. Upper Saddle River, New Jersey 07458 All rights reserved.
Slide 61 Figure 861 Thomas L. Floyd Digital Fundamentals, 9e
Copyright 2006 by Pearson Education, Inc. Upper Saddle River, New
Jersey 07458 All rights reserved. Slide 62 Figure 862 Thomas L.
Floyd Digital Fundamentals, 9e Copyright 2006 by Pearson Education,
Inc. Upper Saddle River, New Jersey 07458 All rights reserved.
Slide 63 Figure 863 Traffic light control system block diagram.
Thomas L. Floyd Digital Fundamentals, 9e Copyright 2006 by Pearson
Education, Inc. Upper Saddle River, New Jersey 07458 All rights
reserved. Slide 64 Figure 864 Sequence of traffic light states.
Thomas L. Floyd Digital Fundamentals, 9e Copyright 2006 by Pearson
Education, Inc. Upper Saddle River, New Jersey 07458 All rights
reserved. Slide 65 Figure 865 Block diagram of the sequential
logic. Thomas L. Floyd Digital Fundamentals, 9e Copyright 2006 by
Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All
rights reserved. Slide 66 Figure 866 State diagram for the traffic
light control system. Thomas L. Floyd Digital Fundamentals, 9e
Copyright 2006 by Pearson Education, Inc. Upper Saddle River, New
Jersey 07458 All rights reserved. Slide 67 Figure 867 Sequential
logic diagram. Thomas L. Floyd Digital Fundamentals, 9e Copyright
2006 by Pearson Education, Inc. Upper Saddle River, New Jersey
07458 All rights reserved. Slide 68 Figure 868 Input logic for the
2-bit Gray code counter. Thomas L. Floyd Digital Fundamentals, 9e
Copyright 2006 by Pearson Education, Inc. Upper Saddle River, New
Jersey 07458 All rights reserved. Slide 69 Figure 869 The
sequential logic. Thomas L. Floyd Digital Fundamentals, 9e
Copyright 2006 by Pearson Education, Inc. Upper Saddle River, New
Jersey 07458 All rights reserved. Slide 70 Figure 870 Block diagram
of the complete traffic light control system. Thomas L. Floyd
Digital Fundamentals, 9e Copyright 2006 by Pearson Education, Inc.
Upper Saddle River, New Jersey 07458 All rights reserved. Slide 71
Figure 871 Comparison of asynchronous and synchronous counters.
Thomas L. Floyd Digital Fundamentals, 9e Copyright 2006 by Pearson
Education, Inc. Upper Saddle River, New Jersey 07458 All rights
reserved. Slide 72 Figure 872 Note that the labels (names of inputs
and outputs) are consistent with text but may differ from the
particular manufacturers data book you are using. The devices shown
are functionally the same and pin compatible with the same device
types in other available CMOS and TTL IC families. Thomas L. Floyd
Digital Fundamentals, 9e Copyright 2006 by Pearson Education, Inc.
Upper Saddle River, New Jersey 07458 All rights reserved. Slide 73
Figure 873 Thomas L. Floyd Digital Fundamentals, 9e Copyright 2006
by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All
rights reserved. Slide 74 Figure 874 Thomas L. Floyd Digital
Fundamentals, 9e Copyright 2006 by Pearson Education, Inc. Upper
Saddle River, New Jersey 07458 All rights reserved. Slide 75 Figure
875 Thomas L. Floyd Digital Fundamentals, 9e Copyright 2006 by
Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All
rights reserved. Slide 76 Figure 876 Thomas L. Floyd Digital
Fundamentals, 9e Copyright 2006 by Pearson Education, Inc. Upper
Saddle River, New Jersey 07458 All rights reserved. Slide 77 Figure
877 Thomas L. Floyd Digital Fundamentals, 9e Copyright 2006 by
Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All
rights reserved. Slide 78 Figure 878 Thomas L. Floyd Digital
Fundamentals, 9e Copyright 2006 by Pearson Education, Inc. Upper
Saddle River, New Jersey 07458 All rights reserved. Slide 79 Figure
879 Thomas L. Floyd Digital Fundamentals, 9e Copyright 2006 by
Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All
rights reserved. Slide 80 Figure 880 Thomas L. Floyd Digital
Fundamentals, 9e Copyright 2006 by Pearson Education, Inc. Upper
Saddle River, New Jersey 07458 All rights reserved. Slide 81 Figure
881 Thomas L. Floyd Digital Fundamentals, 9e Copyright 2006 by
Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All
rights reserved. Slide 82 Figure 882 Thomas L. Floyd Digital
Fundamentals, 9e Copyright 2006 by Pearson Education, Inc. Upper
Saddle River, New Jersey 07458 All rights reserved. Slide 83 Figure
883 Thomas L. Floyd Digital Fundamentals, 9e Copyright 2006 by
Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All
rights reserved. Slide 84 Figure 884 Thomas L. Floyd Digital
Fundamentals, 9e Copyright 2006 by Pearson Education, Inc. Upper
Saddle River, New Jersey 07458 All rights reserved. Slide 85 Figure
885 Thomas L. Floyd Digital Fundamentals, 9e Copyright 2006 by
Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All
rights reserved. Slide 86 Figure 886 Thomas L. Floyd Digital
Fundamentals, 9e Copyright 2006 by Pearson Education, Inc. Upper
Saddle River, New Jersey 07458 All rights reserved. Slide 87 Figure
887 Thomas L. Floyd Digital Fundamentals, 9e Copyright 2006 by
Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All
rights reserved. Slide 88 Figure 888 Thomas L. Floyd Digital
Fundamentals, 9e Copyright 2006 by Pearson Education, Inc. Upper
Saddle River, New Jersey 07458 All rights reserved. Slide 89 Figure
889 Thomas L. Floyd Digital Fundamentals, 9e Copyright 2006 by
Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All
rights reserved. Slide 90 Figure 890 Thomas L. Floyd Digital
Fundamentals, 9e Copyright 2006 by Pearson Education, Inc. Upper
Saddle River, New Jersey 07458 All rights reserved. Slide 91 Figure
891 Thomas L. Floyd Digital Fundamentals, 9e Copyright 2006 by
Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All
rights reserved. Slide 92 Figure 892 Thomas L. Floyd Digital
Fundamentals, 9e Copyright 2006 by Pearson Education, Inc. Upper
Saddle River, New Jersey 07458 All rights reserved. Slide 93 Figure
893 Thomas L. Floyd Digital Fundamentals, 9e Copyright 2006 by
Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All
rights reserved. Slide 94 Figure 894 Thomas L. Floyd Digital
Fundamentals, 9e Copyright 2006 by Pearson Education, Inc. Upper
Saddle River, New Jersey 07458 All rights reserved.
