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fifo_rtl.v
By udimudi 2015‐01‐10 View s 1 Download s 2 Point s 2 Rate
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From rouiter design using verilogDescription design router using
verilog.design a 1x3 router using verilog.
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`define FIFO_DEPTH 16`define fifo_width 8`define ptr_size
8module fifo_rtl(clk,
reset_n,data_in,wr_en,rd_en,empty,full,data_out );
input [(`fifo_width‐1):0]data_in;input clk,
reset_n,wr_en,rd_en;reg [(`ptr_size‐1):0]wr_ptr;reg
[(`ptr_size‐1):0]rd_ptr;reg [(`ptr_size‐1):0]fifo_status; output
full, empty;output [`fifo _width‐1:0] data_out; wire full,
empty;reg [`fifo_width‐ 1:0] da ta_out; reg [`fifo_width‐1:0]
mem [0:`FIFO_DEPTH‐1];
always@(posedge clk or negedge reset_n) begin if (~reset_n)
begin data_out
8/16/2019 Fifo_rtl.v - Free Open Source Codes - CodeForge
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ff_sync.v
router_reg.v
fsm_router.v
router_1x3.vfifo_rtl.v
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