8/16/2019 Ff_sync.v - Free Open Source Codes - CodeForge
1/3
Login Sign up | FavoriteSource Codes Point Help
LanguageUpload
Home » Source Code » rouiter design using
verilog » ff_sync.v
By udimudi 2015‐01‐10 View s ：1
Download s ：2 Point s ： 2
Rate：0.0
ff_sync.v File view
From： rouiter design using verilog
Description：design router using verilog.design a 1x3 router
using verilog.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
2829
30
31
32
33
34
35
36
37
38
39
40
41
42
4344
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
/************************************************************************
MAVEN SILICON CONFIDENTIAL ‐ This is an unpublished,
proprietary work
of Maven Silicon Softech Pvt. Ltd., Bangalore, and is fully
protected
under copyright and trade secret laws. You may not view, use,
disclose,
copy, or distribute this file or any information contained
herein except
pursuant to a valid written license from Maven Silicon
Softech Pvt. Ltd.,
Bangalore
Design Name : router_1x3
Module Name : ff_sync
Date : 04/10/2009
Description : This module provides synchronization
between
fsm and fifo for data communication
Author : P R SIVAKUMAR
Email : [email protected]
Company : Maven Silicon, Bangalore
www.vlsitraining.com
Version : 1.0 revision 0.0
*************************************************************************/
module ff_sync ( clock,
resetn,
detect_add,
data,
empty_0,
empty_1,
empty_2,
full_0,
full_1,
full_2, write_enb_reg,
write_enb,
fifo_empty,
fifo_full,
vld_out_0,
vld_out_1,
vld_out_2
);
//Port Direction
input clock;
input resetn;
input detect_add;
input [1:0] data;
input write_enb_reg; input empty_0;
input empty_1;
input empty_2;
input full_0;
input full_1;
input full_2;
output [2:0] write_enb;
output fifo_empty;
output fifo_full;
output vld_out_0;
output vld_out_1;
output vld_out_2;
//Port type declaration
wire clock;
wire resetn;
wire detect_add;
wire [1:0] data;
wire write_enb_reg;
wire empty_0;
wire empty_1;
http://www.codeforge.com/http://www.codeforge.com/http://www.codeforge.com/http://www.codeforge.com/pointhttp://www.codeforge.com/help/cfhttp://www.codeforge.com/http://www.codeforge.com/pointhttp://www.codeforge.com/help/cfhttp://www.codeforge.com/article/248808#introductionhttp://www.codeforge.com/article/248808http://www.codeforge.com/article/248808http://www.codeforge.com/codelisthttp://www.codeforge.com/http://www.codeforge.com/help/cfhttp://www.codeforge.com/pointhttp://www.codeforge.com/http://www.codeforge.com/http://www.codeforge.com/user/registration/registerhttp://void%280%29/
8/16/2019 Ff_sync.v - Free Open Source Codes - CodeForge
2/3
66
67
68
69
70
71
72
73
74
75
76
77
7879
80
81
82
83
84
85
86
87
88
89
90
91
92
9394
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124125
126
127
128
129
130
131
132
133
134
135
136
137
138
139140
141
142
143
144
145
wire empty_2;
wire full_0;
wire full_1;
wire full_2;
reg fifo_empty;
reg fifo_full;
wire vld_out_0;
wire vld_out_1;
wire vld_out_2;
reg [1:0] addr;
reg [2:0] write_enb_sel;
// This block will detect the address of channel and will latch
it till
// packet_valid is asserted, address and write_enb_sel
will be used for
// latching the incoming data into the fifo of that channel.
always@(posedge clock)
begin
if (resetn==1'b0)
begin
write_enb_sel = 3'b000;
addr = 2'b11;
end
else if (detect_add)
begin
case (data)
2'b00 : begin write_enb_sel = 3'b001;
addr = 2'b00;
end
2'b01 : begin
write_enb_sel = 3'b010;
addr = 2'b01;
end
2'b10 : begin
write_enb_sel = 3'b100;
addr = 2'b10;
end
default : begin
write_enb_sel = 3'b000;
addr = 2'b11;
end
endcase
end
end
//write enable generation for fifo
assign write_enb[0] = ((write_enb_sel[0]) &&
(write_enb_reg));
assign write_enb[1] = ((write_enb_sel[1]) &&
(write_enb_reg));
assign write_enb[2] = ((write_enb_sel[2]) &&
(write_enb_reg));
//output data will be valid at channels when vld_out will be
high
assign vld_out_0 = ~empty_0;
assign vld_out_1 = ~empty_1;
assign vld_out_2 = ~empty_2;
// fifo_empty and fifo_full are generated from the
// full and empty of the fifo, selected by address bits
always@(addr,empty_0,empty_1,empty_2,full_0,full_1,full_2)
begin
case (addr)
2'b00 : begin
fifo_empty=empty_0;
fifo_full =full_0;
end
2'b01 : begin
fifo_empty=empty_1;
fifo_full =full_1;
end
2'b10 : begin
fifo_empty=empty_2;
fifo_full =full_2;
end
default : begin fifo_empty=1'b0;
fifo_full =1'b1;
end
endcase
end
