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スーパーコネクト（基調講演）スーパーコネクト（基調講演）スーパーコネクト（基調講演）スーパーコネクト（基調講演）

東京大学、国際・産学共同研究センター東京大学、国際・産学共同研究センター東京大学、国際・産学共同研究センター東京大学、国際・産学共同研究センター生産技術研究所生産技術研究所生産技術研究所生産技術研究所桜井貴康桜井貴康桜井貴康桜井貴康

E-mail:tsakurai@iis.u-tokyo.ac.jp

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実装プロセス工学シンポジウム実装プロセス工学シンポジウム実装プロセス工学シンポジウム実装プロセス工学シンポジウム「スーパーコネクトに対応した層間接続プロセス」　「スーパーコネクトに対応した層間接続プロセス」　「スーパーコネクトに対応した層間接続プロセス」　「スーパーコネクトに対応した層間接続プロセス」　2001年年年年5月月月月18日日日日

T.Sakurai

Technology trend

Des

ign

rule

, gat

e le

ngth

Gat

e ox

ide

thic

knes

s [n

m]

Year1998 2002 2006 2010 2014

Design rule

Gate length

Gate oxide thickness

DRAM bit per chip

0.1

1

10

100

1000

DR

AM

bit

per c

hip

[Gbi

t]1000

100

10

1

International Technology Roadmap for Semiconductors 1999 update sponsored by the Semiconductor Industry Association in cooperation with European Electronic Component Association (EECA) , Electronic Industries Association of Japan (EIAJ), Korea Semiconductor Industry Association (KSIA), and Taiwan Semiconductor Industry Association (TSIA)

T.Sakurai

Scaling Law

T.Sakurai&A.Newton,"Alpha-power law MOSFET model and its application to CMOS inverter delay and other formulas",IEEE JSSC,vol25, no,2, pp.584-594, Apr. 1990.

k=2k=2k=2k=2

( ) [ ]3112

.// VxxxVVLW

tI THGS

OXDS ≈−µε= α

VDD [V] 1/kTr. dimensions [x] 1/kTr. current [I~1/x x/x V^1.3] 1/k0.3

Tr. capacitance [C~1/x xx] 1/kTr. delay [d~CV/I] 1/k1.7

Tr. power [P~VI~CVV/d] 1/k1.3

Power density [p~P/x/x] k0.7

Tr. density [n~1/x/x] k2

Local GlobalScaled Anti-scaled

Line thickness [T] 1/k kWidth [W] 1/k kSeparation [S] 1/k kOxide thickness [H] 1/k 1Length [L] 1/k 1Resistance [Rint~L/W/T] k 1/k2

Capacitance [Cint~LW/H] 1/k kRC delay/Tr. delay [D~RintCint/d] k1.7 −−−−Current density [J~pWL/V /W/T] −−−− k0.7

DC noise / Vdd [N~JWTR/V] −−−− k1.7

Scaling scenario

Transistors

Interconnections

Scaling coefficients

Type

T.Sakurai

Scaling Law

Drain Source

Gate

0.2micron

Drain SourceGate

0.2micronSize 1/2

Size x1/2Voltage x1/2Electric Field x1Speed x3Cost x1/4

Power density x1.6RC delay/Tr. delay x3.2Current density x1.6Voltage noise x3.2Design complexity x4

Favorable effects Unfavorable effects

T.Sakurai

Three crises in VLSI designs

Power crisis

Interconnection crisis

Complexity crisis

T.Sakurai

System on a Chip (SoC)

MPU Core

Cache

ROMLogic

AnalogUSB Core

DRAM

IP (A inc.)IP (B univ.)IP (C inst.)IP (D semi.)

IP ; CPU, DSP, memories, analog, I/O, logic..HW/FW/SW

• Re-use and sharing of design• Design in higher abstraction

T.Sakurai

System LSI for Games

●●●● Clock freq. 300MHz

●　●　●　●　10M transistors

●　●　●　●　Graphics synthesizer integrate

40M tr. With embedded DRAM

●●●● Memory bandwidth 3.2GB/s

●●●● Floating operation 6.2GFLOPS/sec

●●●● 3D CG 6.6M polygon/sec

●●●● MPEG2 decode

T.Sakurai

Issues in System-on-Chip

• Un-distributed IP’s (i.e. CPU, DSP of a certain company)

• Low yield due to larger die size

• Huge initial investment for masks & development

• IP testability, upfront IP test cost

• Process-dependent memory IP’s

• Difficulty in high precision analog IP’s due to noise

• Process incompatibility with non-Si materials and/or

MEMS

T.Sakurai

Chip area (A) [mm2]

Y ∝∝∝∝ exp(-D*A)

0 50 1000

0.5

1

Yield

Yiel

d

T.Sakurai

Technologies integrated on a chip

‘98

LogicSRAM

Flash memoryEmbedded DRAM

CMOS RFFPGAMEMS

FeRAMChemical sensors

Electro-opticalElectro-biological

Year‘00 ‘02 ‘04 ‘06 ‘08 ‘10 ‘12

+0+1~2+4+4~5+3~5+2+2~10+4~5+2~6+5~8+?

ITRS’99RF : Radio FrequencyFPGA : Field Programmable Gate ArrayMEMS : Micro Electro Mechanical SystemsFeRAM : Ferroelectric RAM

T.Sakurai

DRAM embedding

DRAM Processor System LSI

Two orders of magnitude improvement in bandwidth and power

K.Sawada, T.Sakurai, et al, "A 72K CMOS Channelless Gate Array with Embedded 1Mbit Dynamic RAM," in Proc. CICC'88, pp.20.3.1-20.3.4, May 1988.

BUT EXPENSIVE!

T.Sakurai

Micro-machined mechanical switch

G.Weinberger, “The New Millennium: Wireless Technologies for a Truly Mobile Society,” ISSCC, pp.20-24, Feb. 2000.

T.Sakurai

Silicon MEMS microphone

M.Pinto, “Atoms to Applets: Building Systems ICs in the 21st Century,” ISSCC, pp.26-30, Feb. 2000.

10umWill soon exceed the performance of the best commercial microphones, yet be inexpensive and potentially integrated with on-chip electronics.

T.Sakurai

System-in-Package

T.Sakurai

System on a Chip

SoC vs. SiP

Chip

MPU Core

Cache

ROMLogic

AnalogUSB Core

DRAM• Smaller area• Shorter interconnect• Optimized process for

each die (Analog, DRAM, MEMS…)

• Good electrical isolation• Through-chip via

• Heat dissipation is an issue

Heat spreader/Heat pipe

System in a PackageMPU Core

DRAM

Logic

AnalogCache

USB ROM

T.Sakurai

System-in-Package (SIP)

Chip

Substrate

SolderResistor Capacitor Inductor

Two-layer Al TaSi SiO2 Si3N4 Polyimide

K.L.Tai, “System-In-Package (SIP): Challenges and Opportunities,” ASPDAC, pp.191-196, Jan. 2000

T.Sakurai

System-in-Packageの課題の課題の課題の課題

• Special design tools for placement & route for co-

design of LSI’s and assembly

• High-density reliable substrate and metallization

technology

• low-cost, available known good die

(reworkablility and module testing)

T.Sakurai

Superconnect example based on three-dimensional assembly

PURE LOGIC

Heat Sink

ANALOG

RF/ANALOG

DRAM

K.Ohsawa, H.Odaira, M.Ohsawa, S.Hirade, T.Iijima, S.G.Pierce, “3-D Assembly Interposer Technology for Next-Generation Integrated Systems,” ISSCC Digest of Tech. Papers, pp.272-273, Feb.2001.

T.Sakurai

Super-connect technologyD

esig

n ru

le (µ

m)

0.01

0.1

1

10

100

Past Present Future

Tr. gate

Tr. gate

Tr. gate

InterconnectUpper layerLower layer

Upper layer

Middle layer

Lower layer

Super-connect

PackagePackagePackage

Technology Vacuum

M. Kimura,"Superconnect : 21st Century LSI Production and Design Method", Nikkei Microdevices, no.180, pp.62-79, June 2000.

T.Sakurai

Super-connect

Bandwidth

0.1

1

10

100

Design rule Power@1GB/s

Area

102

103

104

105

[mm] [mW] [GB/sec]

[mm2

/bit]

Super-connect

Off-chip On-chip

1

10

100

1000

Cost/line

[AU]

10

1000[day]

100

Turn-aroundtime

1

10

100

1000

1

10

100

1000

T.Sakurai

Three crises in VLSI designs

Power crisis

Interconnection crisis

Complexity crisis

T.Sakurai

DSM interconnect design issues

Larger currentIR drop (static and dynamic)Reliability (electro-migration)

Smaller geometry / Denser patternRC delaySignal IntegrityCrosstalk noiseDelay fluctuation

Higher speedInductanceEMI

T.Sakurai

Interconnect determines cost & perf.

0

20

40

60

80

100

Pow

er [%

]

MOSFET

2000 ‘05 ‘10 ‘15

Num

ber o

f int

erco

nnec

t la

yers

Year

(ITRS’99)

0

20

40

60

80

100

Del

ay [%

]

1mm Cu

0

20

40

60

80

100

Proc

ess

step

s [%

]# of layers

RC delayw/o buffers

Interconnect

MOSFETGatedelay

2000 ‘05 ‘10 ‘15Year

2000 ‘05 ‘10 ‘15Year

2000 ‘05 ‘10 ‘15Year

11

10

9

8

7

6

Interconnect

T.Sakurai

VDD, power and current trend

Year

Volta

ge [V

]

Pow

er p

er c

hip

[W]

V DD

curr

ent [

A]

1998 2002 2006 2010 20140

0.5

1

1.5

2

2.5

0 0

200 500

Current

Power

Voltage

International Technology Roadmap for Semiconductors 1999 update sponsored by the Semiconductor Industry Association in cooperation with European Electronic Component Association (EECA) , Electronic Industries Association of Japan (EIAJ), Korea Semiconductor Industry Association (KSIA), and Taiwan Semiconductor Industry Association (TSIA)

T.Sakurai

IR Drop

Vi,j

Vi-1,j

Vi+1,j

Vi,j-1 Vi,j+1

Ii,j

Vi,j=(Vi-1,j +Vi+1,j +Vi,j-1 +Vi,j+1)/4-r Ii,j

rrr

r

ΣΣΣΣIi,j=I, Sheet resistance=RTake IR as unity voltage drop

T.Sakurai

Interconnect Cross-Section and Noise

Unscaled / anti-scaled• Clock• Long bus• Power supply

Scaled interconnect• Signal

1V 20W -> 20A current5% noise →→→→0.05V noise →→→→~0.02V / 20A→→→→~10µm thick CuThick layer interconnect, area pad, package are co-designed.

T.Sakurai

Interconnect parameters trend

0

1

2

3

4

1996 2000 2004 2008 2012Year

εεεε r

ρρρρ[ΩΩΩΩ • cm]

Aspect ratio

Width [x0.1μμμμm]

Al Cu

Semiconductor Industry Association roadmaphttp://notes.sematech.org/1997pub.htm

T.Sakurai

RC delay and gate delay

1996 2000 2004 2008 201210-12

10-11

10-10

10-9

10-8

Year

Clock period

Gate delay

3mm

1mm

100µm

50µm

Del

ay (s

ec)

T.Sakurai

Repeaters

a) Without repeaters b) With repeaters

RINTCINT

( )INTINTOPTOPT

MOSINTINTINTOPT

INTINTOPT

INT

INTOPT

INTINTINTINT

TINTINTTTTINTINT

CCppChkgatesofCap

CRCRpppDelay

stagesofnumberOptimizedCRCR

ppk

kDelay

inverterbufferofsizeOptimizedCRRCh

hDelay

BufferedhCk

Rk

Ch

RhCh

Rpk

Ck

RpkDelay

MOSFETminimumofresistanceeffectiveGateRMOSFETminimumofecapacitancGateC

CRCRCRCRt

73.0/.

4.22

:0

:0

:

::

)(693.0377.0

210

00221

002

1

0

0

00

00

21

0

0

05

===

ττ≈+=

=→=∂

∂

=→=∂

∂

+++≈

+++≈

RT

CT

T.Sakurai

Buffered interconnect delay

1998 2002 2006 2010 201410-11

10-10

10-9

10-8

Gate delay

1µµµµm x 1µµµµm chip long

Clock period (global)

Clock period (local)

1µµµµm x 1µµµµm chip long buffered

Year

Del

ay (s

ec)

T.Sakurai

Power delay optimization

1 1.2 1.4 1.6 1.8 2 2.2 2.4 2.6 2.8 30.20.40.60.81

1.21.41.61.8

Del

ay/D

elay

OPT

, h/h

OPT

, k/k

OPT

Total capacitance / CINT

a) Without repeaters b) With repeaters

RINTCINTRT

CT

CJ

Delay: total delay

h: size of buffer

k: # of stages

T.Sakurai

RC delay of global interconnections

10-10

10-9

10-8

10-7

10-6

Year

Del

ay (s

ec)

6µm x 2µm cross-section interconnectGlobal interconnect

Chip18mm x 18mm

30mm x 30mm

1998

Clock period

Minimum cross-section interconnect

2002 2006 2010 2014

T.Sakurai

Ever Increasing VLSI Power(Power consumption of processors published in ISSCC)

959085800.01

0.1

1

10

100

Year

Pow

er (W

)x4 / 3years

T.Sakurai

0.5V LSIでの逆温度特性での逆温度特性での逆温度特性での逆温度特性

Photograph of 32bit FA0.3µµµµm CMOS

0000 0.50.50.50.5 1111 1.51.51.51.5 22220000

1111

2222

3333

4444

Norm

aliz

ed

Norm

aliz

ed

Norm

aliz

ed

Norm

aliz

ed t ttt

pd

pdpd

pd

VDD [V]

90ºC

50ºC

20ºC Measured

K.Kanda, K.Nose, H.Kawaguchi, and T.Sakurai,"Design Impact of Positive Temperature Dependence of Drain Current in Sub 1V CMOS VLSI's",CICC99, pp.563-566, May 1999.

T.Sakurai

LSI in 2014Year Unit 1999 2014 Factor

Design rule µm 0.18 0.035 0.2Tr. Density /cm2 6.2M 390M 30Chip size mm2 340 900 2.6Tr. Count per chip (µP) 21M 3.6G 170DRAM capacity 1G 1T 1000Local clock on a chip Hz 1.2G 17G 14Global clock on a chip Hz 1.2G 3.7G 3.1Power W 90 183 2.0Supply voltage V 1.5 0.37 0.2Current A 60 494.6 8Interconnection levels 6 10 1.7Mask count 22 28 1.3Cost / tr. (packaged) µcents 1735 22 0.01Chip to board clock Hz 500M 1.5G 3.0# of package pins 810 2700 3.3Package cost cents/pin 1.61 0.75 0.5

International Technology Roadmap for Semiconductors 1998 update sponsored by the Semiconductor Industry Association in cooperation with European Electronic Component Association (EECA) , Electronic Industries Association of Japan (EIAJ), Korea Semiconductor Industry Association (KSIA), and Taiwan Semiconductor Industry Association (TSIA) , International Technology Roadmap for Semiconductors: 1999 edition. Austin, TX:International SEMATECH, 1999.

T.Sakurai

Trend in packages

ITRS’99

2000 2004 2008 20140

1000

2000

3000

4000

5000

6000

7000

8000

9000

High performance

chip

Handheld

020406080

100

120140160180200

2000 2004 2008 2014

Pin countFlip-chip interconnect

pitch [µµµµm]

T.Sakurai

Possible electronic system in 2014

• Sensors/actutors

• 0.035µm 3.6G Si FET’s with VTH & VDD control

• Locally synchronous 17GHz clock, globally asynchronous

• Chip / Package / Board system co-design for power lines, clocks, and long wires (super-connect)

MPU, LogicConfigurable units

Variousmemories

Micro-actuatorsAnalog

Sensors

T.Sakurai

水平分業と垂直統合水平分業と垂直統合水平分業と垂直統合水平分業と垂直統合

ＬＳＩ設計ＬＳＩ設計ＬＳＩ設計ＬＳＩ設計

ＬＳＩ製造ＬＳＩ製造ＬＳＩ製造ＬＳＩ製造

実装部分設計実装部分設計実装部分設計実装部分設計製造製造製造製造

システム設計システム設計システム設計システム設計 US

アジア等アジア等アジア等アジア等

US

台湾等台湾等台湾等台湾等

ＬＳＩ設計ＬＳＩ設計ＬＳＩ設計ＬＳＩ設計

ＬＳＩ製造ＬＳＩ製造ＬＳＩ製造ＬＳＩ製造

実装部分設計実装部分設計実装部分設計実装部分設計製造製造製造製造

システム設計システム設計システム設計システム設計

同同同同一一一一地地地地域域域域でででで

メモリメモリメモリメモリアナログアナログアナログアナログ

CPU

ASIC、、、、デジタル、デジタル、デジタル、デジタル、SoC SoC

SiP

T.Sakurai

Assembly & Packaging

“There is an increased awareness in the industry that assembly and packaging is becoming a differentiator in product development.”

International Technology Roadmap for Semiconductors, ITRS’99 p.213

T.Sakurai

Retinal Prosthesis

Prosthesis Prosthesis -- DualDual IntraocularIntraocular UnitsUnits

Courtesy: Prof. Wentai Liu (North Carolina Univ.)http://www.ece.ncsu.edu/erl/faculty/wtl_data/retina.html

T.Sakurai

System on a chip

Stacked chips

Stacked chips

MPU Core

•

DRAMAnalog

MPU Core

Cache

ROMLogic

AnalogUSB Core

DRAM

藤田他、「スタックド藤田他、「スタックド藤田他、「スタックド藤田他、「スタックドCSPCSPCSPCSP技術」、シャープ技法、技術」、シャープ技法、技術」、シャープ技法、技術」、シャープ技法、1998.81998.81998.81998.8

• Smaller area• Shorter interconnect• Optimized process for

each die (Analog, DRAM, MEMS…)

• Good electrical isolation

• Heat dissipation is an issue

T.Sakurai

Shorter interconnect in 3-D assembly

System on a chip

3-D assembly

( )dinchipsstackedof

dh

hd

DdindevicesofDdindevicesof

#

)(#)(#

32

231

23

≈

+=

d: Manhattan distance

h: Height between chips

T.Sakurai

Three crises in VLSI designs

Power crisis

Interconnection crisis

Complexity crisis