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hsabaghianb @ kashanu.ac.ir Microprocessors 1-1

The 8051

Microcontroller

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8051 Basic Component

4K bytes internal ROM128 bytes internal RAM

Four 8-bit I/Oports (P0 - P3).

Two 16-bit timers/counters

One serial interface

RAM

I/O

PortTimer

SerialCOMPort

Microcontroller

CPUA single chip

ROM

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Block Diagram

CPU

Interrupt

Control

OSC BusControl

4k

ROM

Timer 1

Timer 2

Serial

128 bytes

RAM

4 I/O Ports

TXD RXD

External Interrupts

P0 P2 P1 P3

Addr/Data

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Other 8051 featurs

only 1 On chip oscillator (external crystal) 6 interrupt sources (2 external , 3 internal, Reset)

64K external code (program) memory(only read)PSEN

64K external data memory(can be read and write) by

RD,WR

Code memory is selectable by EA (internal or external)

We may have External memory as data and code

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8051 Internal Block Diagram

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8051

SchematicPin out

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7/99hsabaghianb @ kashanu.ac.ir Microprocessors 1-7

8051

Foot Print

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40

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P1.0

P1.1

P1.2

P1.3

P1.4

P1.5

P1.6

P1.7

RST

(RXD)P3.0

(TXD)P3.1

(T0)P3.4

(T1)P3.5

XTAL2

XTAL1

GND

(INT0)P3.2

(INT1)P3.3

(RD)P3.7

(WR)P3.6

Vcc

P0.0(AD0)

P0.1(AD1)

P0.2(AD2)

P0.3(AD3)

P0.4(AD4)

P0.5(AD5)

P0.6(AD6)

P0.7(AD7)

EA/VPP

ALE/PROG

PSEN

P2.7(A15)

P2.6(A14)

P2.5(A13)

P2.4(A12)

P2.3(A11)

P2.2(A10)

P2.1(A9)

P2.0(A8)

8051

(8031)(8751)

(8951)

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IMPORTANT PINS (IO Ports)

One of the most useful features of the 8051 is that itcontains four I/O ports (P0 - P3)

Port 0pins 32-39P0P0.0P0.7 8-bit R/W - General Purpose I/O Or acts as a multiplexed low byte address and data bus for external

memory design

Port 1pins 1-8 P1P1.0P1.7 Only 8-bit R/W - General Purpose I/O

Port 2pins 21-28P2P2.0P2.7 8-bit R/W - General Purpose I/O Orhigh byte of the address bus for external memory design

Port 3pins 10-17P3P3.0P3.7 General Purpose I/O if not using any of the internal peripherals (timers) or external

interrupts.

Each port can be used as input or output (bi-direction)

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Port 3 Alternate Functions

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8051 Port 3 Bit Latches and I/O Buffers

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Hardware Structure of I/O Pin

D Q

Clk Q

Vcc

Load(L1)

Read latch

Read pin

Write to latch

Internal CPU

bus

M1

P1.X

pinP1.X

TB1

TB2

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Hardware Structure of I/O Pin

Each pin of I/O portsInternally connected to CPU busA D latch store the value of this pinWrite to latch1write data into the D latch

2 Tri-state bufferTB1: controlled by Read pinRead pin1really read the data present at the

pinTB2: controlled by Read latchRead latch1read value from internal latch

A transistor M1 gateGate=0: openGate=1: close

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Writing 1 to Output Pin P1.X

D Q

Clk Q

Vcc

Load(L1)

Read latch

Read pin

Write to latch

Internal CPU

bus

M1

P1.X

pinP1.X

2. output pin is

Vcc1. write a 1 to the pin1

0 output 1

TB1

TB2

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Writing 0 to Output Pin P1.X

D Q

Clk Q

Vcc

Load(L1)

Read latch

Read pin

Write to latch

Internal CPU

bus

M1

P1.X

pinP1.X

2. output pin is

ground1. write a 0 to the pin0

1 output 0

TB1

TB2

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IMPORTANT PINS

PSEN (out): Program Store Enable, the readsignal for external program memory (active low).

ALE (out): Address Latch Enable, to latchaddress outputs at Port0 and Port2

EA (in): External Access Enable, active low toaccess external program memory locations 0 to 4K

RXD,TXD: UART pins for serial I/O on Port 3

XTAL1 & XTAL2: Crystal inputs for internaloscillator.

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Pins of 8051

Vccpin 40Vcc provides supply voltage to the chip.The voltage source is +5V.

GNDpin 20groundXTAL1 and XTAL2pins 19,18These 2 pins provide external clock.Way 1using a quartz crystal oscillatorWay 2using a TTL oscillatorExample 4-1 shows the relationship

between XTAL and the machine cycle.

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Pins of 8051

RSTpin 9reset

input pin and active highnormally low.

The high pulse must be high at least 2

machine cycles.power-on reset.

Upon applying a high pulse to RST, themicrocontroller will reset and all values in

registers will be lost.Reset values of some 8051 registers

power-on reset circuit

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Pins of 8051

/EApin 31external access

There is no on-chip ROM in 8031 and 8032 .

The /EA pin is connected to GND to indicate the code is

stored externally.

/PSEN ALE are used for external ROM.

For 8051, /EA pin is connected to Vcc.

/ means active low.

/PSENpin 29program store enable

This is an output pin and is connected to the OE pin of the

ROM.

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Pins of 8051

ALEpin 30address latch enable

It is an output pin and is active high.

8051 port 0 provides both address and data.

The ALE pin is used for de-multiplexing theaddress and data by connecting to the G pin of

the 74LS373 latch.

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Address Multiplexingfor External Memory

Figure 2-7

Multiplexingthe address(low-byte)and data

bus

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Address Multiplexingfor External Memory

Figure 2-8

Accessingexternal

codememory

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On-Chip MemoryInternal RAM

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Registers

0706050403020100

R7R6R5R4R3R2R1R0

0F

08

17

10

1F

18

Bank 3

Bank 2

Bank 1

Bank 0

Four Register BanksEach bank has R0-R7Selectable by psw.2,3

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Bit Addressable Memory20h2Fh (16 locations X

8-bits = 128 bits)

7F 78

1A

10

0F 08

07 06 05 04 03 02 01 00

27

26

25

24

23

22

21

20

2F

2E

2D

2C

2B

2A

29

28

Bit addressing:

mov C, 1Ah

ormov C, 23h.2

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Special Function Registers

DATA registers

CONTROL registers

TimersSerial portsInterrupt systemAnalog to Digital converter

Digital to Analog converterEtc.

Addresses 80h FFh

Direct Addressing usedto access SPRs

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Bit Addressable RAM

Figure 2-6Summary

of the 8051on-chip

data

memory

(RAM)

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Active bank selected by PSW [RS1,RS0] bit

Permits fast contextswitching in interrupt

service routines (ISR).

Register Banks

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8051 CPU Registers

A (Accumulator)BPSW (Program Status Word)SP (Stack Pointer)PC (Program Counter)DPTR (Data Pointer)

Used in assemblerinstructions

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Registers

A

B

R0

R1

R3

R4

R2

R5

R7

R6

DPH DPL

PC

DPTR

PC

Some 8051 16-bit Register

Some 8-bit Registers

of the 8051

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The 8051

Assembly Language

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Overview

Data transfer instructions

Addressing modes

Data processing (arithmetic and logic)

Program flow instructions

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Data Transfer Instructions

MOV dest, source dest sourceStack instructions

PUSH byte ;increment stack pointer,

;move byte on stack

POP byte ;move from stack to byte,;decrement stack pointer

Exchange instructionsXCH a, byte ;exchange accumulator and byte

XCHD a, byte ;exchange low nibbles of;accumulator and byte

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Addressing Modes

Immediate Mode specify data by its value

mov A, #0 ;put 0 in the accumulator

;A = 00000000

mov R4, #11h ;put 11hex in the R4 register

;R4 = 00010001

mov B, #11 ;put 11 decimal in b register

;B = 00001011

mov DPTR,#7521h ;put 7521 hex in DPTR

;DPTR = 0111010100100001

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Addressing Modes

Immediate Mode continue

MOV DPTR,#7521hMOV DPL,#21H

MOV DPH, #75

COUNT EGU 30~

~

mov R4, #COUNT

MOV DPTR,#MYDATA~

~

0RG 200H

MYDATA:DB IRAN

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Addressing Modes

Register Addressing either source ordestination is one of CPU register

MOV R0,A

MOV A,R7

ADD A,R4

ADD A,R7

MOV DPTR,#25F5H

MOV R5,DPL

MOV R,DPH

Note thatMOV R4,R7 is incorrect

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Addressing ModesDirect Mode specify data by its 8-bit address

Usually for 30h-7Fh of RAMMov a, 70h ; copy contents of RAM at 70h to a

Mov R0,40h ; copy contents of RAM at 70h to a

Mov 56h,a ; put contents of a at 56h to a

Mov 0D0h,a ; put contents of a into PSW

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Addressing Modes

Direct Mode play with R0-R7 by direct addressMOV A,4 MOV A,R4

MOV A,7 MOV A,R7

MOV 7,2 MOV R7,R6

MOV R2,#5 ;Put 5 in R2

MOV R2,5 ;Put content of RAM at 5 in R2

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Addressing Modes

Register Indirect the address of the source ordestination is specified in registers

Uses registers R0 or R1 for 8-bit address:mov psw, #0 ; use register bank 0

mov r0, #0x3C

mov @r0, #3 ; memory at 3C gets #3

; M[3C] 3

Uses DPTR register for 16-bit addresses:

mov dptr, #0x9000 ; dptr 9000hmovx a, @dptr ; a M[9000]

Note that 9000 is an address in external memory

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Addressing Modes

Register Indexed Mode source ordestination address is the sum of the baseaddress and the accumulator(Index)

Base address can be DPTR or PCmov dptr, #4000h

mov a, #5

movc a, @a + dptr ;a M[4005]

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Addressing Modes

Register Indexed Modecontinue

Base address can be DPTR or PC

ORG 1000h1000 mov a, #5

1002 movc a, @a + PC ;a M[1008]

1003 Nop

Table Lookup MOVC only can read internal code memory

PC

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Acc Register

A register can be accessed by direct and register mode

This 3 instruction has same function with different code0703 E500 mov a,00h

0705 8500E0 mov acc,00h

0708 8500E0 mov 0e0h,00h

Also this 3 instruction070B E9 mov a,r1

070C 89E0 mov acc,r1

070E 89E0 mov 0e0h,r1

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SFRs Address

B always direct mode - except in MUL & DIV0703 8500F0 movb,00h

0706 8500F0 mov 0f0h,00h

0709 8CF0 mov b,r4

070B 8CF0 mov 0f0h,r4

P0~P3 are direct address0704 F580 mov p0,a

0706 F580 mov 80h,a

0708 859080 mov p0,p1

Also other SFRs (pcon, tmod, psw,.)

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SFRs Address

All SFRs such as(ACC, B, PCON, TMOD, PSW, P0~P3, )

are accessible by name and directaddress

But

both of themMust be coded as direct address

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Stack

Stack-oriented data transferOnly one operand (direct addressing) SP is other operand register indirect - implied

Direct addressing mode must be used in Push and Pop

mov sp, #0x40 ; Initialize SP

push 0x55 ; SP SP+1, M[SP] M[55]

; M[41] M[55]

pop b ; b M[55]

Note: can only specify RAM or SFRs (direct mode) to push orpop. Therefore, to push/pop the accumulator, must use acc,not a

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Stack (push,pop)

ThereforePush a ;is invalid

Push r0 ;is invalid

Push r1 ;is invalidpush acc ;is correct

Push psw ;is correctPush b ;is correct

Push 13h

Push 0

Push 1

Pop 7Pop 8

Push 0e0h ;acc

Pop 0f0h ;b

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Exchange Instructions

two way data transferXCH a, 30h ; a M[30]

XCH a, R0 ; a R0

XCH a, @R0 ; a M[R0]XCHD a, R0 ; exchange digit

R0[7..4] R0[3..0]a[7..4] a[3..0]

Only 4 bits exchanged

d f

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Bit-Oriented Data Transfer

transfers between individual bits. Carry flag (C) (bit 7 in the PSW) is used as a single-

bit accumulator

RAM bits in addresses 20-2F are bit addressable

mov C, P0.0

mov C, 67h

mov C, 2ch.7

FR h B dd bl

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SFRs that are Bit Addressable

SFRs with addressesending in 0 or 8 arebit-addressable.(80, 88, 90, 98, etc)

Notice that all 4parallel I/O portsare bit addressable.

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Data Processing Instructions

Arithmetic Instructions

Logic Instructions

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Add

Subtract

Increment

DecrementMultiply

Divide

Decimal adjust

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Mnemonic Description

ADD A, byte add A to byte, put result in A

ADDC A, byte add with carry

SUBB A, byte subtract with borrow

INC A increment A

INC byte increment byte in memory

INC DPTR increment data pointer

DEC A decrement accumulator

DEC byte decrement byteMUL AB multiply accumulator by b register

DIV AB divide accumulator by b register

DA A decimal adjust the accumulator

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ADD Instructions

add a, byte ; a a + byteaddc a, byte ; a a + byte + C

These instructions affect 3 bits in PSW:

OV = 1 if result of add is greater than FF

AC = 1 if there is a carry out of bit 3

C = 1 if there is a carry out of bit 7, but not from bit 6, or visaversa.

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Instructions that Affect PSW bits

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ADD Examples

mov a, #3Fh

add a, #D3h

What is the value ofthe C, AC, OV flagsafter the secondinstruction is

executed?0011 11111101 0011

0001 0010

C = 1

AC = 1

OV = 0

i d ddi i d fl

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Signed Addition and Overflow

0111 1111 (positive 127)0111 0011 (positive 115)

1111 0010 (overflow

cannot represent 242 in 8

bits 2s complement)

2s complement:

0000 0000 00 0

0111 1111 7F 127

1000 0000 80 -128

1111 1111 FF -1

1000 1111 (negative 113)

1101 0011 (negative 45)

0110 0010 (overflow)

0011 1111 (positive)

1101 0011 (negative)

0001 0010 (never overflows)

Addi i E l

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Addition Example

; Computes Z = X + Y; Adds values at locations 78h and 79h and puts them in 7Ah;------------------------------------------------------------------X equ 78hY equ 79hZ equ 7Ah

;-----------------------------------------------------------------org 00hljmp Main

;-----------------------------------------------------------------org 100h

Main:

mov a, Xadd a, Ymov Z, aend

Th 16 bi ADD l

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The 16-bit ADD example; Computes Z = X + Y (X,Y,Z are 16 bit)

;------------------------------------------------------------------X equ 78hY equ 7AhZ equ 7Ch;-----------------------------------------------------------------

org 00h

ljmp Main;-----------------------------------------------------------------org 100h

Main:mov a, Xadd a, Y

mov Z, amov a, X+1adc a, Y+1mov Z+1, aend

S b

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Subtract

SUBB A, byte subtract with borrow

Example:

SUBB A, #0x4F ;A A 4F C

Notice thatThere is no subtraction WITHOUT borrow.Therefore, if a subtraction without borrow is desired,it is necessary to clear the C flag.

Example:

Clr c

SUBB A, #0x4F ;A A 4F

I d D

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Increment and Decrement

The increment and decrement instructions do NOTaffectthe C flag.

Notice we can only INCREMENT the data pointer, notdecrement.

INC A increment A

INC byte increment byte in memory

INC DPTR increment data pointer

DEC A decrement accumulator

DEC byte decrement byte

E l I 16 bi W d

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Example: Increment 16-bit Word

Assume 16-bit word in R3:R2

mov a, r2

add a, #1 ; use add rather than increment to affect C

mov r2, a

mov a, r3

addc a, #0 ; add C to most significant byte

mov r3, a

M l i l

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Multiply

When multiplying two 8-bit numbers, the size of themaximum product is 16-bits

FF x FF = FE01

(255 x 255 = 65025)

MUL AB ;BA A * B

Note : B gets the High byte

A gets the Low byte

Di i i

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Division

Integer Division

DIV AB ; divide A by B

A

Quotient(A/B)B Remainder(A/B)

OV - used to indicate a divide by zero condition.C set to zero

D i l Adj t

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Decimal Adjust

DA a ; decimal adjust a

Used to facilitate BCD addition.Adds 6 to either high or low nibble after an addition

to create a valid BCD number.

Example:mov a, #23h

mov b, #29h

add a, b ; a 23h + 29h = 4Ch (wanted 52)

DA a ; a a + 6 = 52

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Logic Instructions

Bitwise logic operations (AND, OR, XOR, NOT)

Clear Rotate

Swap

Logic instructions do NOTaffect the flags in PSW

Bit i L i

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Bitwise Logic

ANL AND

ORL OR

XRL XOR

CPL

Complement

Examples: 0000111110101100ANL

0000111110101100ORL

00001111

10101100XRL

10101100CPL

00001100

10101111

10100011

01010011

Address Modes with Logic

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Address Modes with Logic

a, byte

direct, reg. indirect, reg,

immediate

byte, a

direct

byte, #constant

a ex: cpl a

ANLAND

ORLOR

XRLeXclusive oR

CPLComplement

Uses of Logic Instructions

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Uses of Logic Instructions

Force individual bits low, without affecting other bits.anl PSW, #0xE7 ;PSW AND 11100111

Force individual bits high.orl PSW, #0x18 ;PSW OR 00011000

Complement individual bitsxrl P1, #0x40 ;P1 XRL 01000000

Other Logic Instructions

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Other Logic Instructions

CLR - clear

RL rotate left

RLC rotate left through Carry

RR rotate right

RRC rotate right through Carry

SWAP swap accumulator nibbles

CLR ( Set all bits to 0)

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CLR ( Set all bits to 0)

CLR ACLR byte (direct mode)

CLR Ri (register mode)

CLR @Ri (register indirect mode)

Rotate

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RotateRotate instructions operate only on a

RL a

Mov a,#0xF0 ; a 11110000

RR a ; a 11100001

RR a

Mov a,#0xF0 ; a 11110000

RR a ; a 01111000

Rotate through Carry

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Rotate through Carry

RRC a

mov a, #0A9h ; a A9

add a, #14h ; a BD (10111101), C0

rrc a ; a 01011110, C1

RLC a

mov a, #3ch ; a 3ch(00111100)setb c ; c 1

rlc a ; a 01111001, C1

C

C

Rotate and Multiplication/Division

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Rotate and Multiplication/Division

Note that a shift left is the same asmultiplying by 2, shift right is divide by 2

mov a, #3 ; A 00000011 (3)clr C ; C 0

rlc a ; A 00000110 (6)

rlc a ; A 00001100 (12)

rrc a ; A 00000110 (6)

Swap

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Swap

SWAP a

mov a, #72h ; a 27h

swap a ; a 27h

Bit Logic Operations

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Bit Logic Operations

Some logic operations can be used with single bitoperands

ANL C, bit

ORL C, bit

CLR CCLR bit

CPL C

CPL bit

SETB C

SETB bit

bit can be any of the bit-addressable RAM locationsor SFRs.

Shift/Mutliply Example

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Shift/Mutliply Example

Program segment to multiply by 2 and add1.

Program Flow Control

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Program Flow Control

Unconditional jumps (go to)

Conditional jumps

Call and return

Unconditional Jumps

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Unconditional Jumps

SJMP ; Short jump,relative address is 8-bit 2s complement

number, so jump can be up to 127 locations

forward, or 128 locations back.

LJMP ; Long jumpAJMP ; Absolute jump to

anywhere within 2K block of program memory

JMP @A + DPTR ; Long

indexed jump

Conditional Jump

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Conditional Jump

These instructions cause a jump to occur only if acondition is true. Otherwise, program executioncontinues with the next instruction.

loop: mov a, P1

jz loop ; if a=0, goto loop,; else goto nextinstruction

mov b, a

There is no zero flag (z)

Content of A checked for zero on time

Conditional jumps

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Conditional jumps

Mnemonic DescriptionJZ Jump if a = 0

JNZ Jump if a != 0

JC Jump if C = 1

JNC Jump if C != 1JB , Jump if bit = 1

JNB , Jump if bit != 1

JBC , Jump if bit =1, &clear

bit

CJNE A, direct, Compare A and memory,

jump if not equal

More Conditional Jumps

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More Conditional Jumps

Mnemonic Description

CJNE A, #data Compare A and data, jump

if not equal

CJNE Rn, #data Compare Rn and data,

jump if not equalCJNE @Rn, #data Compare Rn and memory,

jump if not equal

DJNZ Rn, Decrement Rn and then

jump if not zero

DJNZ direct, Decrement memory and

then jump if not zero

Call and Return

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Call and Return

Call is similar to a jump, butCall pushesPC on stack before branching

acall ; stack PC

; PC address 11 bit

lcall ; stack PC

; PC address 16 bit

Return

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Return

Return is also similar to a jump, butReturn instruction pops PC from stack to get

address to jump to

ret ; PC stack

Subroutines

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Subroutines

Main: ...

acall sublabel

...

...sublabel: ...

...

retthe subroutine

call to the subroutine

Initializing Stack Pointer

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Initializing Stack Pointer

SP is initialized to 07 after reset.(Same address as R7)

With each push operation 1st , pc is increased.

When using subroutines, the stack will be used to store thePC, so it is very important to initialize the stack pointer.Location 2Fh is often used.

mov SP, #2Fh

Subroutine - Example

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E mpsquare: push b

mov b,a

mul ab

pop b

ret

8 byte and 11 machine cycle

square: inc a

movc a,@a+pc

ret

table: db 0,1,4,9,16,25,36,49,64,81

13 byte and 5 machine cycle

Subroutine another example

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Subroutine another example

; Program to compute square root of value on Port 3

; (bits 3-0) and output on Port 1.org 0

ljmp Main

Main: mov P3, #0xFF ; Port 3 is an input

loop: mov a, P3

anl a, #0x0F ; Clear bits 7..4 of Alcall sqrt

mov P1, a

sjmp loop

sqrt: inc a

movc a, @a + PC

ret

Sqrs: db 0,1,1,1,2,2,2,2,2,3,3,3,3,3,3,3

end

reset service

main program

subroutine

data

Why Subroutines?

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Why Subroutines?

Subroutines allow us to have "structured"assembly language programs.

This is useful for breaking a large design

into manageable parts.It saves code space when subroutines can

be called many times in the same program.

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8051 timer

Interrupts

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Interrupts

mov a, #2

mov b, #16mul ab

mov R0, a

mov R1, b

mov a, #12

mov b, #20mul ab

add a, R0

mov R0, a

mov a, R1

addc a, bmov R1, a

end

Progra

mExecution

interrupt

ISR: inc r7

mov a,r7

jnz NEXT

cpl P1.6

NEXT: reti

return

Interrupt Sources

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Interrupt Sources

Original 8051 has 5 sources of interrupts Timer 0 overflow Timer 1 overflow External Interrupt 0 External Interrupt 1 Serial Port events (buffer full, buffer empty, etc)

Enhanced version has 22 sourcesMore timers, programmable counter array, ADC, more

external interrupts, another serial port (UART)

Interrupt Process

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Interrupt Process

If interrupt event occurs AND interrupt flag forthat event is enabled, AND interrupts areenabled, then:

1. Current PC is pushed on stack.

2. Program execution continues at the interruptvector address for that interrupt.

3. When a RETI instruction is encountered, the PCis popped from the stack and program execution

resumes where it left off.

Interrupt Priorities

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Interrupt Priorities

What if two interrupt sources interrupt atthe same time?

The interrupt with the highest PRIORITY

gets serviced first.All interrupts have a default priority

order.

Priority can also be set to high or low.

Interrupt SFRs

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Interrupt SFRs

Global Interrupt Enablemust be set to 1 for any

interrupt to be enabled

Interrupt enables for the 5 original 8051 interrupts:

Timer 2

Serial (UART0)

Timer 1

External 1Timer 0

External 01 = Enable

0 = Disable

Interrupt Vectors

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Interrupt Vectors

Each interrupt has a specific place in code memory whereprogram execution (interrupt service routine) begins.

External Interrupt 0: 0003h

Timer 0 overflow: 000BhExternal Interrupt 1: 0013h

Timer 1 overflow: 001Bh

Serial : 0023h

Timer 2 overflow(8052+) 002bh

Note: that there are

only 8 memory

locations betweenvectors.

Interrupt Vectors

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Interrupt Vectors

To avoid overlapping Interrupt Service routines, it iscommon to put JUMP instructions at the vectoraddress. This is similar to the reset vector.

org 009B ; at EX7 vector

ljmp EX7ISR

cseg at 0x100 ; at Main program

Main: ... ; Main program

...

EX7ISR:... ; Interrupt service routine

... ; Can go after main programreti ; and subroutines.

Example Interrupt Service Routine

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p p

;EX7 ISR to blink the LED 5 times.

;Modifies R0, R5-R7, bank 3.

;----------------------------------------------------

ISRBLK: push PSW ;save state of status word

mov PSW,#18h ;select register bank 3

mov R0, #10 ;initialize counter

Loop2: mov R7, #02h ;delay a while

Loop1: mov R6, #00hLoop0: mov R5, #00h

djnz R5, $

djnz R6, Loop0

djnz R7, Loop1

cpl P1.6 ;complement LED value

djnz R0, Loop2 ;go on then off 10 timespop PSW

reti

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few basics of 8051