Feng-Xiang Huang

112/04/18

International Symposium Quality Electronic Design (ISQED), 2012 13thM. H Neishaburi, Zeljko Zilic, McGill University, Quebec Canada.

As emerging System on Chips (SoCs) tend to have many cores, the interactions among cores through functional interconnects such as bus or Network on Chips (NoCs) are and on-chip communication has accentuated the need to enhance traditional debug methods for SoCs. In this paper, we propose a new debug aware Network Interface (NI). The proposed debug aware NI monitors the transactions issued by processing elements and extracts the global order of transactions from the local partial order of transactions. Moreover, the proposed interface provides a mechanism for a cross-triggers debugging. The modules in charge of cross-trigger debugging monitor the transaction issued by connected IP blocks and invoke appropriate debug operations at the right time. Trace data and trigger events are extracted and routed to Shared Direct Memory Access Unit( SDMAU). SDMAU combines debug traces from different NIs. The major benefits of using our proposed mechanism over traditional techniques are as follows: 1) the proposed debug aware NI can generate non-intrusively the global states of a system that involve multiple clock domains and enable validation of global properties, 2) It can detect, mark and bypass severe fault conditions such as deadlocks resulting from design errors or electrical faults in real time, 3) SDMAU maintains an efficient transfer of trace data to an external memory and there is no need for a large internal trace memory.

Runtime Checking of Serializability in Software Transactional Memory[5]

Runtime Checking of Serializability in Software Transactional Memory[5]

Time-stamping mechanismIntrusiveReduces the system throughput

An Enhanced Debug-Aware Network Interface

for Network-on-chip

An Enhanced Debug-Aware Network Interface

for Network-on-chip

Effcient Network Interface Architecture for Network-on-

Chips

Effcient Network Interface Architecture for Network-on-

Chips

•NORCHIP, 2009, Finland

•ISQED, 2012, Canada

[24] [25] [26][24] [25] [26]

•Make Status register of specific core visible

Communications among cores (bus interface/ memory controller/ up)

Distributed of application on NoC。Global vs. Local (transaction ordering)

Design vs. electrical error。Deadlock。Livelock 。Race condition 。Data Inconsistency

a debug-aware NI Character Communication port/ debug interface Non-intrusively & Multi clock domain Compatible AXI Detect & bypass fault Efficient transfer of trace data to external memory

Fig. AXI-Compatible NoC-Based System

Master Side NI Request

。Slicer unit

Response。Merger unit

Local Debug Unit (LDU)。Reorder Buffer。Tran. Table。SDMAU

Trace info. to external trace memory

Cross Triggers

Rou

ter

Packetizer to Router

de_Packetizer from Router

Transaction packet (header/data/tail)

Master Side NI- Flow LDU

。Tran.Table & Reorder Table

Fig. NI flow

Master Side Network Interface LDU

。Tran.Table & Reorder Table

Fig. NI flow

Cross Trigger unit Inform LDU Debug commands (stops, resume, trace, and etc.) Trigger event generation(Debug Reg, Comparator)

Environment Assembly code: Factorial of consecutive number ranging from 1 to 100

Inserted design errors in side NoC routers. 94 fault pattern be detected by LDU

。 Observed that 60% data inconsistenc 32% deadlock

Program (each iteration to check R0(result) by Cross trigger)-------------------------------1!2!3!…100!

Error Fig.

Proposed A debug aware NI that

。Non-intrusively 。Multiple clock domains system。Detects & bypass severe faulty condition (LDU && Trigger)。Compatible AXI protocol

Error information Figure 8

Issue Trace buffer/Table is widely used

。Problem definition of behavior of SoC/NoC components。Specification definition

1.u-processor E-ICE I-IP

2.IP 1149.1 1500 Nexus

3.Memory BIST

4.Bus Protocol Check Protocol Tracer

5.Debug/Test Platform Prof. Li.

6.Dedicated hardware I-IP

7.Embedded logic analyzer ChipScope

8.NoC Network Interface

1.u-processor E-ICE I-IP

2.IP 1149.1 1500 Nexus

3.Memory BIST

4.Bus Protocol Check Protocol Tracer

5.Debug/Test Platform Prof. Li.

6.Dedicated hardware I-IP

7.Embedded logic analyzer ChipScope

8.NoC Network Interface

Memory

1149.1cores

1500cores

TAPC

TAMController

ProtocolCheck

ProtocolTracer

OCP-IP

WrapperICE

Memory Interface

μp

E-ICE

Memory Interface

I-IP

Memory Interface

IPI-IP

1

2.6

3 4

5.6

IP

Network Interface

Router/Switch to Networking

NoC

DFD1.Shadow registers/scan chains

(specific trgger/hardware checker)

2.On-chip trace buffers

DFD1.Shadow registers/scan chains

(specific trgger/hardware checker)

2.On-chip trace buffers