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Feed-Forward- and Shared-Buffer-BasedOptical Packet Switch ArchitectureRajat Kumar Singh a , Rajiv Srivastava b & Yatindra Nath Singh ca IIIT Allahabad, Jhalwa , Allahabad, Indiab IIT Rajasthan , Kanpur, Indiac IIT Kanpur , Kanpur, IndiaPublished online: 22 Sep 2010.

To cite this article: Rajat Kumar Singh , Rajiv Srivastava & Yatindra Nath Singh (2010) Feed-Forward-and Shared-Buffer-Based Optical Packet Switch Architecture, Fiber and Integrated Optics, 29:5,381-393, DOI: 10.1080/01468030.2010.503983

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Fiber and Integrated Optics, 29:381–393, 2010

Copyright © Taylor & Francis Group, LLC

ISSN: 0146-8030 print/1096-4681 online

DOI: 10.1080/01468030.2010.503983

Feed-Forward- and Shared-Buffer-Based Optical

Packet Switch Architecture

RAJAT KUMAR SINGH,1 RAJIV SRIVASTAVA,2 and

YATINDRA NATH SINGH 3

1IIIT Allahabad, Jhalwa, Allahabad, India2IIT Rajasthan, Kanpur, India3IIT Kanpur, Kanpur, India

Abstract This architecture incorporates wavelength-routed loop-buffer modules in

the feed-forward configuration, and the buffering in these modules is recirculatingin nature, using shared memory. The signal quality will deteriorate during each

revolution, due to the insertion loss of the various optical components; therefore,it will impose a limit on the number of circulations that a packet can take in the

buffer before its correct reception. Generally, this limit has not been considered inthe past, but one should have to take care of it in the current scenario for the actual

switching systems.

Keywords loop-buffer memory, optical buffering, optical packet switch, wavelengthdivision multiplexing

1. Introduction

In optical transport networks, the current approach is to use switches to set up light paths.

These all-optical switches are circuit switches and transparent to information carried over

the light path. Another viable and possible approach is optical packet switching. In the

current scenario, all-optical packet switching is hybrid in nature, where the header is

converted into the electrical form, and the payload remains in optical domain throughout

the switch. The information contained in the header is used to route the packet. Several

architectures for optical packet switching are proposed in the literature [1, 2]. Wavelength

division multiplexing (WDM) technology has been incorporated [3] in some of them to

improve their performance.

The important functionalities in photonic packet switching for successful routing of a

packet are control, packet synchronization, clock recovery, packet routing, contention res-

olution, and packet header replacement [4, 5]. Among all the aspects, contention reso-

lution is the major issue for all-optical networks. To avoid contention, one can either

use deflection routing [6] or store the contending packets in the fiber delay lines [7].

The wavelength conversion technique can be applied for contention resolution. Optical

buffering can be incorporated in three ways: input buffering, output buffering, and

shared buffering [8, 9]. The shared buffer optical switch is more advantageous and flexible

Received 18 January 2010; accepted 22 June 2010.Address correspondence to Dr. Rajat Kumar Singh, 2123, CC-1, IIIT Allahabad, Jhalwa,

Allahabad, 211012, India. E-mail: rajat.singh@gmail.com

381

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382 R. K. Singh et al.

compared to the other two, because it also provides switching along with buffering. These

shared-type buffers can be implemented in optical switches either in the feedback or

in the feed-forward configuration [10–13]. Two architectures incorporating loop-buffer

architectures in a feedback configuration have already been proposed [14, 15]. All of these

optical packet switch architectures also utilize the WDM technique for better results.

This article discusses one of the three architectures proposed in [13], and that

architecture will also be analyzed in terms of signal power loss and noise induced due

to the presence of various optical components in the loop-buffer module. The optical

buffering is done using feed-forward shared fiber delay lines. These shared buffers

use recirculating fiber loops and utilize WDM for storing the packets [16, 17]. The

recirculating loop buffers are designed for equal-length packets. The length of the loops,

as well as the length of packets, is kept equal to the one-time slot duration.

The organization of rest of the article is as follows. A brief description of the archi-

tecture is given in Section 2. Power budget analysis for this architecture is presented in

Section 3. Scheduling algorithms for the operation of the switch is explained in Section 4,

and simulation results are discussed in Section 5. The article is concluded in Section 6.

2. Brief Description of Switch Architectures

The switch architecture under consideration and its buffer module are shown in Figures 1

and 2, respectively. The basic building block of the architecture consists of three sections:

(1) a scheduling section, (2) a combined section for routing the packet through either

M direct path or m buffer modules, and (3) a switching section. The scheduling and

switching sections of the architecture (Figure 1) are constructed using space switch. The

size of these sections are N � K and K � N , respectively, while the total size of switch

architecture is N � N . The parameter K is defined as K D M C m � D, where M is

the number of direct paths with no delay, m is the number of buffer modules used in the

feed-forward manner, and D is the number of input/output ports assigned to each buffer

module. The capacity of each buffer module is considered to be equal to B (� D); i.e.,

it can store up to B packets at different wavelengths. The range of these wavelengths is

different from the incoming wavelengths. Also, all buffer modules can reuse the same

Figure 1. Switch architecture.

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Feed-Forward- and Shared-Buffer-Based Architecture 383

Figure 2. Loop-buffer module.

range of wavelengths because the signals in different buffer modules are independent to

each other and do not interfere.

Each buffer module (Figure 2) consists of D tunable wavelength converters (TWCs),

a recirculating loop, and one wavelength demultiplexer (DEMUX). Packets from all

of these D inputs use WDM to share the recirculating loop buffer. The number of

buffer wavelengths (B/ inside the loops depends on the switch design, desired traffic

throughput, packet loss probability, and size of the switch [18]. The wavelength allocation

of the packets in the loop buffer depends on the routing and priority algorithm for the

switch. The wavelength range of the DEMUX placed at the output of the buffer module

is chosen to be different from the range of buffer wavelengths to prevent the direct

transfer of packets through the 3-dB coupler without entering the recirculating loop.

The recirculating loop (Figure 3) consists of a 3-dB coupler, DEMUX, TWC, combiner,

erbium-doped fiber amplifier (EDFA), isolator, and band pass filter (BPF). The number

of TWCs and the size of the DEMUX/combiner, placed inside the loop, are considered

equal to B . The EDFA is placed inside the loop to compensate the power loss in the loop

buffer during revolution, and the BPF is used to band-limit the amplified spontaneous

emission (ASE) noise of the amplifier.

The complete operation of the switch is controlled by an electronic control unit

(Figure 4), which tunes various components of the loop buffer as per the decision and

is similar in nature to what was described in [12]. Various operation performed by the

electronic controller are shown in Figure 4. The semiconductor optical amplifier (SOA)

based TWC, which was proposed and fabricated in [12], has been used here, and it is

operated on the nano-second scale. The space switches are considered as an SOA-based

electro-optical switch. The switching speed of this device is also of the order of nano-

Figure 3. Recirculating loop buffer.

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384 R. K. Singh et al.

Figure 4. Electronic control unit.

second, while the insertion loss will be 0.5-dB per stage. The crosstalk is low (�30 dB)

and is neglected in the calculation [19]. Thus, the tuning speed of the TWCs and the

switching speed of the space switch do not put any constraint on the switching operation.

The TWC is a noisy device, but it has been assumed as a noiseless device for the power

budget analysis in this article. This assumption is justified, because the introduction of

noise may be compensated by the regeneration of the signal in the TWC [20].

3. Power Budget Analysis

The presence of various optical components in the loop-buffer memory module causes

losses in the signal power, while the EDFA adds the noise power. These degrading factors

restrict the storage time (circulation count) in the loop buffer. Thus, the maximum number

of allowed circulations (C ) for a packet must be calculated before its correct reception.

In other words, the packets cannot be retrieved after the .C C 1/th revolution, because

the value of the bit error rate (BER) will cross the acceptable limit. The proposed switch

is analyzed in terms of loss, power, and noise by using the simplified structure, as shown

in Figure 2.

3.1. Loss Analysis

The loss analysis has been divided into three parts according to the three sections

(Figure 1). The input (scheduling) and output (switching) sections consist of a space

switch fabric so the loss is through them:

Lin D LSS and Lout D LSS : (1)

Loss through the buffer module for one circulation is obtained in terms of each component

loss and can be written as

LBM .1/ D LTWCLComALBL3 dBLDEMUX ; (2)

where ALB is the loss through the recirculating loop, which consists of eight splices [16],

and is defined as

ALB D L3 dBLDEMUXLTWCLComLISOLBPF8LSLF : (3)

Here LCom and LISO are the combiner and isolator insertion loss, respectively.

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Feed-Forward- and Shared-Buffer-Based Architecture 385

Table 1

Values of different parameters

Symbol Quantity Value

R Responsivity 1.28 amp/watts

nsp Population inversion factor 1.2

h Planck constant 6:6 � 10�34 J-s

Be Electrical bandwidth 10 GHz

Bo Optical bandwidth 20 GHz

q Electronic charge 1:6 � 10�19 Coulomb

RL Load resistance 300 �

T Temperature 300 K

KB Boltzmann constant 1:38 � 10�23 J/K

L3 dB Loss of 3-dB coupler 3.4 dB

LCom Combiner loss (W � 1)a 10 Log10 W dB

LDEMUX Loss of DEMUX 1.5 dB

LTWC Loss of TWC 2 dB

LS Splice loss 0.2 dB

LF Fiber loss 0.2 dB/Km

LISO Isolator loss 0.15 dB

LSS Space switch loss (N � N ) 0:5.Log2 N / dB

LBPF Loss of BPF 1 dB

aW is a general variable, taken as the number of input of combiner.

The loss of the buffer module after J circulations will be

LBM .J / D LTWCLCom.ALB/J L3 dBLDEMUX: (4)

Here, J is the probable number of allowed circulations. Thus, the total loss through the

switch architecture after J circulations is

L D LinLBM .J /Lout : (5)

The definitions and values of various parameters used in the above and the ongoing

analysis are described in Table 1.

3.2. Power Analysis

Following Figure 1, the input power is defined as Pin.b/, where b = 1 for bit “1” and 0

for bit “0.” Thus, the signal power after one circulation, just before the 3-dB coupler, is

given by

P1.b/ D Pin.b/A1ALB G C .G � 1/nsph�BoA2; (6)

where

A1 D LinLTWCLCom; (7)

A2 D LISOLBPF3LSLF : (8)

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386 R. K. Singh et al.

In Eq. (6), the first term represents the signal power, and the second term is the ASE

noise power [21]. Here, G is the gain of the EDFA, Bo is the optical bandwidth, A1 is

the loss from the switch input up to the input of 3-dB coupler, and A2 is the loss in the

second-half portion of loop, i.e., after the EDFA up to the 3-dB coupler (Figure 3). Thus,

the power for bit b after J circulations is

PJ .b/ D Pin.b/A1.ALB /J GJ C .G � 1/nsph�BoA2F; (9)

where

F D

8

ˆ

<

ˆ

:

1 � .ALB G/J

1 � ALBG; ALBG < 1

J; ALBG D 1

9

>

=

>

;

: (10)

For signal-to-noise ratio (SNR) maximization, the product of loop gain and loop loss

must be equal to unity (i.e., ALBG D 1) [22]. Thus,

PJ .b/ D Pin.b/A1 C J.G � 1/nsph�BoA2: (11)

Hence, the power for bit b at the output of the switch is given as

P.b/ D PJ .b/L3 dBLDEMUXLout: (12)

3.3. Noise Analysis

The optical amplifiers not only restore the signal but also add ASE noise to it. Due to

square law detection by the photodetector in the receiver, various noise components are

generated. These noise components are shot noise, ASE-ASE beat noise, sig-ASE beat

noise, ASE-shot beat noise, and thermal noise with variances given by �2s , �2

sp-sp, �2sig-sp,

�2s-sp, and �2

th, respectively [21]. These noise terms for bit b after J circulations are

given as

�2s D 2qRP.b/Be; (13)

�2sp-sp D 2R2P 2

sp.J /.2Bo � Be/Be

B20

; (14)

�2sig-sp D 4R2P.b/

Psp.J /Be

B0

; (15)

�2s-sp D 2qRPsp.J /Be ; (16)

�2th D

4kTBe

RL

; (17)

where

Psp.J / D J nsp.G � 1/h�BoA2L3 dBLDEMUXLout: (18)

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Feed-Forward- and Shared-Buffer-Based Architecture 387

Thus, the total noise variance for bit b is

�2.b/ D �2s C �2

sp-sp C �2sp-sig C �2

s-sp C �2th: (19)

The BER [21] can be obtained as

BER D Q

�

I.1/ � I.0/

�.1/ C �.0/

�

; (20)

where Q.x/, the error function, is defined as

Q .z/ D1

p2�

Z

1

z

exp.�z2=2/dz: (21)

Here I.1/ D RP.1/ and I.0/ D RP.0/ are photocurrents, sampled by the receiver

during bit “1” and bit “0,” respectively, and R is the responsivity of the photodetector.

3.4. EDFA Gain Calculation and Wavelength Selection for Loop

The gain of the EDFA is evaluated by the model given in [23]. An automatic gain control

(AGC) scheme is assumed, where gain of the EDFA will remain constant, irrespective

of the number of channels passing through it [22, 24]. Since a loop-buffer module of

capacity B with its various combination (i.e., B D 4, 8, and 12) is used, the size, as

well as gain, of the EDFA will also be changed in order to maintain the condition of

ALBG D 1 inside the loop. The gain of the EDFA for a different buffer space has

been computed by considering the loss through each optical component of loop. The

wavelength selections have been done by following the ITU-T grid. The channel spacing

considered in this article is greater than six times the bit rate (i.e., �f � 6Rb) for the

minimization of cross-talk [18, 25].

Depending upon the above analysis, the maximum number of allowed circulations

(C ) is obtained at different power levels (mW) for various sizes of N and B (Table 2).

Here, C is the largest value of J , for which the acceptable limit of the BER is 10�9 (i.e.,

BER � 10�9).

Table 2

Maximum allowed circulations (C ) for switch of various sizes and

buffer wavelength (B) at different power levels (P ) for D D 4

N B

C at

P D 1 mW

C at

P D 2 mW

C at

P D 4 mW

C at

P D 6 mW

C at

P D 8 mW

C at

P D 10 mW

16 4 14 28 56 84 113 141

32 4 11 22 44 67 89 112

64 4 8 17 35 53 71 89

16 8 4 9 18 27 36 45

32 8 3 7 14 21 28 35

64 8 2 5 11 17 22 28

16 12 1 2 5 8 11 14

32 12 1 2 4 6 9 11

64 12 0 1 4 5 7 9

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388 R. K. Singh et al.

4. Scheduling Algorithm

The buffering technique of the proposed architectures utilizes the loop-buffer module in a

feed-forward configuration. Routing is done in such a way that the first-in–first-out (FIFO)

discipline can be maintained. The priority will be given to the buffered packets over the

incoming packets. For any output, if there is no packet in any of the buffer modules,

and if more than one packet arrives at various inputs of the switch for that output, then

one of them will be transmitted through the direct line (if free), and remaining packets

will be stored in the buffer modules (if free). Thus, the direct path will only be used

when there is no packet in any of the buffer modules destined for the same output port.

Each loop-buffer module uses B C D wavelengths, where B is the number of buffer

wavelengths used to store a packet in the buffer, and D is the number of wavelengths

used for reading out the packets from loop-buffer module. The buffering in these modules

is done using the following algorithm.

1. For the buffering of packets, the respective TWC at the input of an available

buffer module tunes the wavelength of the incoming packet to any one of the free

wavelengths of the loop buffer.

2. Once the packet is placed in the buffer, it will keep recirculating, and the corre-

sponding TWC in the recirculating loop buffer will remain transparent until the

packet is desired to be read out.

3. For reading out a packet when the contention is resolved, the corresponding

TWC inside that loop tunes the packet wavelength to any of the DEMUX port

wavelengths, and the packet is directed toward the switching section through the

DEMUX.

4. Finally, these scheduled packets through switching section can be directed to a

destined output port through the space switch fabric.

5. The number of packets xi for the output i stored in all the buffer modules should

never be greater than min.mB; C/; i.e.,

xi � min.mB; C/; 1 � i � N:

Here, m is the number of buffer modules, and Bpackets can be stored at different

wavelengths in each of these modules. Therefore, mB is the maximum buffering

capacity, and C is the maximum allowed circulations. If mB < C , then there

will be no circulation limit, and mB packets can be stored in the buffer. But if

mB > C , then there will be circulation limit, and it is useless to store packets

more than C because of the acceptable BER limit.

6. The total amount of buffered packets must be less than or equal to the maximum

buffering capacity mB; i.e.,

X

xi � mB; 1 � i � N:

7. Simultaneous read and write is allowed in the same slot for the same wavelength.

8. During any time slot, FIFO discipline will be maintained.

9. If any of the incoming packets will not be able to pass through the switch due

to the maximum buffering capacity limitation or the circulation limit, then it will

be dropped at the input of the switch.

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Feed-Forward- and Shared-Buffer-Based Architecture 389

5. Simulation Results

The simulations are done using the scheduling algorithm, and the results for loss probabil-

ity and average delay are obtained under various loading conditions. In the simulations,

uniform random arrival of traffic is considered. To maintain the switch size equal to

N � N , the values of m and B are chosen in such a manner that they can provide

minimum loss probability. Therefore, for N D 16 at P D 2 mW, it was found that the

loss probability is minimum (8 � 10�5) for m D 3 and B D 8 (Figure 5), whereas at

P D 8 mW, the minimum (2 � 10�5) is obtained for m D 3 and B D 12. The later

obtained loss probability is four times lower than the earlier one, but this advantage will

be overshadowed by the induction of non-linear effects in the fiber due to the higher

power level. The average delay is nearly the same at B D 8 and B D 12 for m � 3

(Figure 6). Therefore, the case of m D 3 and B D 8 is an optimal choice for the 16 � 16

switch.

It can be observed that as the signal power increases, the probability of packet loss

decreases due to the increment in C with power. The switch parameters for simulations

are N D 16, M D 4, m D 3, and D D 4; thus, the maximum buffering capacity (mB)

for B D 8 is 24, while for B D 12, it will be 36. At lower power levels and under

lower loading conditions, B D 8 gives better results as compared to B D 12 (Figure 7)

because of the greater number of allowed circulations for B D 8. But, at higher powers

and lower loading conditions, B = 12 gives better results as compared to B D 8. The

explanation lies in the fact that the allowed circulations for individual packets in the

case of B D 12 is as good in number as that achieved with B D 8 (Table 2). Also, at

higher powers, the greater number of circulations for B D 8 does not give any advantage,

Figure 5. Optimization of B and m for N D 16 in terms of loss probability.

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390 R. K. Singh et al.

Figure 6. Optimization of B and m for N D 16 in terms of average delay (slot count).

Figure 7. Probability of packet loss for various power levels at D D 4.

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Feed-Forward- and Shared-Buffer-Based Architecture 391

Figure 8. Average delay (slot count) for various power levels at D D 4.

because the storage capacity is limited by the available buffer capacity and not by the

circulation limit. Under higher loading conditions, the loss probability is very large for

both cases.

The average delay for B D 8 is nearly equal at all power levels (Figure 8), whereas

for B D 12, the average delay increases with higher power levels due to more utilization

of buffering capacity. Also at lower power levels, the average delay is very small for

B D 12 and nearly constant under various loading conditions.

On the basis of above observations, it can be deduced that B D 12 should be favor-

able over B D 8, because it provides better loss probability. But the main disadvantage

of B D 12 is that to achieve this greater capacity in the recirculating loop, a larger size

DEMUX/combiner and more TWCs will be required. Also, the gain of the EDFA will

be much higher. Hence, the loop-buffer module of capacity B D 8 is considered as the

optimal choice for all power levels.

6. Conclusion

This article presents an architecture of an optical packet switch that uses WDM loop-

buffer modules in a feed-forward configuration. There is a limitation on the storage time;

i.e., the packet cannot circulate for longer durations because of degradation in the signal

quality during each revolution. Therefore, the maximum number of allowed circulations

in the loop buffer has been calculated. Also, due to the reuse of the same set of wavelength

range in all buffer modules, the need for a large range of wavelengths will be reduced.

The switch is optimized to achieve the best packet loss probability at the reasonable

delay performance. This switch architecture is scalable, but the main constraint is the

requirement of a large number of optical components.

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392 R. K. Singh et al.

The degradation in the signal quality demands the regeneration of the signal and

needs to be further investigated. In order to focus on the performance of the switch, the

analysis is done under the assumption of a single-node network instead of the network

consisting of several such switches. The fresh data is generated at the input and received

at the switch output. In future work, the performance of the network having multiple

such switches will be investigated.

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13. Singh, R. K., Srivastava, R., Mangal, V., and Singh, Y. N. 2006. Wavelength routed shared

buffer based feed-forward architectures for optical packet switching. IEEE INDICON 2006,

New Delhi, India, September 15–17.

14. Singh, R. K., Srivastava, R., and Singh, Y. N. 2007. Wavelength division multiplexed loop

buffer memory based optical packet switch. Optic and Quantum Electronics 39(1):15.

15. Singh, R. K., Srivastava, R., and Singh, Y. N. 2007. AWG and EDFA based optical packet

switch using feedback shared loop buffer memory. Optic and Quantum Electronics 39(14):1153.

16. Shukla, S., Srivastava, R., and Singh, Y. N. 2004. Modeling of fiber loop buffer based switch.

Photonics 2004 1(1):248.

17. Srivastava, R., Singh, R. K., Mangal, V., and Singh, Y. N. 2006. A modified photonic switch

architecture based on fiber loop memory. IEEE INDICON 2006, New Delhi, India, September

15–17.

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Biographies

Rajat Kumar Singh was born in Jaunpur (UP), India, in 1975. He received his

B.Tech. in electronics and instrumentation engineering from Bundelkhand Institute of

Engineering and Technology, Jhansi (UP), in 1999, his M.E. in communication engineer-

ing from Birla Institute of Technology & Science, Pilani (Raj.) in 2001, and his Ph.D.

from Indian Institute of Technology, Kanpur, in 2007. Currently, he is working as faculty

at Indian Institute of Information Technology, Allahabad. His research interests are in

the field of photonic packet switching, telecom networking, and optical networks.

Rajiv Srivastava was born in Kanpur (UP), India, in 1976. He received his M.Sc.

in physics (solid state) from CSJM University, Kanpur (UP), in 1997, his M.Tech. in

laser technology from Indian Institute of Technology, Kanpur, in 2003, and his Ph.D.

from Indian Institute of Technology, Kanpur, in 2009. Currently, he is working as faculty

at Indian Institute of Technology, Rajasthan. His research interests are in the field of

photonic packet switching and soliton-based optical networks.

Yatindra Nath Singh was born in Delhi, India, in 1969. He obtained his B.Tech. in

electrical engineering from Regional Engineering College, Hamirpur, Himachal Pradesh,

in 1991, his M.Tech. in optoelectronics and optical communications from Indian Insti-

tute of Technology, Delhi, in 1992, and his Ph.D. from the Department of Electrical

Engineering, Indian Institute of Technology, Delhi, in 1997. He was with the Depart-

ment of Electronics and Computer Engineering, IIT Roorkee, India as faculty from

February through July of 1997. He is currently working as faculty in the Department

of Electrical Engineering, Indian Institute of Technology, Kanpur. He was awarded the

AICTE young teacher award in 2002. He is a fellow of Institution of Electronics and

Telecommunication Engineers (IETE), India, and a senior member of The Institution of

Electrical and Electronics Engineers, Inc., (IEEE) USA. His academic interests include

optical networks, photonic packet switching, optical communications, telecom networks,

network managements, e-learning systems, and open-source software development. He is

actively involved in development of open-source e-learning platform tools code named

Brihaspati.

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