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VHDL


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Module I Introduction to VHDLModule II

Modeling Digital SystemsModule III Basic Language ConceptsModule IV Modeling Delays

Module V Dataflow Style of ModelingModule VI Behavioral Style of ModelingModule VII Structural Style of Modeling

Module VIII SubprogramsModule IX Advanced ConceptsModule X Orcad Simulation


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Module I Introduction to VHDL


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What is VHDL?

VHSIC Very High Speed Integrated Circuit

H Hardware

D Description

L Language


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Hardware Description Languages

A Language to describe hardware atmultiple levels of Abstraction

Ability to represent hardware parallelism

Ability to represent timing relationships

Ability to represent logic structure


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Why a new Language?

Languages like C/C++ lack concept totiming relationship

Writing code to represent Parallelism or Concurrency is very difficult


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The Role of HDL

Interoperability: models at multiple levels of abstractionTechnology independence: portable modelDesign re-use and rapid prototyping


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Traditional vs. HD Languages

Procedural programming languages provide the how or recipes :

for computation

for data manipulationfor execution on a specific hardware model

Systems can be described from many different points of view :

Behavior: what does it do?

Structure: what is it composed of?Functional properties: how do I interface to it?Physical properties: how fast is it?


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What is HARDWARE & What kindof DESCRIPTION?

The word 'hardware', is used in a wide variety of contexts which range fromcomplete systems like personal computers on one side to the small logical gates

on their internal integrated circuits on the other side.This is why different descriptions exist for the hardware functionality.Complex systems are often described by the behavior that is observable from

the outside. Abstract behavioral models are used in this case that hide all the

implementation details.

The description of a basic logic gate, on the other hand, may consist of onlyone Boolean equation, which is a very short and precise description.

Hardware Description Language = "Programming language for modeling hardware(Digital)


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Why do we describe systems

Design Specification unambiguous definition of components and interfaces in a large design

Design Simulation verify system/subsystem/chip performance prior to design implementation

Design Synthesis automated generation of a hardware design


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Digital System Design Flow


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Module II Modeling Digital Systems


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Systems Hierarchy


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What elements should be ina description

Descriptions should be at multiple levels of abstractionThe descriptive elements must be common to multiple

levels of hierarchyThe elements should enable meaningful and accurate

simulation of hardware described using the elementsElements should have attributes of time as well as

function

The elements should enable the generation of hardwareelements that realize a correct physical implementationExistence of a mapping from elements to VLSI devices


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Abstraction

Abstraction is hiding of details Differentiation between essential and nonessential information

Creation of abstraction levels On every abstraction level only the essential information is considered,nonessential information is left out

Equability of the abstraction

All information of a model on one abstraction level contains the same degreeof abstraction


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Abstraction Levels in IC DesignFunctional description of the model

No system clockSimulatable, only, but notsynthesizable

Design is divided into combinationallogic and storage elements

Synthesizable Description

Design isrepresented as a netlist with logic gates(AND, OR, NOT, ...)and storage elements

Different cells of the target technologyare placed on the chip

Connections are routed.

After the layout has been verified, thecircuit is ready for the production process


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Abstraction Levels and VHDL


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Information Content of AbstractionLevels


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Attributes of Digital Systems : Timing

Computation of events takes place at specific points in time

Need to wait for an event (in this case the clock)

Timing is an attribute of both synchronous and asynchronous systems


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Attributes of Digital Systems : Timing

Example

Asynchronous communication

No global clockStill need to wait for events on specific signals


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Attributes of Digital Systems : SignalValues


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Attributes of Digital Systems : MultipleDrivers


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Modeling Digital Systems

We seek to describe attributes of digital systems common tomultiple levels of abstraction

events, propagation delays, concurrencywaveforms and timingsignal valuesshared signals

Hardware description languages must provide constructs for naturally describing these attributes of a specific design

simulators use such descriptions for mimicking the physical systemsynthesis compilers use such descriptions for synthesizing manufacturable

hardware specifications that conform to this description


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Simulation vs. Synthesis


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Simulation of Digital Systems

Digital systems are modeled as the generation of eventsValueTransitions on signals

Discrete event simulations manage the generation and ordering of eventsCorrect sequencing of event processingCorrect sequencing of computations caused by events


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Synthesis and Hardware Inference


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Module III Basic Language Concepts


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Design Units

Primary design unitsEntityConfigurationPackage DeclarationThese are not dependent on other design units

Secondary design units

Package bodyArchitecture

Design units are created in design files

Now you know the layout of a VHDL program!


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Basic Rules, Syntax, and Constraints

Case InsensitiveCan Handle Analog Modeling (VHDL-AMS)Statements end with ; (May span multiple lines)White space characters are delimiters in the syntax

Allows Libraries and importing them in the current file

Comments start with - - List Delimiter is , Signal Assignment Operator


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Describing Design Entities

Primary programming abstraction is a design entityRegister, logic block, chip, board, or system

What aspects of a digital system do we want to describe?Interface: how do we connect to itFunction: what does it do?


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Describing the Interface : The EntityConstruct

The interface is a collection of p o r t s Ports have a typePorts have a mode


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Example Entity Descriptions


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Example Entity Descriptions : IEEE 1164


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Mode in


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Mode out


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Mode inout


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Bottom Line


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Describing Behaviour : The ArchitectureConstruct

Implementation of the design

Always connected with a specific entityOne entity can have several architectures

Entity ports are available as signals within the architecture

Contains concurrent statements


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Describing Behaviour : The ArchitectureConstruct

d f


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Identifiers

There are two kinds of identifiers in VHDL:

1. Basic Identifiers2. Extended Identifiers


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Basic/Normal Identifiers


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Extended Identifiers

Graphical characters includes:a) .b) !c) @d)

e) $ etc


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Reserved Words / Keywords

These have a specific meaning in the language, and therefore, cannotbe used as basic identifiers


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Data Objects

A data object, holds a value or a sequence of valuesof a certain specified type.

Every data object, belongs to one of the following four classes :

1. Constants2. Variables3. Signals4. File


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Deferred Constants

Example

constant NO_OF_INPUTS : INTEGER;

The value of the constant has not been specified in this case.Such a constant is called a DEFERRED CONSTANT, and it can appear only

inside a package declaration.

The complete constant declaration with the associated value, must appear in

the corresponding package body.


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Variables An object of variable class can hold a single value of a given type.However, in this case, different values can be assigned to the variable at

different times, using a variable assignment operator := It can optionally be assigned initial values (done only once prior to

simulation).

variable symbol: type [:= initial_value];

If no initial value is specified for a variable object, a default value is used asan initial value.

The default value is T LEFT, where T is the object type, and LEFT is apredefined attribute of a type, that gives the leftmost value in the set of valuesbelonging to type T.


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Variables Cont..


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Signals

An object belonging to the signal class, holds a list of values, whichincludes the current value of the signal, and a set of possible future values,that are to appear on the signal.

Future values can be assigned to the signal using a signal assignment

statement.

Examples:


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Signals vs. Variables


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File An object belonging to the file class, contains a sequence of values.Values can be read or written to the file using read procedures and write

procedures respectively.

file file_names:file_type_name [[open mode] is string expression];

The mode specifies whether, the file is to be used as a read only or write onlyor in the append mode.

file STIMULUS : TEXT open READ_MODE is /usr/home/add.sti;

The file STIMULUS is declared to be one of the predefined file type TEXT.

When the path is not specified, the file will have to be explicitly opened usinga file open procedure.

When no mode is specified, READ_MODE is used as the default mode.


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Data TypesEvery data object in VHDl, can hold a value, that belongs to a set of values.This set of values is specified by using a TYPE DECLARATION .

A TYPE is a name, that has associated with it, a set of values and a setof operations.

Certain types, and operations that can be performed on these objects

are predefined in the language.The declarations for the predefined types of the language are containedin package STANDARD.

The language also provides facility to define user customized datatypes, and the operations that can be performed on those data typedobjects, as and when needed.

The data types can be classified as:1. Scalar Types2. Composite Types3. Access Types4. File Types5. Incomplete Types


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SCALAR TYPESScalar types represents a single numeric value, or an enumeration value.Values belonging to these types, appear in sequential order.Every value has a position number associated with it.This number is the position of the value in the ordered list of values belonging

to that type.

The scalar types can broadly be classified under the following four categories:

1. Enumeration Type2. Integer Type3. Physical Type4. Real (Floating Point) Type


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Enumeration Types

An enumeration type declaration, defines two categories:1. User Defined Enumeration Types2. Predefined Enumeration Types

User defined data types are frequently used to enhance readabilitywhen dealing with so called state machines, i.e. modules that behavedifferently, depending on the state of internal storage elements.

Instead of fixed bit patterns, the symbolic names of the data type valuesare used which will be mapped to a bit level representation automaticallyduring synthesis.

These enhances readability in the code.


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User Defined Enumeration Types

These have a set of user defined values, consisting of identifiers andcharacter literals.

The order in which, values appear in the enumeration type declaration,defines their ordering, i.e., when using relational operators, a value isalways les than a value that appears to its right in the order.

The position of the leftmost element is 0.The values of an enumeration type are called ENUMERATION

LITERALS .If the same literal is used in two different enumeration type declarations,

the literal is said to be Overloaded .

type MVL is (U , 0 , 1 , Z ); type TWO_STATE is (0 , 1 ); signal CONTROL_A : MVL; signal CONTROL_B :TWO_STATE


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User Defined Enumeration Types


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Predefined Enumeration Types

The Predefined enumeration types are:

1. CHARACTER2. BIT3. BOOLEAN4. SEVERITY_LEVEL5. FILE_OPEN_KIND6. FILE_OPEN_STATUS7. STD_ULOGIC


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CHARACTER TypeIt constitutes the 191 characters of the IS eight-bit coded character set.These values are called character literals , and are always written

between two single quotes ( ).

Examples

A - 3

variable VAL: character := $ ;


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SEVERITY_LEVEL Type

It has the values:

NOTE, WARNING, ERROR and FAILURE.

It is typically used in assertion statements.

FILE OPEN KIND d FILE OPEN STATUS


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FILE_OPEN_KIND and FILE_OPEN_STATUSTypes

FILE_OPEN_KIND has the following values:

READ_MODE, WRITE_MODE and APPEND_MODE

FILE_OPEN_STATUS has the following values:

OPEN_OK, STATUS_ERROR, NAME_ERROR and MODE_ERROR


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Integer Scalar Type

The range of the INTEGER type is implementation dependent, but must atleast cover the range from

-(231 1) to +(2 31 1)

Values belonging to an integer type are called integer literals .Literal 6E2 refers to 6*10 2


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Real(floating point) Scalar Type

Floating point literals are values of a floating point type.Example : 16.26, 0.6, 0.002These differ from integer literals by the presence of the dot (.)

character.Thus, 0 is an integer literal, while 0.0 is a floating point literal.These can also be expressed in an exponential form.

Example : 62.3E-2 (E represents power of 10, and value must be aninteger)It provides at least six decimal digits of precision.


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Physical Scalar Types

It contains values, that represent measurement of some physical quantity, liketime, length, voltage, or current.

Values of this type are expressed as integer multiples of a base unit.

type CURRENT is range 0 to 1E9unitsnA;uA = 1000 nA;mA = 1000 uA;

Amp = 1000 mA;End units;

CURRENT is defined to be a physical type, that contains values from 0 nA to10 9 nA.

The base unit is nano-ampere, while all others are derived units.The position number of a value is the number of base units represented by that

value, i.e.; 2uA has a position of 2000.


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Physical Scalar Types

The range of values may include negative values.Values of a physical type are called physical literals .The only predefined physical type is TIME .Its range is also implementation dependent, must at least being

-(231 1) to +(2 31 1)Predefined physical subtype DELAY_LENGTH is also present, which

represents non negative time values.Available time units : fs, ps, ns, us, ms, sec, min, hr


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Array TypesArrays are a collection of a number of values of a single data type.type ADDRESS_WORD is array (0 to 63) of BIT;

Elements of an array can be accessed by specifying the index values intothe array.

E.g. signal ADDRESS_BUS : ADDRESS_WORD; ADDRESS_BUS(26) refers to the 27 th element of ADDRESS_BUS array

object.


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Dimensional Array TypesThe language allows for an arbitrary number of dimensions to be associated

with an array.

An object X(5,2) declared of multi type, refers to the value of the element at the2nd column and 5 th row of 2-d object.

Also, it can be in the form of array of an array.

The index set can be of any type.


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Unconstrained Array

The array types can be unconstrained also.In this case, the number of elements in the array is not specified in the type

declaration, instead, an object declaration for an object of that type declares thenumber of elements of the array.

The symbol is called BOX .

type STACK_TYPE is array (INTEGER range ) of ADDRESS_WORD;subtype STACK is STACK_TYPE (0 to 63);subtype STACK_ONE is STACK_TYPE (0 to 5);

There are two predefined one-dimensional unconstrained array types in thelanguage:1. STRING (array of characters) (string literals are enclosed within double quotes)2. BIT_VECTOR (array of bits)

variable MESSAGE : STRING (1 to 17) := Hello, VHDL world; VHDL does not allows a type, that is an unconstrained array of anunconstrained array.


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Unconstrained Array Contd..

There are two one-dimensional unconstrained array types defined in thepackage STD_LOGIC_1164:

1. type STD_ULOGIC_VECTOR is array (NATURAL range) of STD_ULOGIC;

2. type STD_LOGIC_VECTOR is array (NATURAL range ) of STD_LOGIC;

Examples

signal RASTER_LINE : STD_LOGIC_VECTOR (0 to 8);


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Assignment to an Array

The language allows an array object to be assigned to another array object of thesame type using a signal assignment statement.

The assignment can be made to an entire array, or to an element of an array, or to aslice of an array.

Examples

variable OP_CODES : BIT_VECTOR (1 to 5);OP_CODES := 01001; -- A string literal is assignedOP_CODES := (0 , 1 , 0 , 0 , 1 ); -- Positional association is used

OP_CODES := (2=> 1 ,5=> 1 ,others => 0 ); -- Named AssociationOP_CODES := (others => 0 ); OP_CODES(4) := 1 ; -- Assign to an element of an arrayDECODER_VALUE := DECODER; -- An entire array is assigned

ADDRESS_BUS(1 to 3)


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Record Types

It represents a collection of values, that may belong to different types.An object of a record type is composed of elements of same or different

types.

Three choices exist for value assignments:

Assign one record to another (' STUDENT_2


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Record Types Contd..


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Access Types

Values belonging to an access type are pointers to a dynamically allocatedobject of some other type.

These are similar to pointers in Pascal and C languages.

type PTR is access MODULE;type FIFO is array (0 to 63, 0 to 7) of bit;type FIFO_PTR is access FIFO;

PTR is an access type, whose values are addresses, that points to objects of type MODULE.

Only variables can be an access type; that is, it is not permissible for asignal to be utilized as an access type.

Every access type may also have the value null, which means that, it doesnot point to any object, i.e. null is the default value unless otherwise specified)

l


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Incomplete Types

It is possible to have an access type, that points to an object, which haselements, that are also access types.

This can lead to mutually dependent or recursive access types.Since a type must be declared before it is used, this can be done using the

incomplete types.type type_name ;

Once an incomplete type has been declared, the type_name can now beused in any mutually dependent or recursive access type.

However, a corresponding full type declaration, must follow later.type COMP;type COMP_PTR is access COMP;

Full Type Declarations:type COMP isrecordCOMP_NAME : STRING(1 to 10);end record;

Fil T


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File Types

Objects of file types, represent files in the host environment.They provide a mechanism, by which, a VHDL design, communicates with the

host environment.

type file-type-name is file of type_name;

The type name is the type of values contained in the file.

type VECTORS is file of BIT_VECTOR;type NAMES is file of STRING;

A file can be opened, closed, read, written to, or tested for an end of filecondition by using special procedures and functions, that are implicitly declared for every file type.

Function ENDFILE, and procedures like READLINE, READ, WRITELINE, andWRITE are predefined in the package TEXTIO.

d d


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VHDL Standard Data Types

A ib


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Attributes

Data can be obtained about VHDL objects such as types, arrays and signals.

object attribute

Example: consider the implementation of a signal

What types of information about this signal are useful?Occurrence of an eventElapsed time since last eventPrevious value, i.e., prior to the last event

Cl f A ib


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Classes of Attributes

Value attributesReturns a constant value

Function attributesInvokes a function that returns a value

Signal attributesCreates a new signal

Type AttributesSupports queries about the type of VHDL objects

Range attributesReturns a range


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F i A ib


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Function Attributes

Use of attributes invokes a function call which returns a value

F i A ib C


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Function Attributes Cont.

Function array attributes

type mem_array is array(0 to 7) of bit_vector(31 downto 0)mem_array left = 0 mem_array right = 7 mem_array length = 8 (value kind attribute)

R Att ib t


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Range Attributes

Si l Att ib t


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Signal Attributes

Creates a new implicit signal

Si l Att ib t E l


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Signal Attributes: Example

Ali


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Aliases

T C i


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Type ConversionsSince VHDL is a strongly typed language one cannot assign a value of one data

type to a signal of a different data type.In general, it is preferred to the same data types for the signals in a design,

such as std_logic (instead of a mix of std_logic and bit types).Sometimes one cannot avoid using different types.

To allow assigning data between objects of different types, one needs to convertone type to the other.Fortunately there are functions available in several packages in the ieee library,

such as the std_logic_1164 and the std_logic_arith packages. As an example, the std_logic_1164 package allows the following conversions:


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Operators


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Operators

PRECEDENCE

Operators in the same category, have the same precedence, and evaluation isdone from left to right.

Parenthesis may be used to override the left to right evaluation.

Logical Operators


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Logical Operators

The logic operators (and, or, nand, nor, xor and xnor) are defined for the bit, Boolean, std_logic and std_ulogic types and their vectors.

They are used to define Boolean logic expression or to perform bit-per-bitoperations on arrays of bits.

They give a result of the same type as the operand (Bit or Boolean).These operators can be applied to signals, variables and constants.Notice that the nand and nor operators are not associative. One should use

parentheses in a sequence of nand or nor operators to prevent a syntax error:

X nand Y nand Z will give a syntax error and should be written as (X nand Y) nand Z

Relational Operators


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Relational Operators

The relational operators test the relative values of two scalar types andgive as result a Boolean output of TRUE or FALSE.

For discrete array types, the comparison is done on an element-per-elementbasis, starting from the left towards the right.

Examples


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Examples


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Example


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Example

The operand is on the left of the operator and the number (integer) of shifts is on the rightside of the operator. As an example,

variable NUM1:bit_vector := 10010110 ;

NUM1 srl 2;

will result in the number 00100101 .

When a negative integer is given, the opposite action occurs, i.e. a shift to the left will be ashift to the right. As an example

NUM1 srl 2 would be equivalent to NUM1 sll 2 and give the result 01011000 .

Addition Operators


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Addition Operators

The addition operators are used to perform arithmetic operation (addition andsubtraction) on operands of any numeric type.

The concatenation (&) operator is used to concatenate two vectors together to makea longer one.

In order to use these operators one has to specify the ieee.std_logic_unsigned.all or std_logic_arith package in addition to the ieee.std_logic_1164 package.

Example


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Example

An example of concatenation is the grouping of signals into a single bus [4].

signal MYBUS :std_logic_vector (15 downto 0);signal STATUS :std_logic_vector (2 downto 0);signal RW, CS1, CS2 :std_logic;signal MDATA :std_logic_vector ( 0 to 9);MYBUS


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Unary Operators

The unary operators + and - are used to specify the sign of a numeric type.

Multiplying Operators


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Multiplying Operators

The multiplying operators are used to perform mathematical functions onnumeric types (integer or floating point).

Multiplication Operator


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Multiplication Operator

The multiplication operator is also defined when one of the operands is a physicaltype and the other an integer or real type.

The remainder (rem) and modulus (mod) are defined as follows:

A rem B = A (A/B)*B (in which A/B in an integer) A mod B = A B * N (in which N is an integer)

The result of the rem operator has the sign of its first operand while the result of the mod operators has the sign of the second operand.


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Module IV Modelling Delays


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Inertial Delays : Example


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Inertial Delays : Example

Transport Delays: Example


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Transport Delays: Example

Delta Delays : Example


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Delta Delays : Example

Delta Delays: Behavior


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Delta Delays: Behavior

Delay Models : Summary


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Delay Models : Summary

Delay models Inertial For devices with inertia such as gates VHDL 1993 supports pulse rejection widths

Transport Ensures propagation of all events Typically used to model elements such as wires

Delta Automatically inserted to ensure functionalcorrectness of codeblocks that do not specify timing Enforces the data dependencies specified in thecode

Summary


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Summary

Primary unit of abstraction is a design entity Design units include

Primary design units entity, configuration, package declaration

Secondary design units architecture, package body Concurrent signal assignment statements

Simple, selected, conditional Can be coalesced to form models of combinational circuits


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Module V Dataflow Style of

Modelling

Design Description


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Design Description A design is described using one or more concurrent statements in an

architecture body (all statements within an architecture are executedconcurrently)

The execution of a concurrent statement is based on events onsignals in its input list, i.e. ,at the same time.

The order of concurrent statement within an architecture body is notimportant.

Each concurrent statement will synthesize to a block of logic.

The following concurrent statements are available in VHDL:Concurrent Signal Assignment StatementConcurrent Procedure Call StatementConcurrent Assertion StatementComponent Instantiation StatementGenerate StatementProcess StatementBlock Statement

Dataflow Style of Modelling


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Dataflow Style of Modelling

A Data flow model, specifies the functionality of the entity, withoutexplicitly specifying its structure.

This functionality shows the flow of information through the entity,

which is expressed primarily using concurrent signal assignmentsstatements and block statements.

The structure of the entity is not explicitly specified in this modelingstyle, but it can be implicitly deduced.

Simple/Concurrent Signal


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Assignment

Simple Signal Assignment


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StatementA statement is executed when an event(change of value) takes place on any

signal in the RHS of an expression.The signals in the expression, forms the SENSITIVITY LIST for the signal

assignment statement.Order of statement execution follows propagation of events in the circuitTextual order does not imply execution order

An architecture body can have any number of concurrent signal assignmentstatements.

The after clause, models the delay of the logic represented by theexpression.

Each concurrent signal assignment statement, creates a driver for the signalbeing assigned.

Implementation of Signals


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Implementation of Signals (cont.)


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In the absence of initialization, default values are determinedby signal type

Waveform elements describe time-value pairs Transact ions are internal representations of signal value

assignmentsEvents correspond to new signal valuesA transaction may lead to the same signal value



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Driver is set of future signal values: current signal value is provided by thetransaction at the head of the list

We can specify multiple waveform elements in a single assignmentstatement by specifying multiple future values for a signal

Example: Waveform


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Generation

Multiple waveform elements can be specified in a single signal assignmentstatement

Describe the signal transitions at future point in timeEach transition is specified as a waveform element

Issue of Multiple Drivers with SignalA i S


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Assignment Statements

When there are more than one assignment to the same signal, the signal hasmore than one driver; and a mechanism is therefore needed to compute theeffective value of the signal.

Unresolved Data Type : Only One Driver

Resolved Data Type : Possibly several drivers per signal

Resolution conflicts are detected at run time and not during compilation.



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The basic structure of a signal assignment statement

s ign al


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Shared Signals

Resolved Signals


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Resolved Signals

Resolution Function Behavior


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Physical operationIf any of the control signals activate the switch, the output signal is

pulled low

VHDL modelIf any of the drivers attempt to drive the signal low (value at the head of

the driver), the resolution functions returns a value of 0Resolution function is invoked when any driver attempts to drive the

output signal

Resolved Types: std logic


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Resolved Types: std_logic


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Example


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p

Multiple components driving a shared error signal

Signal value is the logical OR of the driver values


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Conditional SignalA i


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AssignmentThe signal assignment can be extended by the specification of conditions.The condition is appended after the new value and is introduced by the

keyword ' when '.The keyword ' else ' is also strictly necessary (mandatory) after each

condition as an unconditional signal assignment has to be present.It selects different values for the target signal, based on the specified

condition.Equivalent to if else statement

Condition is a Boolean expression.

Whenever an event occurs on a signal used ineither any of the waveform expressions(valueexpression is a waveform element), or any of theconditions, the conditional signal assignmentstatement is executed by evaluating the conditionsone at a time.

Conditional SignalA i


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Assignment

For the first true condition found, the corresponding value (or values) of thewaveform is scheduled to be assigned to the target signal.

Example

Z


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Assignment

Unaffected Value


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It is possible to assign a value of UNAFFECTEDto a signal in a concurrent signal assignmentstatement.

Such an assignment causes no change to thedriver for the target signal; i.e. the target driver retains its previous/old value.

Selected Signal AssignmentSt t t


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StatementThe behavior of the so called selected signal assignment is similar to the

case statement.It selects different values for a target signal based on the value of a

select expression. Whenever an event occurs on a signal in theselect expression, or any signal used in any of the waveform expressions, the statement isexecuted.

Based on the value of the select expressionthat matches the choice value specified, thevalue of the corresponding waveform is

scheduled to be assigned to the target signal.The choices are not evaluated in sequence. All possible values of the select expression

must be covered by the choices exactly once.Values not covered explicitly, may be covered

by an others choice, which covers all such

values.

Selected Signal AssignmentSt t t


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Statement

BLOCK Statement


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It can be used for three major purposes:1. To disable signal drivers by using guards.2. To limit the scope of declarations, including signal declarations.3. To represent a portion of the design (modularity)

Syntax:Block_label:block [(guard_expression)][is]

[block_header][block declarations]

begin

concurrent statementsend block [Block_label];

The block_header if present, describes the interface of the blockstatement to its environment.

Any declarations appearing within the block are visible only within

the block.

BLOCK Statement Cont..


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Any number of concurrent statements can appear within a block,possibly none.Block statements can be nested.The Block_label at the beginning is necessary, however, at the end, is

optional, if present, however, must be the same as the one used at thebeginning.

If a GUARD expression appears in a block statement, there is an implicitsignal called GUARD of type BOOLEAN declared within the block.

ExampleBLAB : block(HANDLE)

beginTOG


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Statement An assertion statement is a concurrent statement, by virtue of its

place of appearance within the model.If it appears inside a process, it is a sequential assertion statement,

and if it appears outside a process, it is a concurrent assertionstatement.

Whenever an event occurs on a signal in the boolean expression of the assertion statement, the statement is executed.

Exampleentity sr isport (s,r:in std_lgic;q,notq:out std_logic);end sr;

architecture sr_assert of sr isbeginassert not (s=0 and r=0 );report Not valid inputs severity error;

end sr assert;


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Module VI

Behavioral Style ofModelling

Behavioural style ofModelling


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ModellingIt specifies the behavior of an entity as a set of statements that are executed

SEQUENTIALLY in the specified order.The behavior of the entity is expressed using sequentially executed, procedural

code, which is very similar in syntax and semantics to that of a high level

programming language like C or Pascal.

A PROCESS STATEMENT IS THE PRIMARY MECHANISM USED TO MODELTHE BEHAVIOR OF AN ENTITY.

A process statement itself is a concurrent statement, which can appear in thearchitecture body, and the sequential statements can be specified inside theprocess statement.


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Types of PROCESSStatements


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Statements1. Variable Assignment Statement2. Sequential Signal Assignment Statement3. WAIT Statement4. IF Statement

5. CASE Statement6. NULL Statement7. LOOP Statementa) For iterationb) While iterationc) No iteration

8. EXIT Statement9. NEXT Statement10.Sequential Assertion Statement11.Report Statement12.Procedure Call Statement13.Return Statement

Variable AssignmentStatement


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StatementVariables can be declared and used inside a process statement.

A variable is assigned a value, using this statement.

Assign the value of an expression to a target variable.

[ label: ] target := expression ;

A := -B + C * D / E mod F rem G abs H;Sig := Sa and Sb or Sc nand Sd nor Se xor Sf xnor Sg;

The expression is evaluate when the statement is executed, and thecomputed value is assigned to the variable object instantaneously, i.e.;at the current simulation time.

A variable can also be declared outside of a process, or a subprogram.Such a variable can be read and updated by more than one processand are called SHARED VARIABLES.


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WAIT Statement


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A process may be suspended by means of a sensitivity list, i.e.; when aprocess has a sensitivity list, it always suspends after executing the lastsequential statement in the process.WAIT Statement provides an ALTERNATE way to suspend theexecution of a process.There are three basic forms of wait statement:1. wait on sensitivity list;2. wait until boolean_expression;3. wait for time_expression;

Wait on sensitivity list until boolean_expression for time_expression;

[ label: ] wait [ sensitivity clause ] [ condition clause ] ;

wait for 10 ns; -- timeout clause, specific time delay.wait until clk='1'; -- condition clause, Boolean conditionwait until A>B and S1 or S2; -- condition clause, Boolean condition

wait on sig1 sig2; -- sensitivity clause any event on any

WAIT Statement Cont..


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It is possible for a process not to have an explicit sensitiity list.In such a case, the process may have one or more wait statements.It must have at least one wait statement, otherwise, the process will never get suspended, and would remain in an infinite loop during the simulation.

It is an ERROR, if both the sensitivity list and a wait statement arepresent within a process.The presence of a sensitivity list in a process, implieas the presence of animplicit wait on sensitivity list statement as the last statement in theprocess.

wait for 0ns;Implies wait for one delta cycle.It is useful when one wants the process to e delayed so that, deltadelayed signal assignments within a process can take effect.

IF Statement


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It selects a sequence of statements for execution, based on the value of acondition.The condition can be any expression, that evaluates to a Boolean value.

IF Statement Cont..


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It is executed by checking each condition sequentially, until the first truecondition is found; then the set of sequential statements associated withthis condition is executed.

The if statement can have zero or more elsif clauses, and an optional

else clause.

CASE Statement


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It selects one of the branches for execution based on the value of the expression.Choices may be expressed as:a) single valuesb) Range of valuesc) Using others clause

All possible values of the expression must be covered in the casestatement exactly once.

The others clause can be used as a choice to cover the catch allvalues, and, if present, must be the last branch in the casestatement.


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NULL Statement


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It is a sequential statement, that does not cause any action to take place.Execution continues with the next statement.It is useful in an if statement or in a case statement, where, for certainconditions, it may be useful or necessary to explicitly specify that no actionis to be performed.

Example:processbeginIf STROBE =0 then MARK_DET


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It is used to iterate through a set of sequential statements.

[loop label:] iteration scheme loopsequential statementsend loop [loop label];

There are three types of iteration schemes:1. FOR Iteration Scheme2. WHILE Iteration Scheme3. No Iteration Scheme

All kind of schemes may have exit and next statements. Loops operate in the usual way, i.e. they are used to execute the same some

VHDL code a couple of times.Loop labels may be used to enhance readability, especially when loops are

nested or the code block executed within the loop is rather long.The loop variable is the only object in VHDL which is implicitly defined.The loop variable can not be declared externally and is only visible within the

loop

FOR Iteration Scheme


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If a for loop is to be synthesized, the range of the loop variable must notdepend on signal or variable values (i.e., it has to be locally static).

WHILE Iteration Scheme


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If a variable number of cycles is needed, the while statement will have to beused.While loops are executed as long as CONDITION evaluates to a 'true' value.Therefore this construct is usually not synthesizable.

No Iteration Scheme


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In this, all statements in the loop body are repeatedly executed, untilsome other action causes the loop to exit.This can be achieved by using an exit statement, a next statement, or areturn statement.

SUM:=1;J:=0;L2: loopJ:=J+2;

SUM:=SUM*10;exit when SUM > 100;end loop L2;

EXIT Statement


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It is a sequential statement, that can be used only inside a loop.It causes execution to jump out of the innermost loop, or the loop whoselabel is specified.If no loop label is specified, the innermost loop is exited.If the when clause is used, the specified loop is exited only if, the givencondition is true; otherwise, execution continues with the next statement.

[ label: ] exit [ label2 ] [ when condition ] ;

loopwait on A,B;exit when A=B;end loop;

NEXT Statement


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It is a sequential statement, that can be used only inside a loop.It results in skipping the remaining statements in the current iteration of thespecified loop; execution resumes with the first statement in the next iterationof this loop, if one exists.If n loop label is specified, the innermost loop is assumed.

[ label: ] next [ label2 ] [ when condition ] ;

next ;next outer_loop;next when A>B;next this_loop when C=D or done; -- done is a Boolean variable


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Report Statement


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It can be used to display a message.It is similar to the assertion statement, but without the assertion check.When a report statement is executed, it causes the specified string to beprinted and the severity level to be reported to the simulator for proper action.

Procedure Call Statement


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The specified procedure is called, whenever an event occurs on an inputparameter.

PROPAGATE_DELAY ( in_sig=>q, out_sig => prop_q, delay => dy);

Return Statement


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Causes the subprogram, that contains the return statement to terminate.

Multiple Processes


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Since a process statement is a concurrent statement, it is possible to have morethan one process within an architecture body.Processes within an architecture body communicate with each other usingsignals that are visible to all the processes.Variables declared within a process, cannot be used to pass information

between processes, because their scope is limited to be within a process.Shared variables, however, could be used.

Concurrent Processes: FullAdder


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Adder


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Module VII

Structural Style ofModelling

Structural Style ofModelling


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Modelling An entity is modeled as a set of components connected by signals, i.e.;as a net list.The behavior of the entity is not explicitly apparent from its model.

THE COMPONENT INSTANTIATION STATEMENT IS THE PRIMARYMECHANISM USED FOR DESCRIBING SUCH A MODEL OF ANENTITY.

The component instantiation statements are concurrent statements, andtheir order of appearance in the architecture body is therefore notimportant.

A component can, in general, be instantiated any number of times.However, each instantiation must have a unique component label.

A purely structural architecture does not describe any functionality andcontains just a list of components, their instantiation and the definition of their interconnections.

Component Declaration


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A component instantiated in a structural description must first be declaredusing a component declaration, in the declaration part of the architecturebody.

A component declaration declares the name and the interface of acomponent.

The interface specifies the mode and the type of ports.

component component_name [is][port (list of interface ports);]

end component [component_name];

The component_name may or may not refer to the name of an entity alreadyexisting in a library.If it does not, it must be explicitly bound to an entity; otherwise, the modelcannot be simulated.The binding information can be specified using a configuration.

Component Instantiation


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A component instantiation statement defines a subcomponent of the entity inwhich it appears.It associates the signals in the entity with the ports of that subcomponent.

component_label : component_name [port map (association_list)];

The component_label can be any legal identifier, and can be considered as thename of the instance.The component_name must be the name of the component declared earlier using a component declaration.The association list, associates signals in the entity, called ACTUALS, with the

ports of a component, called FORMALS. An actual may be a signal or an expression or it can be the keyword open, toindicate a port that is not connected.There are two ways to perform the association of formals with the actuals:1. Positional Association2. Named Association

Positional Association


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In positional association, the association list is of the form:

Actual1, actual2, actual3,,actualn Each actual in the component instantiation is mapped by position with each portin the component declaration. That is, the first port in the component declarationcorresponds to the first actual in the component instantiation, the second withthe second, and so on.The ordering of actuals is therefore important.If a port in a component instantiation is not connected to any signal, thekeyword open can be used to signify that the port is not connected.

N3:NAND2 port map (S1, open, S3);The second input port of the NAND2 component is not connected to any signal.

An input port may be left openonly if its declaration specifies an initial value.

Named Association


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In named association, the ordering of the association is not important, since,the mapping between the actuals and the formals is explicitly specified.The port names from the component declaration, also called "formals", areassociated with an arrow ' => ' with the signals of the entity ("actuals").

entity FULLADDER isport (A,B, CARRY_IN: in bit;

SUM, CARRY: out bit);end FULLADDER;

architecture STRUCT of FULLADDER is

component HALFADDERport (A, B : in bit;

SUM, CARRY : out bit);end component;

. . .

signal W SUM W CARRY1 W CARRY2 : bit;

Modeling Structure


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Structured Modeling


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State Machines


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Basic components Combinational component: outputfunction and next state

function Sequential component Natural process -based implementation

Example: State Machine


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Example: Output and NextState Functions


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State u ct o s

Example: Clock Process


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Generics


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library IEEE;use IEEE.std_logic_1164.all;entity xor2 isgeneric (gate_delay : Time:= 2 ns);port(In1, In2 : in std_logic;z : out std_logic);end entity xor2;architecture behavioral of xor2 isbeginz


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generic (gate_delay: Time);

port (a, b : in std_logic;c : out std_logic);end component;component and2generic (gate_delay: Time);port (a, b : in std_logic;

c : out std_logic);end component;beginEX1: xor2 generic map (gate_delay => 6ns)port map(a => a, b => b, c => sum);

A1: and2 generic map (gate_delay => 3ns)port map(a=> a, b=> b, c=> carry);end architecture generic_delay;

Parameter al es are passed thro gh the hierarch

Example: Full Adder


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Example: Full Adder


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Precedence of GenericDeclarations


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Generics: Properties


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Generics are constant objects and canonly be read The values of generics must be known atcompile time They are a part of the interfacespecification but do not have aphysical interpretation Use of generics is not limited to delaylike parameters and are in fact a very powerful structuringmechanism

Example: N-Input Gate


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Example: Using the Generic N-Input OR Gate architecture structural of full_adder iscomponent generic_or

generic (n: positive);


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g ( p );port (in1 : in std_logic_vector ((n-1)downto 0);z : out std_logic);end component;...... -- remainder of the declarative regionfrom earlier example...beginH1: half_adder port map (a => In1, b =>In2, sum=>s1, carry=>s3);H2:half_adder port map (a => s1, b =>c_in, sum =>sum, carry => s2);O1: generic_or generic map (n => 2)port map (a => s2, b => s3, c => c_out);end structural; Full adder model can be modified to use the generic

OR gate model via the generic map () construct Analogy with macros

Example: N-bit Register


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Implementing Global Set/Reset inVHDL


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The Generate Statement What if we need to instantiate a largenumber of components in


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a regular pattern? Need conciseness of description Iteration construct for instantiatingcomponents! The generate statement

A parameterized approach to describingthe regular interconnection of componentsa: for i in 1 to 6 generatea1: one_bit generic map (gate_delay)port map(in1=>in1(i), in2=> in2(i),cin=>carry_vector(i-1),result=>result(i),cout=>carry_vector(i),opcode=>opcode );end generate;

The Generate Statement: Example


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Instantiating an register

entity dregister isport ( d : in std_logic_vector(7 downto0);q : out std_logic_vector(7 downto 0);clk : in std_logic);end entity dregisters

architecture behavioral of dregister isbegind: for i in dreg range generate reg: dff port map( (d=>d(i), q=>q(i),clk=>clk;end generate;

end architecture register;

Instantiating interconnected components Declare local signals used for theinterconnect

The Generate Statement: Example


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Using the Generate Statement


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Identify components with regular interconnect Declare local arrays of signals for theregular interconnections Write the generate statement

Analogy with loops and multidimensionalarrays

Beware of unconnected signals! Instantiate remaining components of thedesign

Configurations


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A design entity can have multiplealternativearchitectures A configuration specifies the architecturethat is to

be used to implement a design entity

Component Binding


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We are concerned with configuring thearchitecture and not the entity Enhances sharing of designs: simplychange the configuration

Default Binding Rules architecture structural of serial adder is


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architecture structural of serial_adder is

component comb isport (a, b, c_in : in std_logic;z, carry : out std_logic);end component comb;component dff isport (clk, reset, d :in std_logic;

q, qbar : out std_logic);end component dff;signal s1, s2 : std_logic;beginC1: comb port map (a => a, b => b, c_in=> s1, z =>z, carry => s2);

D1: dff port map(clk => clk, reset Search for entity with the same component name If multiple such entities exist, bind the last compiled architecture for that entity How do we get more control over binding?

Configuration Specification


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We can specify any binding where portsand arguments match

Configuration Specification


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Short form where applicable for all: half_adder use entityWORK.half_adder (behavioral); Not constrained by the name space Delayed binding when a specification is

not present Will be available at a later step Analogous to unresolved symbolreferences duringcompilation of traditional programs

Configuration Declaration


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Written as a separate design unit Can be written to span a design hierarchy Use of the for all clause

Subprograms, Packages, andLibraries


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Essentials of Functions function rising_edge (signal clock:


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g_ g ( g

std_logic) returnboolean is----declarative region: declare variables local to thefunction

--begin-- body --return (expression)end rising_edge;

Formal parameters and mode Default mode is of type in Functions cannot modify parameters

Pure functions vs. impure functions Latter occur because of visibility into signals that are not parameters Function variables initialized on each call

Essentials of Functions (cont.) function rising_edge (signal clock:


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std_logic) returnboolean is----declarative region: declare variables local to thefunction--begin-- body --return (expression)end rising_edge;

Types of formals and actuals must match except for formals which are constants (default) Formals which are constant match actuals which arevariable, constant or signal Wait statements are not permitted in a function!

And therefore not in any procedure called by a functions

Placement of Functions


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Function: Example


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Function: Example function to_bitvector (svalue :std_logic_vector) return


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g )

bit_vector isvariable outvalue : bit_vector (svalue length -1 downto 0);beginfor i in svalue range loop -- sc an all e lem ents o f the ar ray

case svalue (i) iswhen 0 => outvalue (i) := 0 ; when 1 => outvalue (i) := 1 ; when others => outvalue (i) := 0 ; end case;end loop;

return outvalue;end to_bitvector

A common use of functions: type conversion Use of attributes for flexible function definitions

Data size is determined at the time of the call Browse the vendor supplied packages for many examples

Summary: Essentials of Functions


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Placement of functions Visibility Formal parameters

Actuals can have widths bound at the call

time Check the source listings of packages for examplesof many different functions

Essentials of Procedures procedure read v1d (variable f: in text;


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p ocedu e ead_v d (va ab e : te t;

v :out std_logic_vector)--declarative region: declare variables local to the procedure--begin-- body

--end read_v1d;

Parameters may be of mode in (read only) and out

(write only) Default class of input parameters is constant Default class of output parameters is variable Variables declared within procedure are initialized on each call

Procedures: Placement


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Placement of Procedures


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Procedures and Signals procedure mread (address : instd logic vector (2 downto 0);


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std_logic_vector (2 downto 0);

signal R : out std_logic;signal S : in std_logic;signal ADDR : out std_logic_vector (2downto 0);signal data : out std_logic_vector (31downto 0)) isbegin

ADDR


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std_logic_vector (2 downto 0);

signal R : out std_logic;signal S : in std_logic;signal ADDR : out std_logic_vector (2downto 0);signal data : out std_logic_vector (31downto 0)) isbegin

ADDR


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Concurrent Procedure Calls


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Variables cannot be passed into aconcurrent procedure call Explicit vs. positional association of formal and actualparameters

Equivalent Sequential ProcedureCall


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Subprogram Overloading


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Hardware components differ in number of inputs and the typeof input signals

Model each component by a distinctprocedure Procedure naming becomes tedious



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Consider the following procedures for the previouscomponentsdff_bit (clk, d, q, qbar)asynch_dff_bit (clk, d,q,qbar,reset,clear)dff_std (clk,d,q,qbar)asynch_dff_std (clk, d,q,qbar,reset,clear) All of the previous components can use the same name subprogram overloading The proper procedure can be determined based on the arguments of the call

Example

function * (arg1, arg2: std_logic_vector) returnstd_logic_vector;function + (arg1, arg2 :signed) return signed; -- the following function is from std_logic_arith.vhd



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VHDL is a strongly typed language Overloading is a convenient means for handling user definedtypes We need a structuring mechanism tokeep track of our overloaded implementations

Essentials of Packages Package Declaration

D l ti f th f ti d


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Declaration of the functions, procedures,and types that areavailable in the package

Serves as a package interface Only declared contents are visible for external use

Note the behavior of the use clause Package body Implementation of the functions andprocedures declared in thepackage header

Instantiation of constants provided in the

package header

Example: Package Headerstd_logic_1164

package std_logic_1164 is


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p g g

type std_ulogic is (U , --Unitialized X ,-- Forcing Unknown0 , -- Forcing 0 1 , -- Forcing 1Z ,-- High ImpedanceW ,-- Weak UnknownL ,-- Weak 0 H ,-- Weak 1- -- Dont care );type std_ulogic_vector is array (natural range ) of std_ulogic;function resolved (s : std_ulogic_vector) return std_ulogic;subtype std_logic is resolved std_ulogic;type std_logic_vector is array (natural range ) of std_logic;function and (l, r : std_logic_vector) return std_logic_vector; --..end package std_logic_1164;

Example: Package Body


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package body my_package is---- type definitions, functions, and

procedures--end my_package;

Packages are typically compiled into libraries New types must have associated definitions for operations such as logical operations (e.g., and, or)and arithmetic operations (e.g., +, *) Examine the package std_logic_1164 stored in library IEEE

Essentials of Libraries


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Design units are analyzed (compiled) andplaced in libraries

Logical library names map to physicaldirectories Libraries STD and WORK are implicitlydeclared

Libraries


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Packages


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Packages are repositories for type definitions, procedures, and Functions

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