FBS-GAM02P-C-PSE - freebirdsemi.com · The FBS-GAM02P-C-PSE is intended to drive external Freebird eGaN ® HEMT power switch transistors rated up to 100V (refer to Table 1, Page 11

FBS-GAM02P-C-PSE Rev Q4 1 www.freebirdsemi.com May 24, 2017

FBS-GAM02P-C-PSE 50V Rad Tolerant High Speed Multifunction Power HEMT Driver

d l h l

Features 50V Fully De-Rated Operation internally utilizing

100V Rated eGaN® HEMT technology Independent Low and High Side eGaN® HEMT

Gate Drivers Four Possible Configurations:

- Single Low Side Gate Driver - Single High Side Gate Driver - Independent High and Low Side Gate

Drivers - Half-Bridge Gate Drivers With Shoot-

Through Protection Internal Shoot-Through Protection Internal Power Good Circuitry High Speed Switching Capability: 1.0+MHz Rugged Compact Molded SMT Package “Pillar” I/O Pads Drives External eGaN® Switching Elements No Bipolar Technology Commercially Screened Development Vehicle for:

• FBS-GAM02P-R-PSE • FBS-GAM02C-R-PSE

Description Freebird Semiconductor’s FBS-GAM02P-C-PSE Series Radiation Tolerant High Speed Multifunction Power HEMT Gate Driver Module incorporates eGaN® HEMTs with intended end use design within commercial satellite space environments. These development modules contain two independent high speed gate drive circuits (consisting entirely of eGaN® switching elements), shoot-through prevention logic (for a Half-Bridge configuration) and +5V gate drive bias “power good” monitoring circuitry in an innovative, space-efficient, 18 pin SMT molded epoxy package. The FBS-GAM02P-C-PSE is intended to drive external Freebird eGaN® HEMT power switch transistors rated up to 100V (refer to Table 1, Page 11 for device options). Application

Power Switches/Actuators Single and Multi-Phase Motor Phase Drivers Commercial Satellite EPS & Avionics High Speed DC-DC Conversion

FBS-GAM02P-C-PSE Functional Block Diagram

Level Shift

(13) BGATE

(14) PGND

Shoot-Thru/ Disable Logic

VBIAS (4)

Power Good

Detection And Logic

PG (5)

UVA/*SD (6)

TIN (2) 1KΩ

BIN (1) 1KΩ

BSTP

(16)

BC

ON

(15)

TST

P (1

7)

TCO

N (1

8)

H/S Gate Driver

H/S Gate Driver

SD (7)

R LGND (3)

(Pin 9 Is No Connect)

(11) TGATE

(12) SN

(10) VBST

(9) SNS

http://www.freebirdsemi.com/

FBS-GAM02P-C-PSE

©2017 Freebird Semiconductor Corporation Page 2 of 22 www.freebirdsemi.com


FBS-GAM02P-C-PSE


FBS-GAM02P-C-PSE Configuration and Pin Assignments

FBS-GAM02P-C-PSE Configuration and Pin Assignment Table

Pin # Pin Name Input/Output Pin Function 1 BIN I Low Side Switch Logic Input 2 TIN I High Side Switch Logic Input 3 LGND -- Logic Ground, 0V (Low Current) 4 VBIAS I +5V Gate Driver Power Supply Bias Input Voltage 5 PG O Power Good Logic Output (Open Drain) 6 UVA/*SD I Under Voltage Threshold Adjustment/Low True Shutdown Input 7 SD I High True Shutdown Input 8 SNS -- Switching Node Sense 9 N/C -- No Internal Connection

10 VBST I High Side Bootstrap Potential 11 TGATE O High Side Gate Output 12 SN -- High Side Switching Node* 13 BGATE O Low Side Gate Output 14 PGND -- Power Supply Return, 0V 15 BCON I Low Side Switch Control Input 16 BSTP O Low Side Switch Shoot Through Protection Output 17 TSTP O High Side Switch Shoot Through Protection Output 18 TCON I High Side Switch Control Input

* High Side HEMT Gate Driver Reference Potential

18 Pin Molded SMT Package w/Pillar Pins

TOP (X-Ray) VIEW

1

2

3

4

5

6 7 8 9 10 11

12

13

14 15 16 17 18


FBS-GAM02P-C-PSE


Absolute Maximum Ratings TC =25 oC unless otherwise noted

Symbol Parameter-Conditions Value Units SN to PGND High Side Gate Driver Reference Voltage (Note 1) 50 V

COUT BGATE or TGATE Output Capacitance 5000 pF VBIAS Gate Driver Bias Supply Voltage -0.3 to 6.0 V VIN BIN or TIN Input Voltage -0.3 to 5.0 V TJ, TSTG Operating and Storage Junction Temperature Range -55 to +130 oC Tc Case Operating Temperature Range -55 to +110 oC Tsol Package Mounting Surface Temperature 260 oC

ESD ESD class level 1A

Thermal Characteristics

Symbol Parameter-Conditions Value Units RθJC Effective Thermal Resistance Junction to Case 110 oC/W


FBS-GAM02P-C-PSE


Low and High Side Gate Driver Static Electrical Characteristics TC =25oC unless otherwise noted

PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS

High Side Switch Ground Leakage Current: SN to PGND IHSIG

SN = 50Vdc; PGND = 0Vdc (Notes 1,2) 15 50 uA

High Side Gate Driver Pull-Up Resistance (Note 3) RPUH

VBIAS = 5.0Vdc ; TIN =2.5Vdc; PGND = LGND = 0Vdc

Tc= 25oC - 2.1 2.8 Ω

Tc= 110oC - 4.5 -

High Side Gate Driver Pull-Down Resistance (TOUT to SN) RPDH

VBIAS = 5.0Vdc ; TIN =0.8Vdc; PGND = LGND = 0Vdc

Tc= 25oC - 2.1 2.8 Ω

Tc= 110oC - 4.5 -

Low Side Gate Driver Pull-Up Resistance VBIAS to BGATE RPUL

VBIAS = 5.0Vdc ; BIN =2.5Vdc; PGND = LGND = 0Vdc

Tc= 25oC - 2.1 2.8 Ω

Tc= 110oC - 4.5 -

Low Side Gate Driver Pull-Down Resistance (BGATE to PGND) RPDL

VBIAS = 5.0Vdc ; BIN =0.8Vdc; PGND = LGND = 0Vdc

Tc= 25oC - 2.1 2.8 Ω

Tc= 110oC - 4.5 - BOUT, TOUT Load Characteristics TC =25oC unless otherwise noted


Load Capacitance CL (Note 3) 1500 pF BIN, TIN Logic Input Static Electrical Characteristics TC =25oC unless otherwise noted


Low Logic Level Input Voltage VIL VBIAS = 5.0Vdc (Note 4) 0.8 V High Logic Level Input Voltage VIH VBIAS = 5.0Vdc (Note 5) 2.5 V Low Logic Level Input Current IIL VBIAS = 5.0V, VIL = 0.4V -5 1 5 uA High Logic Level Input Current IIH VBIAS = 5.0V, VIL = 3.0V -5 1 5 uA

PG Logic Output Static Electrical Characteristics TC =25oC unless otherwise noted


Low Logic Level Output Voltage VOL VBIAS = 5.0Vdc (Notes 6,7) 0.2 V High Logic Level Output Voltage VOH VBIAS = 5.0Vdc (Note 6,7) 4.8 V Low Logic Level Output Current IOL VBIAS = 5.0V (Note 8) 5 mA High Logic Level Output Leakage Current IOH VBIAS = 5.0V, PG = 5.5V (Note 8) 15 uA

SN-to-PGND Static Electrical Characteristics TC =25oC unless otherwise noted

PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS SN-to-PGND Operating Voltage Range SN-PGND (Note 3) 10 50 V

VBIAS Static Electrical Characteristics TC =25oC unless otherwise noted

PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS VBIAS Recommended Operating Voltage Range VBIAS VBIAS = 5.0Vdc (Note 9) 4.5 5.5 V

VBIAS Operating Current IBIAS VBIAS = 5.5Vdc 12.9 15.5 mA


FBS-GAM02P-C-PSE


PG Functional Static Electrical Characteristics TC =25oC unless otherwise noted

PARAMETER SYMBOL TEST CONDITIONS TC = +25oC MIN TYP MAX UNITS

VBIAS UVLO Rising Threshold UVLO+

(Notes 6,7,8,9)

4.05 4.1 4.25 V VBIAS UVLO Falling Threshold UVLO- 3.85 3.95 4.05 V

VBIAS UVLO Hysteresis UVLO+ - UVLO- 0.2 V

VBIAS OVLO Rising Threshold OVLO+ 5.95 6.1 6.25 V VBIAS OVLO Falling Threshold OVLO- 5.85 5.9 6.05 V

VBIAS OVLO Hysteresis OVLO+ - OVLO- 0.12 V

Low and High Side Gate Driver Dynamic Electrical Characteristics TC =25oC unless otherwise noted


BIN-to-BGATE Turn-ON Delay Time td(on)

VBIAS = 5.0V; CL = 1000pF (See Switching Figures); PGND = 0V

40 50 ns BGATE Rise Time tr 8 10 ns BIN-to-BGATE Turn-OFF Delay Time td(off) 45 50 ns

BGATE Fall Time tf 8 10 ns TIN-to-TGATE Turn-ON Delay Time td(on)

VBIAS = 5.0V; CL = 1000pF (See Switching Figures); PGND = SN = 0V

50 70 ns

TGATE Rise Time tr 8 10 ns TIN-to-TGATE Turn-OFF Delay Time td(off) 60 85 ns

TGATE Fall Time tf 8 10 ns Module Dynamic Electrical Characteristics TC =25oC unless otherwise noted

PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS High Side Gate Driver Start Up Pre-Charge Time: Half Bridge Configuration

tpcg

(Notes 10,11,12)

5 us

High Side Gate Driver Minimum Operating Switching Frequency fsw(min) 200 kHz

High Side Gate Driver Maximum Duty Cycle td/c 95 %

Maximum Switching Frequency fs (Notes 13, 14, 15, 16) 2.0 MHz Shoot-Through Protection Activation Delay Time tst (Notes 3,14) 5 ns


FBS-GAM02P-C-PSE


Specification Notes

1.) VBIAS = +5Vdc, PGND = LGND = 0V, BIN = 0Vdc, TIN = 2.5Vdc and SN = 50Vdc.

2.) Leakage current measured from SN to PGND.

3.) Guaranteed by design. Not tested in production.

4.) When either logic input (BIN or TIN) is at the low input voltage level the associated output (BGATE or TGATE) is guaranteed to be OFF (high impedance).

5.) When either logic input (BIN or TIN) is at the high input voltage level the associated output (BGATE or TGATE) is guaranteed to be ON (low impedance).

6.) Parameter measured with a 10kΩ pull-up resistor between PG and VBIAS.

7.) PG is at a low level when VBIAS is below the UVLO falling threshold level or the OVLO rising threshold level. PG is at a high level when VBIAS is above the UVLO rising threshold level or the UVLO rising threshold level. Refer to Figure 5.

8.) PG is an open drain output referenced to PGND/LGND.

9.) VBIAS levels below the UVLO- and above the OVLO+ thresholds result in the low side and high side gate drivers being disabled: The logic inputs to the drivers are internally set to a logic low state (i.e. OFF) to prevent damage to the external Freebird eGaN® HEMT power switches.

10.) The high side gate driver utilizes a bootstrap capacitor to provide the proper bias for this circuit. As such, this capacitor MUST be periodically re-charged from the VBIAS supply. The time tpcg is the minimum time required to insure that the bootstrap capacitor is properly charged when power is initially applied to the FBS-GAM02P-C-PSE Module.

11.) The minimum frequency of operation is determined by the internal bootstrap capacitance and the bias current required by the high side gate driver circuit.

12.) In order to keep the high side gate driver bootstrap capacitor properly charged it is recommended that the maximum duty cycle (ton/fs) of the top power switch is limited to the value shown. Consequently, the high side switch is unsuitable for DC applications.

13.) The shoot-through protection is activated if both the BIN and TIN logic inputs are set to the logic high (“1”) condition simultaneously. If the BIN and TIN inputs are activated simultaneously and BSEN is connected to BCON and TSEN is connected to TCON then both BGATE and TGATE are LOW (i.e. OFF).


FBS-GAM02P-C-PSE


Switching Figures

Figure1. TIN-to-TGATE Switching Time Test Circuit

Figure 2. TIN-to-TGATE Switching Time Definition

TGATE 11

12

18 17 16 15

14

13

7

8 9 10

3

4

5

6

1

2

+5Vdc FBS-GAM02P-C-PSE

DUT CL = 1000pF

Pulse Generator

BIN

TIN

LGND

VBIAS

TGATE

SN

PGND

Only pins connected during testing are identified. Pulse Generator set to 500kHz frequency, 5% duty cycle.

TGATE

TIN

10% Vpeak

5V

0V

2.5V

td(on)

0V

90% Vpeak

Vpeak*

tr

NOTE: Waveforms exaggerated for clarity and observability. * Vpeak is ~ VBIAS - 0.4Vdc.

td(off)

tf


FBS-GAM02P-C-PSE


Switching Figures (Continued.)

Figure 3. BIN-to-BGATE Switching Time Test Circuit

Figure 4. BIN-to-BGATE Switching Time Definition

11

12

18 17 16 15

14

13

7

8 9 10

3

4

5

6

1

2

+5Vdc FBS-GAM02P-C-PSE DUT

Pulse Generator

BIN

TIN

LGND

VBIAS

BGATE

PGND

Only pins connected during testing identified. Pulse Generator set to 500kHz frequency, 5% duty cycle.

BGATE CL = 1000pF

BGATE

BIN

10% Vpeak

5V

0V

2.5V

td(on)

0V

90% Vpeak

Vpeak*

tr td(off)

tf NOTE: Waveforms exaggerated for clarity and observability.

* Vpeak is ~ VBIAS.


FBS-GAM02P-C-PSE


Figure 5. VBIAS-to-PG Relationship

Typical Application Information

The following figures detail the suggested applications for the FBS-GAM02P-C-PSE Module. For all

applications, please refer to the Implementation section, following, for proper power supply bypassing and

layout recommendations and criteria. In any of the following applications, the external HEMT transistors are

Freebird eGaN® power devices, appropriately rated for the voltage and current requirements of the application. If an

inductive load is driven then an appropriately-rated Schottky rectifier/diode should be connected across the

load to prevent destructive flyback/”kickback” voltages from destroying the external HEMT power switches. To

keep power losses low, it is recommended to use a Schottky diode with the lowest possible Vf and Cj ratings.

In all the following figures only the pins that are considered or that require connection are identified.

VBIAS

PG

UVLO+

VOH

VOL

UVLO-

OVLO- OVLO+

NOTE: Waveforms exaggerated for clarity and observability.

0V


FBS-GAM02P-C-PSE


Figure 6. Single High-Side Power Switch Configuration

Figure 7. Single Low-Side Power Switch Configuration

VDD

11

12

18 17 16 15

14

13

7

8 9 10

3

4

5

6

1

2


Rload

BIN

TIN

LGND

VBIAS

TGATE

SN

PGND PWM In

Qext

VDD

11

12

18 17 16 15

14

13

7

8 9 10

3

4

5

6

1

2


Rload

BIN

TIN

LGND

VBIAS

BGATE

PGND

PWM In

Qext


FBS-GAM02P-C-PSE


Figure 8. Independent High- and Low-Side Power Switches

Figure 9. Half-Bridge Configuration: POL Converter Output Stage

VDD

11

12

18 17 16 15

14

13

7

8 9 10

3

4

5

6

1

2


Rload1

BIN

TIN

LGND

VBIAS

TGATE

BGATE

PGND PWM2 In Rload2

SN

PWM1 In

Qext1

Qext2

VDD

11

12

18 17 16 15

14

13

7

8 9 10

3

4

5

6

1

2


Rload

BIN

TIN

LGND

VBIAS

TGATE

BGATE

PGND PWM2 In

SN

L

C

VOUT

T

ton

PWM2

VOUT = ~ VDD • (ton/((2 * td) + T))

PWM1 In

td td

PWM1

BCO

N

BSTP

TSTP

TCO

N

Qext1

Qext2

Dext


FBS-GAM02P-C-PSE


Recommended External eGaN HEMT Power Transistors

The recommended Freebird eGaN® HEMT power transistors for various power supply voltages (Vdd) and

load currents (Id) for the Qext, Qext1 and Qext2 devices shown in Figures 6, 7, 8 and 9 are shown in Table I.

Please note appropriate de-rating guidelines should be used in space and mission-critical applications.

TABLE I. Recommended Freebird eGaN® HEMT Power Transistors.

VDD (Vdc) Io (Adc) Freebird P/N Rds(ON) (mΩ) Package

40 8 FBG04N08AX 24 FSMD-A

40 30 FBG04N30BX 6 FSMD-B

100 5 FBG10N05AX 38 FSMD-A

100 30 FBG10N30BX 9 FSMD-B

The FBS-GAM02P-C-PSE is capable of driving any of the devices shown in Table I without modification or

additional circuitry.

Power Good Output (PG)

The FBS-GAM02P-C-PSE incorporates a Power Good (PG) sensing circuit that disables both the low

and high side gate driver outputs (BGATE and TGATE) when the +5V gate drive bias potential (VBIAS) falls

below an under-voltage threshold, typically 4.25V, or rises above an over-voltage threshold level, typically

5.60V – refer to Figure 5 for the proper operational nomenclature and functionality versus the state of the

VBIAS power supply. During the time when the VBIAS potential is outside of the pre-set threshold(s), the PG

output (Pin 5) pin is logic low (“0”). Alternatively, when the VBIAS potential is within the pre-set thresholds the

PG pin is logic high (“1”). The PG pin is an open drain output, so for proper operation the PG pin must be

pulled-up to VBIAS external to the module with a 10kΏ resistor. The logic condition of the PG pin may be

sensed by an FPGA or Microcontroller/DSP in order to determine when the external eGaN® HEMT power

switches may be driven with a pulse-width modulated (PWM) input signal(s) at the BIN and TIN logic inputs. If

either the under-voltage and over-voltage protection features are not required or desired, then these may be

disabled by connecting the UVA/*SD (Pin 6) pin to VBIAS and the SD pin (Pin 7) to LGND, as shown in

Figure 10.


http://freebirdsemi.com/wp-content/uploads/2016/07/FBG04N08A_REV_Q3.pdf

http://freebirdsemi.com/wp-content/uploads/2016/07/FBG04N30B_REV_Q6.pdf

http://freebirdsemi.com/wp-content/uploads/2016/07/FBG10N05A_REV_Q3.pdf

http://freebirdsemi.com/wp-content/uploads/2016/07/FBG10N30B_REV_Q7.pdf

FBS-GAM02P-C-PSE


Figure 10. PG Protection Function Disabled

“Shoot-Through” Protection

The FBS-GAM02P-C-PSE is also provided with a “shoot-through” or cross-conduction prevention circuit that

must be utilized when the FBS-GAM02P-C-PSE is connected as a half-bridge driver circuit. If both the BIN

and TIN logic inputs are asserted to a high (“1”) logic condition simultaneously, the top and bottom gate driver

outputs are commanded to a LOW output state (i.e. 0Vdc). This action prevents destructive, uncontrolled

current from passing from VDD through the two closed, external low ON-resistance eGaN® HEMT power

switches. If the FBS-GAM02P-C-PSE is connected in the Half-Bridge configuration (where the external top

and bottom eGaN® HEMT power switches are connected in series as shown in Figure 9 and are closed

alternatingly), then the BCON (Pin 15) pin MUST be externally connected to the BSTP (Pin 16) pin, and the

TCON (Pin 18) pin must be connected externally to the TSTP (Pin 17) pin as shown in Figure 11.

Figure 11. Shoot-Through Protection Function Enabled

11

12

18 17 16 15

14

13

7

8 9 10

3

4

5

6

1

2


BIN

TIN

LGND

VBIAS

PWM1 In PWM2 In

11

12

18 17 16 15

14

13

7

8 9 10

3

4

5

6

1

2


BIN

TIN

LGND

VBIAS

PWM1 In PWM2 In

BCO

N

BSTP

TSTP

TCO

N


FBS-GAM02P-C-PSE


Shutdown Inputs (SD and *SD)

The low- and high-side power switches may be disabled (set to their high impedance OFF state)

utilizing the SD or *SD inputs, as shown in Figures 12 and 13. To disable the FBS-GAM02P-C-PSE module

gate drive outputs, the SD (Pin 7) input may be driven by an open drain or open collector that pulls this input

to the VBIAS supply pin (Pin 4). Alternatively, the module may be disabled by driving the UVA/*SD (Pin 6)

input with an open drain or open collector that pulls this input to LGND (Pin 3). If the SD or SD* functions are

not required, these pins should be left OPEN (unconnected).

Figure 12. UVA/*SD Input Function Enabled

Figure 13. SD Input Function Enabled

11

12

18 17 16 15

14

13

7

8 9 10

3

4

5

6

1

2 Q

FBS-GAM02P-C-PSE

BIN

TIN

LGND

VBIAS

PWM1 In PWM2 In

UVA/*SD

R SD

+5Vdc

11

12

18 17 16 15

14

13

7

8 9 10

3

4

5

6

1

2

Q

FBS-GAM02P-C-PSE

BIN

TIN

LGND

VBIAS

PWM1 In PWM2 In

SD R *SD

+5Vdc


FBS-GAM02P-C-PSE


PGND Pin (Pin 14)

For proper operation of the FBS-GAM02P-C-PSE, the PGND (Pin 14) pin MUST be connected directly

to the “Source Sense” connection of the external eGaN® HEMT power transistor for low side and Half-bridge

application circuits. For single high side applications, pin 14 should be connected directly to the system

ground.

N/C Pin (Pin 9)

Pins 9 is not internally connected. However, future revisions of the FBS-GAM02P-C-PSE may

utilize/exploit this pin for testing and added functionality purposes. This “no connection” pin is recommended

to be grounded as good engineering practice to avoid coupling unwanted noise into the internal circuitry of the

FBS-GAM02P-C-PSE. It is recommended that this grounding be accomplished using an 0805 size “Zero

Ohm” jumper resistor such that future revision FBS-GAM02P-C-PSE devices with internal connections to pin

9 may be accommodated by legacy PCB layout designs by omitting this jumper resistor.

Recommended VDD-to-PGND Power Supply Bypassing

The power supply pins and return pin of the FBS-GAM02P-C-PSE require proper high frequency

bypassing to one-another in order to prevent harmful switching noise-related spikes from degrading or

damaging the internal circuitry in the FBS-GAM02P-C-PSE module. It is recommended that a 1.0 microfarad

ceramic capacitor and a 0.1 microfarad ceramic capacitor, each 25V rating, be connected between VBIAS

(pin 4) and PGND (pin 14).


FBS-GAM02P-C-PSE


Suggested FBS-GAM02PSE Schematic Symbol

The suggested schematic symbol for the FBS-GAM02P-C-PSE is shown in Figure 14. This symbol

groups the I/O pins of the FBS-GAM02P-C-PSE into groups of similar functionality.

Figure 14. Suggested FBS-GAM02P-C-PSE Schematic Symbol

Radiation Characteristics

The FBS-GAM02P-C-PSE intended utilization is as a development vehicle for our future hermetically sealed radiation hardened ceramic version (noted by Freebird Semiconductor as the FBS-GAM02C-R-PSE or the current available, FBS-GAM02P-R-PSE (Epoxy, Over-Molded- Commercial Space Version).

Radiation hardness assured device to this data sheet (under identical form-fit function) is the FBS-GAM02P-R-PSE:

• Freebird Semiconductor FBS-GAM02P-R-PSE incorporates internally utilized eGaN HEMT technology designed, fabricated and tested per Mil-Std-750 Method 1019 for total ionizing dose validation with an in-situ Gamma Bias for (i) VGS = 5.1V, (ii) VDS=VGS=0V and (iii) VDS=80% BVDSS.

• Under the above prescribed conditions Freebird Semiconductor can guarantee full parametric data limits as outlined within the FBS-GAM02-P-C50 datasheet with pre/post radiation effects guarantee under a best practice commercial screened reliability level.

When incorporating Freebird Semiconductors radiation validated HEMT materials the FBS-GAM02P-R-PSE series are then “guaranteed by designed” to survive High Dose Rate TID to levels of no less than 100 kRad (Si) with minimum Single Event Immunity to:

~Heavy Ion: Au, LET= 83.7, 2482 MeV, Range = 130um


FBS-GAM02P-C-PSE


PACKAGE OUTLINE AND DIMENSIONS

Figure 15. FBS-GAM02P-C-PSE Package Outline and Dimensions

Recommended PCB Solder Pad Configuration

The novel I/O “pillar” pads fabricated onto the bottom surface of the FBS-GAM02P-C-PSE module are

designed to provide optimal electrical, thermal and mechanical properties for the end-use system designer.

To achieve the full benefit of these properties, it is important that the FBS-GAM02P-C-PSE module be

soldered to the PCB motherboard using SN63 (or equivalent) solder. The recommended pad dimensions and

locations are shown in Figure 16. All dimensions are shown in inches.


FBS-GAM02P-C-PSE


Figure 16. Recommended PCB Solder Pad Configuration (Top View)

1

6 11

14 18

10


FBS-GAM02P-C-PSE


Freebird Semiconductor Part Number Information

FBS-GAM02P-C-PSE

PSE = Power Switch, External

C= Commercial screen or

R= Commercial screen with rad-hard assurance*

P= Molded Plastic SMT Package

C= Ceramic SMT Package

Freebird Semiconductor “GaN Adaptor Module”

*FBS-GAM02P-R-PSE (Utilizes High Lead Content Die) *FBS-GAM02C-R-PSE (Utilizes High Lead Content Die)

Disclaimers

ALL PRODUCT, PRODUCT SPECIFICATIONS AND DATA ARE SUBJECT TO CHANGE WITHOUT NOTICE TO IMPROVE RELIABILITY, FUNCTION OR DESIGN OR OTHERWISE. Freebird Semiconductor Corporation, its affiliates, agents, employees, and all persons acting on its or their behalf (collectively, “Freebird”), disclaim any and all liability for any errors, inaccuracies or incompleteness contained in any datasheet or in any other disclosure relating to any product. Freebird makes no warranty, representation or guarantee regarding the suitability of the products for any particular purpose. To the maximum extent permitted by applicable law, Freebird disclaims (i) any and all liability arising out of the application or use of any product, (ii) any and all liability, including without limitation special, consequential or incidental damages, and (iii) any and all implied warranties, including warranties of fitness for particular purpose, non-infringement and merchantability. Statements regarding the suitability of products for certain types of applications are based on Freebird market knowledge of typical requirements that are often placed on similar technologies in generic applications. Product specifications do not expand or otherwise modify Freebird terms and conditions of purchase, including but not limited to the warranty expressed therein. Except as expressly indicated in writing, Freebird products are not designed for use in medical, life-saving, or life-sustaining applications or for any other application in which the failure of the Freebird product could result in personal injury or death. Customers using Freebird products not expressly indicated for use in such applications do so at their own risk. Please contact authorized Freebird personnel to obtain written terms and conditions regarding products designed for such applications. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document or by any conduct of Freebird. Product names and markings noted herein may be trademarks of their respective owners.


FBS-GAM02P-C-PSE


Export Administration Regulations (EAR)

The products described in this datasheet could be subjected to the Export Administration Regulations (EAR). They may require an approved export license prior to export from the United States. An export includes release of product or disclosure of technology to a foreign national inside or outside the United States.

International Traffic in Arms Regulations (ITAR)

The products described in this datasheet could be subjected to the International in Arms Regulations (ITAR). They require an approved export license prior to export from the United States. An export includes release of product or disclosure of technology to a foreign national inside or outside the United States.

Patents

Freebird Semiconductor holds numerous U.S and international patents to include 15/374,756, 15/374,774, PCT/US2016/065952, PCT/US2016/065946. Any that apply to the product(s) listed in this document are identified by markings on the product(s) or on internal components of the product(s) in accordance with U.S Patent laws eGaN® is a registered trademark of Efficient Power Conversion Corporation, Inc. Data and specification subject to change without notice.


FBS-GAM02P-C-PSE


Revision

Datasheet Revision Product Status REV - Proposal/development REV - Characterization and Qualification REV # Production Released

Contact Freebird Semiconductor Corporation for further information and to order: Email : [email protected]

Phone: +1 941 740 1909 Website: www.Freebirdsemi.com Address: 17 Parkridge Road, Unit E,

Haverhill, MA 01835 USA


mailto:[email protected]


Documents

FBS-GAM02P-C-PSE - freebirdsemi.com · The FBS-GAM02P-C-PSE is intended to drive external Freebird eGaN ® HEMT power switch transistors rated up to 100V (refer to Table 1, Page 11