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Fault-Tolerant design of RF front-end circuitsFault-Tolerant design of RF front-end circuits
P.R. Mukund, Ph.D.Gleason Professor of Electrical Engineering
Director, RF/Analog/Mixed-signal Lab (RAMLAB)
Rochester Institute of TechnologyRochester, NY 14623
Fault-Tolerant Design of RF Front end Circuitry
FundingFunding
Henning Braunisch
Industry Liaisons
Hosam Haggag
Ronald McBean(Motorola)
This work was funded by the Semiconductor Research Corporation
Fault-Tolerant Design of RF Front end Circuitry
MotivationMotivation
SoC, SiP implementations High levels of integration
Complex interaction between RF, analog, & digital domains
Heightened sensitivity to package parasitics, wide tolerances
CHIPCARRIER
RF Design
MEMS
Digital Logic
Horizontal Floor Planning
RF Modules
Digital Modules
Passives
Mutual-coupling, electro-magnetic coupling, stray inductances
Gap between models and silicon Several design iterations, higher costs
and lower yield for RFICs
Fault-Tolerant Design of RF Front end Circuitry
Need for Fault-tolerance in RF circuitsNeed for Fault-tolerance in RF circuits
RF Design
Si Die
Probes
RF Testing
Complex behavioral, modeling and fabrication problems More faults and higher variations
Poor, unpredictable Q-factors
Post fabrication processing is needed Analog/Digital techniques not relevant for RF circuits Novel fault-tolerance techniques for RF required !
Testing is expensive (ATE)Very act of probing affects performanceAccess to RF core difficult
Yield of RFICs 10%-12% less than digital ASICs
Fault-Tolerant Design of RF Front end Circuitry
BackgroundBackground
Self-test solutions with high overheads Computation, real-estate, DSP, power
ATE testing very expensive (40% of chip cost)
Fault-tolerance in digital circuitsReconfigurability and redundancyHuge real-estate and power overheads for RF
Fault-tolerance in analog circuitsFeedback mechanismsNot practical for HF circuits
Parametric fault-modeling for analog circuits
High Cost $$
010010101000010101001000111001000011000010101000010101011111
Use of DSPs Time Intensive
Can detect but not correct
faults
Limitations
No Prior art for fault-tolerant RF design
Fault-Tolerant Design of RF Front end Circuitry
Inductor Library
0
5
10
15
20
25
30
35
40
0 2 4 6 8
Frequency(GHz)
Qu
alit
y F
acto
r
L1 off chip L2 off chipL1 on chipL2 on chip
Design Methodologies
Early Design Software – ‘DREAM’
2D and 3D Analysis for Power Distribution AnalysisPhase Noise Analysis for VCO &
Sideband Analysis for Mixer
RF
Digital Pin Placement
Power Distribution
Mixed SignalAnalysis
A/D and Op-Amp Analysis
Inductor Modeling and Characterization
Inductor Librariesfor RF Design
Vertically Integrated Designs(Si on Si)
PassiveCharacterization
Novel DesignTechniques
Vertical Integration
RF Design
MEMS
Digital Logic
Horizontal Floor Planning
RF Modules
Digital Modules
Summary of Prior WorkSummary of Prior Work
Fault-Tolerant Design of RF Front end Circuitry
Prior BIST ArchitecturePrior BIST Architecture
on-chip off-chip
Current MonitorSignature Analyzer
RF/Analog/Mixed-Signal CUT
Vdd
TASKS
Development of an accurate and non-intrusive current monitor
Fault modeling of 3D Stacked RF circuits
Analyzing and quantifying various factors leading to performance degradation
Development of current signatures - Mapping circuit performance to supply current.
Integrating information into a BIST architecture
Dr P.R.Mukund, RF / Analog / Mixed Signal Lab
Proposed BIST Architecture
Fault-Tolerant Design of RF Front end Circuitry
Feedback for RF circuits?Feedback for RF circuits?
Alternative
An approach that overcomes these roadblocks, yet retains its usability
√
Why feedback will not workWhy feedback will not work
Stability issues @ GHz: Mutual coupling, Ground loops, Metal trace parasitics
Feedback Re-design of circuit !
Very little gain available for trade-off
Transformers, inductors, etc., have wide tolerances
Fault-Tolerant Design of RF Front end Circuitry
This work….This work….
Alternative fault-tolerance methods for RF circuits Overcome limitations of traditional feedback
Emphasis on low overhead, minimally intrusive, low-cost solutions
Robust circuitry/algorithms for error-free operation
Low-frequency/DC post-processing No DSP/off-chip processing, ultra-fast
Fault-Tolerant Design of RF Front end Circuitry
Methodology: ‘Locked loop’ conceptMethodology: ‘Locked loop’ concept
Start with nominal design
Sense current with
minimally intrusive element
Amplify sensed current
Down-convert signal to baseband
Map signal to
performance metric
Generate baseband/digit
al signal to modify design
parameters
Dynamically modify design parameters in
RF circuit
Performance
metric ok?
NO
YES
End Calibration process
RF CIRCUIT
Sense Amplifier Peak Detector
Baseband Signal Processing
Specification based correction
Fault-Tolerant Design of RF Front end Circuitry
‘‘Locked Loop’ approachLocked Loop’ approach
To sense a signal which is indicative of the performance metric of the circuit
Four fold approach
Sense
Quantify
Self-corrective signal
Tapped coilA mechanism in the circuit which can adaptively change its performance in real time based on the above signal.
Use this information to send a signal back to the circuit where the metric can be re-corrected towards the desired value
To process this signal appropriately into a form which quantitatively describes the metric
Fault-Tolerant Design of RF Front end Circuitry
Minimally Intrusive SensingMinimally Intrusive Sensing
Current sensing: HF transient current has performance info
S21 & S22
degraded
No effect on S11
S22 & S21 degraded Resistor in return path!
Small value
S22 & S21 unaffected S11 degraded Regain by co-design! NF marginally Dynamic range marginally
√
Fault-Tolerant Design of RF Front end Circuitry
Non-intrusive sensingNon-intrusive sensing
Eliminate resistor for circuits with source-degenerative coils No measurable intrusion on LNA performance Over a narrow-frequency range, the source-coil can provide
similar current-information as the resistor
Gain and S22 sensed from source coil of mixer: accounts for matching network
Fault-Tolerant Design of RF Front end Circuitry
Quantifying SpecificationsQuantifying Specifications
Gain sensed directly at mixer, using a third tone.
Peak-peak value of this signal is a direct measure of gain
Two-tonal approach to quantify impedance matching
Differential nature removes dependence on absolute values
Highly robust and insensitive to process variations and soft faults in processing circuitry itself
Fault-Tolerant Design of RF Front end Circuitry
Variable SVariable S1111: The tapped coil: The tapped coil
Varies match frequency Tap the coil at several points in outer turn CMOS Switches Include switch and interconnect parasitics
)1
)((GS
gsGS
smin C
LLjC
LgZ
Dependence of gain, etc. on gm
Magnitude of match
Varactor cannot be connected in series
Digitally tapped gate inductor
ASITIC – Include all interconnects
Switch size: trade-off between on- resistance and capacitance
Fault-Tolerant Design of RF Front end Circuitry
Variable Gain and SVariable Gain and S2222
S22: Bank of varactors at output node
Gain: Variable Transconductance array
‘Current-splitting’ variable transconductance array eliminates S11 dependency: CGS
remains constant on input-side
Fault-Tolerant Design of RF Front end Circuitry
Self-correction algorithmSelf-correction algorithm
VIDEAL
Minimal overheads No DSP, ADC or analog memory cell requirements, low power
Ultra-fast, Low cost
Fault-Tolerant Design of RF Front end Circuitry
Sensor chainSensor chain
Source follower for isolation More stages for higher gain PD output stored on capacitors Op-amps for buffers, comparators Basic digital logic
SF Cascaded CS Stages
Peak Detector
Fault-Tolerant Design of RF Front end Circuitry
Results - Sensor chainResults - Sensor chain
Spectral response of sensor chain
Tap no. sensor chain o/p for tone1(1.6GHZ)
sensor chain o/p for tone2(2.2GHZ)
1 1098.54 mV 1391.57 mV
2 1112.85 mV 1375.63 mV
3 1128.67 mV 1365.23 mV
4 1150.61 mV 1356.95 mV
5 1166.88 mV 1355.01 mV
Output of Sensor Chain for all taps of Lg
Charge leakage is negligible due to the presence of buffers
0.4 mV charge leakage for 1V
1000mv999.6mv
Transfer characteristic of the sensor chain.
The sensor chain delivered a gain of 9.4 at room temperature,
nominal process.
Fault-Tolerant Design of RF Front end Circuitry
Simulation results - LNASimulation results - LNA
Desired S11
S11 before correction
S11 after correction
CCGSGS reduction by 15% reduction by 15%
Desired S11
S11 before correction
S11 after correction
LLGG increase by 10% increase by 10%
Time taken per tap:1.75 μs, per cycle: 6.2 μs, Total: 18.7 μs.
Worst-case scenario: all five cycles, 21.75 μs
Desired S11
S11 before correction
S11 after correction
Weakest Weakest cornercorner
Fault-Tolerant Design of RF Front end Circuitry
Experimental Results Experimental Results (1)(1)
Less than 10% of LNA areaRe-used for other front-end circuits
Turned on only during correction process
S11: -23 dB
Spectral response
Fault-Tolerant Design of RF Front end Circuitry
Experimental Results Experimental Results (2)(2)
Tapped Coil performance
S11 magnitude stayed below -20 dB for all taps
Match frequencies were: 1.737 GHz, 1.925 GHz, 2.03 GHz and 2.125 GHz.
Measured transfer curve of the sensor chain
Tap no.
Inductance
Simulated S11 freq
Digital word
Measured S11 freq
1 7.4 nH 1.7 GHz 00 1.7375 GHz
2 9 nH 1.91 GHz 01 1.925 GHz
3 10 nH 2.0 GHz 10 2.03 GHz
4 11 nH 2.11 GHz 11 2.125 GHz
Fault-Tolerant Design of RF Front end Circuitry
S22 and Gain correction (I)S22 and Gain correction (I)
Left: Gain and S22 match varies as the load
inductor value varies
Right: Output of sensor chain quantifying this
variation
Left: S22 curves as varactor Bank is varied
Right: Output spectrum of Sensor for these S22 curves
Fault-Tolerant Design of RF Front end Circuitry
S22 and Gain Correction (II)S22 and Gain Correction (II)
Self-calibration of S22: Before (1.81 Ghz) and
After (1.89 GHz), for a 1.9 GHz LNA
Left: Variation in the magnitude of Gain (due to Q-factor variation of the load coil)
Right: This Variation quantified by sensor
Fault-Tolerant Design of RF Front end Circuitry
OverheadsOverheads
Same circuitry re-used for all specifications Area overhead less than 10% of cascode LNA Can be re-used for other circuits of Front-end
Losses in switches of the gate-coil NF degradation by 0.2 - 0.3 dB
Power overheads Additional circuitry switched on only for duration of
self-calibration – negligible power overhead Current-splitting transconductance array uses
additional current (5% - 10% overhead)
Fault-Tolerant Design of RF Front end Circuitry
SummarySummary
Fault-tolerant RF design has great relevance and applicability in an RFIC world of increasing complexity and massive integration
Alternate, novel methodology for fault-tolerance in GHz domain
Minimal overheads, no topological revision Ultra-fast (200 us) compared to existing
test schemes (order of 100s of ms) Robust algorithms and post-processing
techniques Demonstrated in silicon
Fault-Tolerant Design of RF Front end Circuitry
PublicationsPublications (1)(1)
Journal Papers Tejasvi Das, Anand Gopalan, Clyde Washburn and P.R. Mukund, “Self-calibration
of RF front end circuitry”, IEEE Transactions on Circuits and Systems, Dec 2005 Tejasvi Das, Anand Gopalan, Clyde Washburn and P.R. Mukund, “Towards
Fault-tolerant RF front-ends”, Journal of Electronic Testing (JETTA), Accepted for publication (Issue release Sep.06)
Anand Gopalan, M. Margala and P.R. Mukund, “A current based self-test methodology for RF front-end circuits”, Microelectronics Journal, No.36, Aug 2005
Anand Gopalan, Tejasvi Das, Clyde Washburn and P.R. Mukund, “BiST for Multi-GHz CMOS RF Front-ends”, IEEE Transactions on Circuits and Systems (Under review)
Conference Papers
“Self-calibration of Gain and Output match in LNAs”, IEEE ISCAS May 2006, Kos, Greece
“Towards Fault-Tolerant RF Front-Ends: On-Chip Input Match Self-Correction of LNAs”, The IEEE Mixed-signal Test Workshop, June 2005, Cannes, France.
“Dynamic Input match correction in RF Low Noise Amplifiers”, 19th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, Oct. 2004, Cannes, France
Fault-Tolerant Design of RF Front end Circuitry
PublicationsPublications (2)(2)
Conference papers (contd.)
“Use of Source Degeneration for Non-Intrusive BIST of RF Front-end Circuits”, Proceedings of the International Symposium on Circuits and Systems, Kobe, Japan, May 2005
An Ultra-fast, on-chip BiST for RF LNAs”, 18th IEEE International Conference on VLSI Design, India, Jan. 2005.
Fault-Tolerant Design of RF Front end Circuitry
References References (1)(1)
[1] B. Razavi, “RF CMOS transceivers for cellular telephony”, IEEE Communications Magazine, Vol. 41, No. 8, pp.144 – 149, August 2003.
[2] B. A. Floyd, C.-M. Hung, K. K. O, “Intra-Chip Wireless Interconnect for Clock Distribution Implemented With Integrated Antennas, Receivers, and Transmitters”, IEEE Journal of Solid-State Circuits, vol. 37, no. 5, pp. 543-552, May 2002.
[3] M.-C. F. Chang, V. P. Poychowdhury, L. Zhang, H. Shin, Y. Qian, “RF/Wireless Interconnect for Inter- and Intra-Chip Cpmmunications”, Proceedings of the IEEE, vol. 89, no. 4, pp.456-466, April 2001.
[4] J.M.V Santos Dos, J.M.M Ferreira, “Fault-tolerance: new trends for digital circuits”IEEE International Conference on Electronics, Circuits and Systems, Vol 3, pp. 237 – 240, Sept. 1998
[5] Michael S. Heutmaker, Duy K. Le, “Architecture for self-test of a wireless communication system using sampled IQ modulation and boundary scan”, IEEE Communications Magazine, Vol. 37, No. 6, pp. 98-102, June 1999.
[6] Madhuri Jarwala, Duy Le, Michael S Heutmaker, “End-to-end test strategy for wireless systems” Proceedings of the IEEE International Test Conference (TC), pp. 940-946, 1995.
[7] N. Nagi, A. Chatterjee, H. Yoon, J. A. Abraham, “Signature analysis for analog and mixed-signal circuit test response compaction”, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 17, No. 6, pp. 540-546, June 1998.
[8] Rajsuman R., “Iddq testing for CMOS VLSI”, Proceedings of the IEEE, Vol.88 No. 4, pp. 544 –568, April 2000.
Fault-Tolerant Design of RF Front end Circuitry
References References (2)(2)
[9] Isern E., Figueras J., “Test generation with high coverages for quiescent current testing of bridging faults in combinational systems”, Proceedings of the International Test Conference, pp. 73 -82, October 1993.
[10] A. Gopalan, T. Das, C. Washburn and P.R. Mukund, “An ultra-fast on-chip BiST for RF CMOS LNAs”, Proceedings of 18th International conference on VLSI Deign, January 2005, pp.485 – 490
[11] J.M.V Santos Dos, J.M.M Ferreira, “Fault-tolerance: new trends for digital circuits” IEEE International Conference on Electronics, Circuits and Systems, Vol 3, Sept.1998 pp. 237 - 240
[12] M. Soma, “Challenges and approaches in mixed signal RF testing” Proceedings of the Tenth Annual IEEE International ASIC Conference, Sept. 1997, pp. 33 – 37
[13] E. Liu, W. Kao, E. Felt, A. Sangiovanni-VIncentelli, “Analog testability analysis and fault diagnosis using behavioral modeling”, Proceedings of the IEEE Custom Integrated Circuits Conference, May 1994, pp. 413 – 416
[14] Yu.V Malyshenko, “Functional fault models for analog circuits”, IEEE Design & Test of Computers, Volume 15, Issue 2, April-June 1998, pp. 80 – 85
[15] Anand Gopalan, P.R.Mukund and Martin Margala, “A Non-Intrusive Self-Test Methodology for RF CMOS Low Noise Amplifiers”, IEEE Mixed-signal Test workshop, Portland, June 2004.
[16] Thomas H. Lee, “The Design of CMOS Radio-Frequency Integrated Circuits”, Cambridge University Press, 1998.
[17] John Ferrario, Randy Wolf, Steve Moss, Mustapha Slamani, “A low-cost test solution for wireless phone RFICs”, IEEE Communications Magazine, v 41, n 9, September, 2003, pp. 82-89
Fault-Tolerant Design of RF Front end Circuitry
Thank You