FATIMA MICHAEL COLLEGE OF ENGINEERING AND …fmcet.in/ECE/EC6302_qb.pdf · · 2014-07-236 D.ANTONYPANDIARAJAN ASST.PROF/ECE UNIT 3 : Design of Sequential Circuits PART –A (2 Marks)

1D.ANTONYPANDIARAJAN ASST.PROF/ECE

QUESTION BANK

UNIT – I: Boolean Functions and Logic GatesPART -A (2 Marks)

1. Convert binary number 11011110 into its decimal equivalent.(AUC MAY 2012)

2. State Demorgan’s theorem. (AUC MAY 2012)

3. Write the application of gray code. (AUC MAY 2012)

4. The solution of the quadratic equation X^2-11x +22=0 is x=3 and x=6. What is thebase of the numbers? (AUC MAY 2012)

5. Map the standard SOP expression on a karnaugh map. (AUC NOV2011) ABC + A B C +ABC +ABC

6. Draw the logic diagram of OR gate using universal gates. (AUC NOV 2011)

7. State De-Morgan’s theorem. (AUC APR 2010)

8. Draw an active-high tri-state buffer and write its truth table. (AUC APR 2010)

9. Prove that the logical sum of all minterms of a Boolean function of 2 variables is 1.(AUC NOV 2009)

10. Show that a positive logic NAND gate is a negative logic NOR gate. (AUC NOV2009)

11. Convert 10002 into gray code and Excess 3 code.(AUC NOV 2008)

12. Simplify the given function : F=A’BC +A’B’C+AB’C’+ABC’+ABC. (AUC NOV 2008)

13. Using 2’s compliment perform the given subtraction 1011012 – 1101002

(AUC NOV 2007)

14. Using Boolean algebra prove x’y + xy’ =x + y (AUC NOV 2007)

15. Convert the binary number 10112 to gray code.(AUC JUNE 2007)

16. Minimize the function using Boolean algebra f=x(y+w’z)+wxz (AUC JUNE 2007)

FATIMA MICHAEL COLLEGE OF ENGINEERING ANDTECHNOLOGY, MADURAI

DEPARTMENT: ECE SEMESTER – III

SUBJECT CODE: EC6302 SUBJECT NAME: DIGITAL ELECTRONICS


PART –B (16 Marks)

1. Convert the following decimal numbers to their hexadecimal equivalent.i)1410 ii) 8010 iii) 300010 iv) 250010 (AUC MAY 2012)Explain the canonical and standard forms of Boolean expression with examples.

2. Elaborate the basic laws of Boolean alzebra with sample. (AUC MAY2012) Write the steps for multiplying a logic expression using akarnaugh map.

3. Implement the switching function F(x,y,z) = ∑m(1,2,3,4,5,7) (AUC MAY 2012)

4. Minimize the expression using Quine Mccluskey(Tabulation) method (AUC MAY2012) Y=A’BC’D’+A’BC’D+ABC’D’+ABC’D+AB’C’D+A’B’CD’

5. Simplify the logic function using Quine –McCluskey method and realize usingNAND gates. (AUC NOV 2011)f(A,B,C,D)=∑m(1,3,5,9,10,11)+∑d(6,8)

6. a) Draw a TTL circuit with totem pole output and explain its working. (AUCNOV 2011)b) With a neat diagram ,explain the operation of CMOS NAND and NOR gates.i) Express the Boolean function as POS form

(1)SOP form D = (A’ + B) (B’ + C) (4)(ii)Minimize the given terms

πM (0, 1, 4, 11, 13, 15) + π d (5, 7, 8) using Quine-McClusky methods andverify the results using K-map methods. (12) (AUC APR 2010)

7. i)Implement the following function using NOR gates. (8) (AUC APR 2010)Output = 1 when the inputs are Σ m(0,1,2,3,4) = 0 when the inputs are Σ m(5,6,7) .

(ii) Discuss the general characteristic of TTL and CMOS logic families.(8)(AUC APR 2010)

8. (a) (i) Express the Boolean function F = XY + XZ in product of Maxterm.(6)9. Reduce the following function using K-map technique ) (AUC NOV 2009)

10. f (A, B, C, D) = π (0, 3, 4, 7, 8, 10, 12, 14) + d (2, 6) . (10) ) (AUC NOV 2009)11. Simplify the following Boolean function by using Quine –Mcclusky method

F(A,B,C,D)= Σ(0, 2, 3, 6, 7, 8, 10, 12, 13)(16) (AUC NOV 2009)12. Simplify the given function using K map F=∑m(1,3,4,5,9,11,12,13,14,15) (AUC NOV

2008)13. List all the prime implicants and draw the logic diagram for the minimized

expression using gates (4) (AUC NOV 2008)14. Solve the given expression using tabular method

F=∑m(0,2,3,6,7,10,12,14,15) (16) (AUC NOV 2008)

15. For the given functions :g(w,x,y,z)=∑m(0,3,4,5,8,11,12,13,14,15). List allprime implicants and find the minimum product of sum expression. (AUCNOV 2007)


16. For the given function f(a,b,c,d)=∑m(0,2,3,6,8,12,15)+∑d(1,5) (AUC NOV 2007)

Find the minimum sum of products expression using Quine –McCluskey method.(AUC NOV 2007)

17. Find the minimum sum of product expression using K map for the function ,

F=∑m(7,9,10,11,12,13,14,15) and realize the minimized function using onlyNAND gates (AUC JUNE 2007)

18. Simplify using Quine Mc Clusky methodF=∑m(0,1,2,3,10,11,12,13,14,15) (AUC JUNE 2007)


UNIT 2 : Design of Combinational Circuits

PART -A (2 Marks)

1. What is tristate logic? What are its demerits? (AUC MAY 2012)

2. State the features of bipolar logic families. (AUC MAY 2012)

3. Draw the logic diagram and give the truthtable of Half subtractor. (AUC MAY2012)

4. What is meant by look ahead carry ? (AUC NOV 2011)

5. Give the logical expression for sum output and carry output of a full adder.(AUC NOV 2011)

6. Write an expression for borrow and difference in a full subtractor circuit.(AUC APR 2010)

7. Draw the circuits diagram for 4 bit Odd parity generator. (AUC APR 2010)

8. Suggest a solution to overcome the limitation on the speed of an adder.(AUC NOV 2009)

9. Differentiate a decoder from a demultiplexer. (AUC NOV 2009)

10. Design a half adder using verilog. (AUC NOV 2008)

11. Draw the logic diagram of a master /slave JK flip flop. (AUC NOV 2008)

12. Draw a 2 input CMOS NOR gate. (AUC NOV 2007)

13. Define fanout of a digital IC. (AUC NOV 2007)

14. What is the advantage of using schottky TTL gate. (AUC JUNE 2007)

15. Define propagation delay. (AUC JUNE 2007)


PART -B (16 Marks)

1. Design Half and Full subtractor circuits (AUC MAY 2012)

2. Design a circuit that converts 8421 BCD code to Excess -3 code. (AUC MAY2012)

3. Design a 2 bit comparator and explain its operation in detail. (AUC NOV 2011)

4. a)Draw the circuit of BCD adder and explain. (AUC NOV 2011)

b)What is priority encoder? How is it different from encoder? Draw the circuit of 4bit priority encoder and explain. (AUC NOV 2011)

5. i)Derive the equation for a 4-bit look ahead carry adder circuit. (6)

(ii)Draw and explain the block diagram of a 4-bit serial adder to add the contents oftwo registers. (10) (AUC APR 2010)

6. Multiply (1011)2 by (1101)2 using addition and shifting operation so draw blockdiagram of the 4-bit by 4 bit parallel multiplier. (8)

Design and implement the conversion circuits for Binary code to gray code. (8)Design a carry look ahead adder with necessary diagrams. (16)(AUC NOV 2009)

7. (i) Implement full subtractor using demultiplexer. (10) (AUC NOV 2009)

(ii) Implement the given Boolean function using 8 : 1 multiplexer

F(A, B, C) = Σ(1, 3, 5, 6) . (6) (AUC NOV 2009)

8. Design a mod 10 synchronous counter and draw the timing diagram of it.(AUC NOV 2008)

9. Design a 4 bit universal shift register and explain its function. (AUC NOV 2008)

10. Design a 4:1 multiplexer using transmission gates and explain its operation.(AUC NOV 2007)

11. Draw a 2 input NAND gate using schotky TTL logic and explain its operation.(AUC NOV 2007)

12. Draw the circuit diagrams of 2 input CMOS NOR gate and CMOS NAND gateusing CMOS logic and explain their operation. (AUC JUNE 2007)

13. What are the different types of TTL gates available? Explain their operationstaking suitable example. (AUC JUNE 2007)


UNIT 3 : Design of Sequential Circuits

PART –A (2 Marks)

1. Draw the logic diagram and give the truth table of Half Subtractor.(AUC MAY 2012)

2. State the principle of parity checker. (AUC MAY 2012)

3. Draw the logic diagram of T flip flop using JK flip flop. (AUC NOV 2011)

4. How can a SIPO register used as a SISO register? (AUC NOV 2011)

5. Mention any two differences between the edge triggering and level triggering.(AUC APR 2010)

6. What is meant by programmable counter? Mention its application. (AUC APR 2010)

7. Write down the characteristic equation for JK flipflop. (AUC NOV 2009)

8. Distinguish between synchronous and asynchronous sequential circuits.(AUC NOV 2009)

9. Differentiate combinational and sequential circuits. (AUC NOV 2008)

10. What is an essential hazard? (AUC NOV 2008)

11. Implement the function f=∑m(0,1,4,5,7) using 8:1 multiplexer. (AUC NOV 2007)

12. Design a half subtractor using 2 to 4 decoder. (AUC NOV 2007)

13. Design a 2 input NAND gate using 2:1 multiplexer. (AUC JUNE 2007)

14. Design a half adder. (AUC JUNE 2007)



1. Implement a fulladder with two 4x1 multiplexers. (AUC MAY 2012)

2. Implement the following function using PLA. (AUC MAY 2012)A(x,y,z)=∑m(1,2,4,6) B(x,y,z)=∑m(0,1,6,7) C(x,y,z)=∑m(2,6)

3. a i) Draw the logic diagram of master slave SR flip flop and explain its workingwith truth table.(10) (AUC NOV 2011)ii) Design a D flip flop using JK flip flop and explain with its truth table.(6)

(AUC NOV 2011)

4. Draw the logic diagram of 4 bit binary up /down synchronous counter and explainwith truth table .Also draw the timing diagram. (AUC NOV 2011)

5. (a) (i) Construct a clocked JK flip flop which is triggered at the positive edge of theclock pulse from a clocked SR flip flop consisting of NOR gates. (4)(ii) Design a synchronous up/down counter that will count up from zero to one totwo to three, and will repeat whenever an external input x is logic 0, and will countdown from three to two to one to zero, and will repeat whenever the external inputx is logic 1.Implement your circuit with one TTL SN74LS76 device and one TTLSN74LS00 device. (12) (AUC APR 2010)

(b) (i)Write down the Characteristic table for the JK flip flop with NOR gates. (4)(ii)What is meant by Universal Shift Register? Explain the principle of Operation of4-bit Universal Shift Register. (12) (AUC APR 2010)

6. i) How will you convert a D flipflop into JK flipflop? (8)(AUC NOV 2009)

ii)Explain the operation of a JK master slave flipflop. (8)(AUC NOV 2009)

7. Explain in detail the operation of a 4 bit binary ripple counter. (16)(AUC NOV 2009)

8. An asynchronous circuit is described by the following excitation and outputfunctions:Y=x1 x2’ +(x1+x2’)y , z=y a) Draw the logic diagramb) Derive the transistion table and output map. (AUC NOV 2008)

9. Differentiate synchronous and asynchronous sequential circuits with examples.(6)(AUC NOV 2008)Write short notes on race conditions in asynchronous sequential circuits and explainhow they can be avoided.(10) (AUC NOV 2008)

10. a)Design a BCD –Excess 3 code converter and implement it using logic gates.(AUC NOV 2007)(8)

b)Design a 4 bit ripple carry adder. (AUC NOV 2007)(12)

11. Design the given functions using PAL and PROM (AUC NOV 2007)F1=∑m(0,1,4,5,7,9,11,13) F2=∑m(1,3,5,6,9,11,14,15)

12. Design 4 bit comparator using logic gates. (AUC JUNE 2007)

13. Implement the given function using PROM and PAL (AUC JUNE 2007)F1=∑m(0,1,3,5,7,9) F2=∑m(1,2,4,7,8,10,11)


UNIT 4 : Memory Devices

PART –A (2 Marks)

1. Mention any four applications of shift registers. (AUC MAY 2012)

2. How does JK flip flop differ from an SR flip flop in its basic operation. (AUC MAY2012)

3. What is the need for output buffer in a PLA system? (AUC NOV 2011)

4. Bring out the difference between fundamental mode and pulse mode sequential circuits.

(AUC NOV 2011)

5. What is meant by memory expansion? Mention its limit. (AUC APR 2010)

6. What are the advantages of static RAM compared to Dynamic RAM? (AUC APR 2010)

7. Compare and contrast static RAM and dynamic RAM. (AUC NOV 2009)

8. What is PAL? How does it differ from PLA? (AUC NOV 2009)

9. How the semiconductor memories are classified? (AUC NOV 2008)

10. Design a D flip flop using verilog. (AUC NOV 2008)

11. Draw the logic diagram of 3 bit ring counter. (AUC NOV 2007)

12. Write the excitation tables of JK and D flip flops. (AUC NOV 2007)

13. Write the characteristic equation of JK FF and show how JKFF can be converted toTFF. (AUC JUNE 2007)

14. Draw the logic diagram of 4 bit universal shift register. (AUC JUNE 2007)


PART –B(16 Marks)1. Design the sequential circuit specified by the state diagram using JK flip flop

(AUC MAY 2012)

2. Draw a 4 bit ripple counter with D flip flop. (AUC MAY 2012)

3. Draw the basic block diagram of PLA device and explain each block. List out itsapplications. Implement a combinational circuit using PLA by taking a suitable Booleanfunction. (AUC NOV 2011)

4. a)Explain the operation of static and dynamic MOS RAM cell with necessarydiagrams.(12) (AUC NOV 2011)

b)What are the advantages of FPGA. (AUC NOV 2011)

5. (a) (i) We can expand the word size of a RAM by combining two or more RAM chips. Forinstance, we can use two 32 × 8 memory chips where the number 32 represents thenumber of words and 8 represents the number of bits per word, to obtain a 32 × 16 RAM.In this case the number of words remains the same but the length of each word will twobytes long. Draw a block diagram to show how we can use two 16 × 4 memory chips toobtain a 16 × 8 RAM. (8) (AUC APR 2010)

(ii) Explain the principle of operation of Bipolar SRAM cell. (8) (AUC APR 2010)

6. (b) (i) A combinational circuit is defined as the functions(AUC APR 2010)F1 = AB’C’+AB’C+ABC

F2 = A’BC+AB’C+ABC

7. i)Implement the digital circuit with a PLA having 3 inputs, 3 product terms, and 2outputs. (8) (AUC APR 2010)

(ii) Write a note on SRAM based FPGA. (8) (AUC APR 2010)

8. (a) Implement the following Boolean functions with a PLA

F1(A ,B ,C ) = Σ(0, 1, 2, 4)F2( A,B ,C ) = Σ(0, 5, 6, 7)F3(A ,B , C) = Σ(0, 3, 5, 7) . (16) (AUC NOV 2009)

9. Design a combinational circuit using a ROM. The circuit accepts a three bit number andoutputs a binary number equal to the square of the input number. (16)(AUC NOV 2009)

10. Draw the logic diagram of Xilinx 4000 CLB and I/O blocks and explain their function.(AUC NOV 2008)

11. Implement the given functions using PROM (AUC NOV 2008)F1=∑m(0,1,3,4,6,7) F2=∑m(1,2,3,5)

12. Design a binary to gray code converter using verilog. (AUC NOV 2008)


13. For the state diagram shown ,design a sequential circuit using JK flip flops

(AUC NOV 2008)

14. Design a synchronous counter which counts in the sequence 0,2,6,1,7,5,0 using Dflip flop. Draw the logic and state diagram. (AUC JUNE 2007)

15. Write short notes on semiconductor memories.(6) (AUC JUNE 2007)Reduce the given state table using implication chart.(10) (AUC JUNE 2007)


UNIT 5 : Synchronous and Asynchronous Sequential Circuits

PART –A (2 Marks)

1. Define Race condition. (AUC MAY 2012)

2. What is meant by essential hazards? (AUC MAY 2012)

3. Give the difference between RAM and ROM. (AUC NOV 2011)

4. What is meant by hazard and how it could be avoided? (AUC NOV 2011)

5. Draw the block diagram for Moore model. (AUC APR 2010)

6. What are hazard free digital circuits? (AUC APR 2010)

7. What are Hazards? (AUC NOV 2009)

8. Compare the ASM chart with a conventional flow chart. (AUC NOV 2009)

9. Implement 2 input XOR gate using NAND-NAND logic. (AUC NOV 2008)

10. List any two advantages of using CMOS logic. (AUC NOV 2008)

11. What are the different types of races that occur in fundamental mode circuits.(AUC NOV 2007)

12. Define cycle in asynchronous sequential circuits. (AUC NOV 2007)

13. What is a hazard in asynchronous sequential circuit. (AUC JUNE 2007)

14. What are the different methods of operation in asynchronous sequential circuits.(AUC JUNE 2007)



1. Design an asynchronous sequential circuit that has 2 inputs X2 and X1 and one output z.When X1=0 ,the output z is O. The first change X2 that occurs while X1 is 1will causeoutput Z to be 1. The output Z will remain 1 until X1 returns to 0. (AUC MAY 2012)

2. Find the circuit that has no static hazards and implement the Boolean functionF(A,B,C,D)=∑m(1,3,5,7,8,9,14,15) (AUC MAY 2012)

3. i)Write short notes on shared row state assignment with an example.(8) (AUC NOV2011)(8) (AUC NOV 2011)

ii)A sequential circuit has 3 D flip flop. A,B and C and one input X. It is desired by thefollowing flip flop functions(8) (AUC NOV 2011)

DA =(BC’+B’C)X +(BC+B’C’)X’ ; DB=A , DC=B

Derive the state table for the circuit and draw two state diagrams for X=0 and other forX=1

4. i)Explain the method to eliminate static hazard in an asynchronous circuit with anexample.(10) (AUC NOV 2011)

ii)Write short notes on verilog.(6) (AUC NOV 2011)

5. (a) For the circuit shown in figure, write down the state table and draw the state diagramand analyze the operation. (16) (AUC APR 2010)

(b) What are called as essential hazards? How does the hazard occur in sequentialcircuits? How can the same be eliminated using SR latches?Give an example.(16)(AUC APR 2010)

6. (a) Design a three bit binary counter using T flipflops. (16) (AUC NOV 2009)

7. (b) Design a negative-edge triggered ‘T flipflop’. (16)(AUC NOV 2009)

8. a) Draw a 2 input NAND gate in TTL logic and explain its operation.(12)(AUC NOV 2008)

b) Write short notes on BICMOS logic. (AUC NOV 2008)

9. a) Design a 2 input NOR gate using CMOS logic. (AUC NOV 2008)b)Write short notes on CMOS logic and interfacing. (AUC NOV 2008)

10. Discuss on the different types of hazards that occur in asynchronous sequential circuits.(AUC NOV 2007)

11. Write short notes on i) race free assignments ii) pulse mode circuits. (AUC NOV 2007)


12. Write short notes on races and cycles that occur in fundamental mode circuits(10) (AUCJUNE 2007)

What is an essential hazard? Explain with example.(6) (AUC JUNE 2007)

13. Explain how hazard free realization can be obtained for a boolean function.(8)(AUC JUNE 2007)Discuss a method used for race free assignments with example.(8) (AUC JUNE 2007)

14

Documents

FATIMA MICHAEL COLLEGE OF ENGINEERING AND …fmcet.in/ECE/EC6302_qb.pdf · · 2014-07-236 D.ANTONYPANDIARAJAN ASST.PROF/ECE UNIT 3 : Design of Sequential Circuits PART –A (2 Marks)