Fast and Accurate System Model of DDR4 and …...Fast and Accurate System Model of DDR4 and addressing the Challenges of Transition to DDR5 CDNLive 2018, SEP 7, Cadence User Conference

Fast and Accurate System Model of DDR4 and addressing the Challenges of Transition to DDR5

CDNLive 2018,SEP 7, Cadence User Conference 2018Bengaluru.

Authors,Prabhakaran PalaniappanShanmugapriya DevadasanBuvaneshwaran Chinnadurai

22018 Copyright Mobiveil Inc.9/10/2018

Agenda

§ Mobiveil overview

§ Challenges of increasing DDRx data rate

§ System Level Simulation Model

§ Field solver comparison and selection

§ Parametric Simulation (PDN, SSO, Crosstalk, ISI)

§ Sign-off Report

§ Correlation with measurement results

§ Conclusion and addressing the challenges of transition to DDR5

Mobiveil Technologies India Private Limited


§ Headquartered in Milpitas, California§ Development centers in Chennai, Bengaluru and

Hyderabad in India§ Over 200+ strong Engineering team§ IP and IP centric solution provider for Select Vertical

Markets§ Product Engineering Services

§ ASIC/FPGA Design Implementation§ SoC Verification / Validation§ Board Design§ Signal & Power Integrity§ CAD Layout Design§ ID / Mechanical Design§ Embedded Software

§ High Speed interconnect IP’s § PCIe Gen 1 to Gen4§ sRIO Gen 1 to Gen 3§ 1G/10G Ethernet MAC

§ IP portfolio towards Storage domain§ NVMe § EFC (Enterprise Flash controller)§ LDPC (Error correction for Storage)§ DDR 4/3 and LPDDR 3/2§ HBM2§ Octa/QSPI, HyperFlash

Listed as one of the fastest growing private companies in US – Source “Inc 5000”


Product line/ services

Storage domain

§ Mobiveil IP : FPGA based High performance storage solution§ NVMSTor (Arria10 FPGA based NVMe SSD) § NVMSTor – Ultra (Zynq Ultrascale + based NVMe SSD)

§ High performance SSD development§ Non-standard DIMM development§ SSD validation products

IOT solutions

§ IOT Solution for smart city initiatives§ Smart lighting control and environmental monitoring IOT solution§ Traffic Management System for Smart City initiative

§ IOT Gateway applications


Challenges of increasing DDRx data Rate & decreasing Voltage § PDN noise

§ Eye mask compliance

§ Simultaneous switching bits

§ ISI and cross talk

§ Deskewing of Data bits (including package + PCB delay)

§ Accurate modelling required to match the package and PCB delay (not the length)

§ Measurement and probing points

Note :§ DDR4 data rate – 1600 to 3200 Mbps, 1.2V § DDR5 data rate – 3200 to 6400 Mbps, 1.1V (expected)


DDR4 System simulation Model : Topology


System SI Simulation topology


S-parameter Extraction

DDR4: § Frequency sweep: 0- 5GHz§ Data rate: 2400MT/s§ Marker at: 1.2GHz (clock frequency)§ Signals considered: 3 DQbits & 1 DQS

Solver: (For frequency domain result comparison)§ Hybrid§ 3DFEM (Using cut & stitch method : Via transition & pads are modeled using FEM)

Port generation

Capacitor Assignment for PDN:

Cut & Stitch


S-parameter result observation

Field solver comparison : Insertion Loss Field solver comparison : Return Loss Field solver comparison : Time domain

Above Plots indicate the difference in insertion loss and return loss due to inclusion of 3DFEM field solver for complex geometries


Simulation Solver Selection

§ Hybrid solver§ Mixed solver: cut & stitch method (Hybrid & 3DFEM)§ FDTD (Finite Difference Time Domain) - Block box representation of board and direct time domain

simulation

§ Main objective of solver selection is to model the complex simulation system, inorder to extract the results with less simulation time with reasonable accuracy.

§ Based on below observation, FDTD solver consumes lesser simulation time (overall) compared to other approach.


Data bus Simulation:


Data bus Write Simulation: With & Without PDN

Eye Height is reduced while considering PDN in the simulation due to power noise inclusion.


Data bus Read Simulation: With & Without PDN

Eye Height is reduced while considering PDN in the simulation due to power noise inclusion.


Data bus Simulation: Simultaneous Switching bitsPower noise due to switching of data bits

Switching of multiple simultaneous bits injects the noise into the power plane which in turn affects other data bits

Effect of SSO on DQ waveform

Effect of SSO on DQ waveform – Eye diagram


Data bus Simulation: Impact of crosstalk

DQ simulation without considering crosstalk effects

Eye Height is reduced due to Crosstalk.

DQ simulation with crosstalk (1 byte simulation, 1DQ-victim, 7- aggressors)


Data bus Simulation: Impact of ISI

ISI : Effect of one bit transition over another

When Data rate goes up to 6400 MT/s (especially for DDR5), effect of ISI will be very significant. Serdes approach needs to be adopted to ensure eye mask compliance with less BER


Sign-off ReportSystemSI generates report with JEDEC standard compliance.


Measurements

Mobiveil’s NVMStor-Ultra PlatformMeasurement Setup : Keysight technologies MSO9254A


Correlation with Measurements: DQ

Simulation results for a 8x data transfer Measurement for a 8x data transfer

Note : Probing point is exactly the same in both Simulation and measurements


Correlation with Measurements: DQS Read

Simulation results for a 8x data transfer Measurement for a 8x data transfer



Correlation with Measurements : Clock

Simulation results for Clock Signal Measurement of Clock signal



Correlation with Measurements : Clock Eye

Simulation results for Clock Signal Measurement of Clock signal



Conclusion & Addressing the Challenges in DDR5 using Sigrity§ As DDRx speeds go up, so is the complexity of system modelling and comprehensive

approach is necessary to get an accurate results

§ Sigrity is geared up to address the key challenges discussed earlier and below are the advantages

§ Ability to model every part of the interconnects (package, BGA pad, Edge fingers, via stub etc)

§ Ability to define the VRM characteristics including voltage ripples (using spice constructs) which is generally system specific.

§ Solver choice:

§ FDTD : Fast and accurate Field solver§ 3D FEM for complex geometries§ Cut and stitch approach

§ Ability to include the effects of following components accurately§ PDN noise§ ISI§ SSO§ Cross talk

§ Adoption of SERDES technique (IBIS-AMI modelling) for DDR5 and beyond


Thank you !

Documents

Fast and Accurate System Model of DDR4 and …...Fast and Accurate System Model of DDR4 and addressing the Challenges of Transition to DDR5 CDNLive 2018, SEP 7, Cadence User Conference