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Farayola Praise Ololade
Pallavi-Sugantha Ebenezer
Buck Converter with PWM Voltage β Mode β Control
May, 2019
Table of Content
Table of content for the project is listed below to make transition between the design blocks
and simulation results easier.
Content Page Number
Introduction -03
Basic Calculations -03
Buck Converter -05
Buffer Design -06
Power Transistor Design -07
Power Inductor and Output Capacitors -10
Comparator Design -10
Ramp and Clock Generator Design -12
Operational Amplifier Design -13
Compensation Network Design -14
Simulations and Measurements -17
Calculations and Efficiency Measurements -23
Conclusion -24
INTRODUCTION:
Having spent most of the semester learning about Buck Converters, it is imperative that we
build one ourselves with real components; hence this final project.
Over the semester, chunks and part of the Buck Converter has already been built. This final
project adds a few blocks to it and brings all the individual part all working together.
In Homework 4, we designed a closed loop Type-III compensated buck converter operating in
CCM and verified the design using the AC model and transient model. In this final project, we
would be replacing all the ideal components used in the design with real transistor level
circuits.
Specification for the Buck Converter to be designed are set and the final design is adjusted to
ensure that the specifications are met.
The specifications for the project are listed below;
Specifications
Technology UMC 0.18ππ (Preferred) ππ 3.3V ( I/O _33_MM devices for UMC 0.19πm )
Inductor ESR 20mΞ©
Capacitor ESR 10mΞ©
Vo ( Steady β State ) ~1.8V Β± 5% ( Load Regulation )
ππππππππ (Steady β State ) <10mV
ππ π€ 1MHz
πΌπ 300mA - 800mA
Vo under / over- shoot <100mV during transient with 10ns step between 300mA and 800mA
Operation CCM only
Efficiency ( Include Everything ) >85%, Higher is better
The project is designed in the UMC 0.18πm process and ALL the specifications were met.
All blocks designed are real but we were allowed to use current bias and voltage references.
(Idc and Vdc) Also the inductors, capacitors and resistors used are ideal. However for the
inductors and capacitors in the power stage to be properly modelled, we put a reasonable ESR
(20mΞ© for the inductor and 10mΞ© for the capacitor)
BASIC CALCULATIONS:
Various calculations are done to pick the value of the components used. They are shown below;
1) Picking the Value of L and C
βππ
ππ=
1 β π·
8πΏπΆβ
1
π2
Where D is the Duty Cycle
π· =ππ
ππ=
1.8
3.3= π. ππππ
π·β² = 1 β 0.5454 = π. ππππ
To pick the value of inductor L so that the inductor ripple current βIL β 300mA
π· = ( ππ
ππ )
π· = ( 1.8
3.3 ) = 0.5454
β πΌπ =ππ
πΏπ·β²π =
ππ
πΏππ π€
(1 β π·)
πΏ =ππ(1 β π·)
βπΌπππ π€
πΏ =1.8(1 β 0.5414)
300π β 1π
π³ = π. ππ ππ―
To pick the output capacitance C so that the output voltage ripple is about 5mV
βππ =(1 β π·)ππ
8πΏπΆπ2
πΆ =(1 β π·)ππ
βππ8πΏπΆπ2
πΆ =( 1 β 0.5454 )1.8
5π β 8 β 2.75π β 1π2
πͺ = π. ππ ππ These values could be adjusted later to reduce voltage or current ripple.
After the design was completed and optimized to meet the specification, the value of C and L
was adjusted. The final value used for L and C are listed below
Inductor (L) 1.365ππ―
Capacitor (C) 7.44ππ
BUCK CONVERTER:
The Buck converter is one of the major switching converters. It employs switching action on one
or more inductors to regulate the output voltage to a predefined value even when the input
voltage ( ππ ππ ππ·π·) or the load current changes.
They are better than LDOβs in the sense that they have better efficiencies which we would show
in this project.
The Buck Converter is made up of the following design blocks.
(i) Driver Stage ( Buffer Design )
(ii) Power Transistor Design
(iii) Power Inductor and Output Capacitors
(iv) Comparator Design
(v) Ramp and Clock Generator
(vi) Operational Amplifier
(vii) Compensation Network
(viii) Digital Logics
Figure 1 Block Diagram of the Buck Converter
DRIVER STAGE AND POWER TRANSISTOR DESIGN
The driver stage has the buffer and the non-overlapping clock generation circuit design.
BUFFER DESIGN
The design of the buffer used is from project 1. Since the power transistors are of large
dimensions, the PWM control signal cannot drive them effectively. Hence the buffer stage is
designed with gradually increasing sizes by each stage to drive the power transistors, starting
with the minimum sized inverters and the largest sized buffer drives the power stage.
Figure 2 Buffer circuit
NONOVERLAPPING CLOCK DESIGN
A feed-back break before make structure is used to design the nonoverlapping clock
generation circuit. This circuit helps turn off the NMOS before PMOS turns on and vice versa.
The resistor helps the NMOS turns on slower and PMOS turns off faster during low to high
transition. Similarly, for high to low transition, the PMOS turns on slower and NMOS turns off
faster. Hence this logic turns off the PMOS completely before the NMOS is turned on. Similarly,
the NMOS is turned off completely before the PMOS is on. The design of these transistors are
also gradually increased as to drive the power stage. This significantly reduces shoot-through
loss.
POWER TRANSISTOR
The sizing of the power transistor is very important. Here they are represented with βMFβ and
sweep is done to give us the best sizing that will guarantee the maximum efficiency. This is
because there is a trade-off between Conduction Loss and Switching Loss.
Figure 5 Power Transistors
To NMOS
To PMOS
Figure 4 Break before Make Circuit
COMBINATION
I/O_33_MM transistors were used as speculated in the instructions and the variable (MF) was
used in the sizing of the power transistors to make it easy to change and sweep.
Other variables were also used like Ratio1, Ratio2, Ratio3, Ratio4, Ratio5 and Ratio6 to break
down the large power transistor sizing for other transistors used in the buffers.
The buffers were designed using a combination of the two methods to minimize shoot through
loss.
Figure 6 Buffer and Power Transistor Design
OPTIMIZATION OF THE POWER TRANSISTOR SIZING
After the entire design, we swept MF (the Sizing of the Power Transistor and ratioed sizing of the
buffers) from 10k to 100K in 10 steps to pick the best sizing for the buck converter.
Buffer Design Power Transistors
Figure 7 Parametric Sweep for MF
Here is the results that we got after sweeping MF
It is observed that at around 10K to 30k, the PVDD power is decreasing and then later starts increasing
back again after 55K. Hence our choice of picking 50k. The PVDD power is observed to be lowest at that
point and the output power is about the same for all the ranges.
Figure 8 Optimization of the Power Transistor Sizing
Hence this is the final result used.
Figure 9 Final values used for the Buffer and Power Transistor used
POWER INDUCTOR AND OUTPUT CAPACITORS
To ensure that our simulation could be as close to the real life situation as possible, we
modelled the inductor having an ESR of 20mΞ© and the capacitor having an ESR of 10mΞ©. This
can be seen clearly from the diagram below as the resistors connected in series to the capacitor
and the inductor.
COMPARATOR DESIGN
The comparator is used to generate the required PWM signal by adjusting D. It compares the
Vramp and Va to generate a signal Vcmp. Vcmp is high if Va is greater in amplitude than Vramp and vice
versa.
Figure 11 Comparator Block
The comparator is designed as shown below; Care was taken in the sizing of the comparator. We made
sure that the ratio of (M25/M24) / (M22/M23) matched with M35/M37 as corrected in Homework3
Figure 10 Power Stage
Figure 12 Comparator Design
The comparator used in this design is a cross coupled NMOS input pair comparator. The
transistors are minimum sized to provide the least propagation delay. The length of the input
pair is made larger to have better matching and thus have reduced offset. The cross coupled
transistors have size smaller than the transistors in the main branch to have hysteresis.
Here are the results of the comparator after test
The propagation delay (td): Td_LH =8.7ns
Td_HL =1.1ns
Hence, Td = Td_LH + Td_HL = 9.8ns (< 10ns)
Figure 13 Transient Simulation of Comparator
RAMP AND CLOCK GENERATOR DESIGN
The double boundary ramp generator is used in this design as shown in Figure 8. It is based on
the Vm which was used in the AC model simulation. The upper boundary is 1.5 V and the lower
boundary is 0.5V. A current of 12uA is generated from the Vref (=1.2 V) using the voltage to
current converter with a resistor of 100kΞ©. This is mirrored to the ramp and clock generation
circuit.
Since the clock required for the design is 1MHz (dt =1us)
The range of the ramp is between the upper and lower boundary (dv =1V)
The capacitor value chosen:
πΌ = πΆππ£
ππ‘
πΆ = πΌ ππ‘
ππ£ = 12u * 1u / 1
C= 12 p F
The capacitor gets charge until the upper boundary until which the NMOS is off. At this point,
the output of both the upper and lower comparators are high. Since the set and reset signals of
the SR latch are high, the output of the latch holds the previous output and hence the NMOS
remains turned off. When the voltage of the comparator hits the upper boundary limit the
output of the upper Comparator is low. Now the reset signal is low and the output of the latch
is high, which turns on the NMOS. The capacitor discharges through the NMOS and ramp signal
gets pulled to ground. When the signal hits the lower boundary, the output of the lower
comparator becomes low and the latch outputs a low signal and turns off the NMOS. The
capacitor is charged up again, thus generating the ramp signal and clock signals at a frequency
of 1MHz.
Figure 14 Ramp and clock generation circuit
The transistor level ramp and clock generation circuit was designed and its performance was
verified as shown in Figure 9.
OPERATIONAL AMPLIFIER DESIGN
A single stage transistor level implementation is shown in the figure below. The gain from this
op-amp is measured to be around 52 dB and with a phase margin of 87 deg. This is good
enough.
Figure 16 Single stage Opamp
Figure 15 Ramp and clock signals
We then went ahead to plot the gain and phase plot of the op amp to show that it is good enough and
can be used in out design.
Figure 17 Stability plot of the op-amp
COMPENSATION NETWORK DESIGN
Type III Compensator is required to have a high system bandwidth and good stability. It helps
provide a fast response with no ringing as the system bandwidth is greater than the LC resonant
frequency
Figure 18 Type III Compensator
How the resistors and capacitors were picked are referenced in Homework 4 as the exact
capacitors and resistors are used.
C1 500p
C2 42p
C3 2p
R2 100k
R3 1k
We then went ahead to plot the gain and phase margin.
It can be observed that the gain margin of the system is 58db and the phase margin of the
system is 63.8 degrees.
DIGITAL LOGIC
The Digital Logic used is a simple SR latch. A simple transistor level minimum sized SR latch has
been designed to provide the PWM signal for the Power transistors.
The schematic of the SR latch is shown below;
Figure 19 Stability plot of the system
Figure 20 SR Latch Circuit
BUCK CONVERTER CIRCUIT
The Entire Buck Converter circuit is shown again with all the block arranged together.
The complete transistor level buck converter has been designed with real amplifiers, ramp and
clock circuit and other logic circuits as shown in Figures above.
Buffer
Nonoverlapping clock
SR Latch
Compensator
Ramp and clock
Comparator
Power stage
Figure 21 Transistor level Implementation of the Buck Converter Circuit
SIMULATION AND MEASUREMENT RESULTS
AC AND TRANSIENT MODEL SIMULATION
We are required to show the AC and Transient Simulation result and proof that the
specifications in the tables are met. The transient and AC model simulations are shown when
the load is 300mA and 800mA; since these are the two extremes, it is observed that they both
meet specifications. For the transient simulation has all things real while the AC simulation uses
the transformer model for the power stage to make simulations faster
At 300mA
Figure 22 Transient Simulations at 300mA to 800mA transition
Figure 23 AC simulation with 300mA to 800mA transition
For better comparison, we go forward to compare the two together especially the output
voltage and current.
Figure 24 AC and Transient Simulation of the Output Voltage
1) It can be observed that at steady state the voltage ripple is (1.802-1.791) which is 9mV.
This meets specification of less than 10mV and β 1.8π Β± 5%
2) For the Transient Simulation, the voltage undershoot is (1.789 β 1.7408 ) which is
48.2mV. The overshoot is (1.8511-1.791) which is 60.1mV. This meets the specification
of the undershoot/overshoot being less than 100mV. It can be seen that the AC
simulation has better results for overshoot and undershoot because of the transformer
model
The Output current of the AC and Transient Model is also plotted together
Figure 25 AC and Transient of Output current
This is amplified and shown below
Hence it proofs that the output current can range from 300mA to 800mA.
The output current ripple is (788.353 β 782.8152) = 5.5mA which is according to specification.
TOP LEVEL / SYSTEM SIMULATIONS
AC FREQUENCY RESPONSE
With the transformer model, we went ahead to plot the AC frequency response to show that
with the compensation network, the design was stable.
Figure 26 AC Frequency Response
From the AC response, it is observed that the Phase margin is 61.8 degree and the gain margin is 34 db.
This also is to specification of the phase margin above 60 degree and the gain margin above 12dB.
Load transient
With real transistors, the transient results with the inductor current is plotted.
Figure 27 Load Transient
AT STEADY STAGE
At Steady State, the inductor current, output voltage and the switching node voltage is shown
more clearly.
Figure 28 At steady State Showing Inductor Current, Output Voltage and Switching Node
This can be seen more clearly
Figure 29 Zoomed in version of the steady state voltages and current
CALCULATIONS AND EFFICIENCY MEASUREMENT
For each of the simulation, the load was changed to match the required output
current.
LOAD REGULATIONS
We are required to calculate the Load Regulations in V/mA of the Buck Converter at load of
300mA, 500mA and 800mA.
πΏπππ π πππ’πππππ =πΆβππππ ππ ππ’π‘ππ’π‘ ππππ‘πππ
πΆβππππ ππ ππ’π‘ππ’π‘ πΆπ’πππππ‘=
βππ
βπΌπ
πΏπππ π πππ’πππ‘πππ =1.800914 β 1.800032
800 β 300= π. πππ β ππβπ π½/ππ¨
EFFICIENCY
We are required to calculate the Efficiency of the Buck Converter at 300mA, 500mA and
800mA.
πΈπππππππππ¦ =ππ’π‘ππ’π‘ πππ€ππ
πΌπππ’π‘ πππ€ππβ 100%
Since we have input power going to the Power Transistor from PVDD and input power going to
the Logic from AVDD, hence the total input power will be an addition of the two.
πΈπππππππππ¦ =ππ’π‘ππ’π‘ πππ€ππ
πππ·π· πππ€ππ + π΄ππ·π· πππ€ππβ 100%
To get the Power Measurements from the Cadence simulation, we integrated and averaged the
Power signal over 80cycles (From 19us to 99us). The input power signal was gotten from the
multiplication of the transient voltage and current signals from the respective voltage source
while the output power signal was gotten from the multiplication of the voltage and current
signals across the load resistor.
A) At 300mA
Figure 30 Power Calculations at 300mA
Figure 31 Waves at 300mA
πΈπππππππππ¦ =538.9
567.3 + 1.072β 100% = 94.8% β ππ%
B) At 500mA
Figure 32 Power Calculations at 500mA
Figure 33 Waves at 500mA
πΈπππππππππ¦ =895.8
944.7 + 1.07β 100% = 94.72% β ππ%
C) At 800mA
Figure 34 Power Calculations at 800mA
Figure 35 Waves at 800mA
πΈπππππππππ¦ =1.429
1.529 + 1.07πβ 100% = 93.39% β ππ%
Contribution of the Project Mates
Since the basic design was common to both of us we went ahead and used Praiseβs design. The
new blocks were designed by Praise and verified by Pallavi. The report and presentation were
made by Pallavi and missed details were provided by Praise.
CONCLUSION
We were able to get the efficiency of the Buck Converter at around 93% for 800mA Load and
around 95% for 500mA and 300mA load. This is well beyond the required specification.
We also observed that the Load regulation was highest with a load of 300mA ( π. ππππ β
ππβπ π½/ππ¨) This reduced down to π. πππ β ππβπ π½/ππ¨ at a load of 800mA.
It is also seen that the power that is consumed by the logic remains pretty the same (1.07mW)
but as the current increases then the power consumption of the power transistors increases in
proportion.
We also observed that the efficiency dropped as the Load Current increased. This agrees with
what we have learnt in class.
It was a nice project and we learnt a lot of things. The course in general was an interesting
course and we look forward to applying the lots of things that we have learnt in areas of
research and other aspects of Life.