Fall 2012 Chapter 2: x86 Processor Architecture. Irvine, Kip R. Assembly Language for x86 Processors 6/e, 2010. 2 Chapter Overview General Concepts IA-32

Fall 2012

Chapter 2: x86 Processor Architecture

Irvine, Kip R. Assembly Language for x86 Processors 6/e, 2010. 2

Chapter OverviewChapter Overview

• General Concepts

• IA-32 Processor Architecture

• IA-32 Memory Management

• Components of an IA-32 Microcomputer

• Input-Output System


General ConceptsGeneral Concepts

• Basic microcomputer design• Instruction execution cycle• Reading from memory• How programs run


Basic Microcomputer DesignBasic Microcomputer Design

• clock synchronizes CPU operations• control unit (CU) coordinates sequence of execution steps• ALU performs arithmetic and bitwise processing


Basic Microcomputer DesignBasic Microcomputer Design

• Memory Storage Unit: primary memory• I/O Devices: Input/Output devices• Data bus: moves data between memory/i/o and registers• Control bus: determines where data comes from and goes, and ALU activities• Address bus: selects where data comes from or goes to an other part

• A computer system usually contains four bus types: data, I/O, control, and address. • The data bus transfers instructions and data between the CPU and memory.

• The I/O bus transfers data between the CPU and the system input/output devices. • The control bus uses binary signals to synchronize actions of all devices attached to the system bus.

• The address bus holds the addresses of instructions and data when the currently executing instruction transfers data between the CPU and memory .


ClockClock

• synchronizes all CPU and BUS operations• machine (clock) cycle measures time of a single

operation• clock is used to trigger events

one cycle

1

0


What's NextWhat's Next

• General Concepts

• IA-32 Processor Architecture

• IA-32 Memory Management

• Components of an IA-32 Microcomputer

• Input-Output System


Instruction Execution CycleInstruction Execution Cycle

• The execution of a single machine instruction can be divided into a sequence of individual operations called the instruction execution cycle

• Before executing, a program is loaded into memory.

• The instruction pointer contains the address of the next instruction. The instruction queue holds a group of instructions about to be executed.

• Executing a machine instruction requires three basic steps:

• Fetch,decode and execute.

• Two more steps are required when the instruction uses a memory operand:

• fetch operand and store output operand. Each of the steps is described as follows:

Instruction Execution CycleInstruction Execution Cycle

• Fetch: The control unit fetches the next instruction from the instruction queue and increments the instruction pointer (IP). The IP is also known as the program counter

• Decode: The control unit decodes the instruction’s function to determine what the instruction will do. The instruction’s input operands are passed to the ALU, and signals are sent to the ALU indicating the operation to be performed.

Fetch operands: If the instruction uses an input operand located in memory, the control unit uses a read operation to retrieve the operand and copy it into internal registers. Internal registers are not visible to user programs.


• Execute: The ALU executes the instruction using the named registers and internal registers as

operands and sends the output to named registers and/or memory. The ALU updates status

flags providing information about the processor state.• Store output operand:

If the output operand is in memory, the control unit uses a write operation to store the data.


Reading from MemoryReading from Memory

• Program throughput is often dependent on the speed of memory access. CPU clock speed might

• be several gigahertz, whereas access to memory occurs over a system bus running at a much slower speed.

• The CPU must wait one or more clock cycles until operands have been fetched from memory before the current instruction can complete its execution.

• The wasted clock cycles are called wait states.



Reading from MemoryReading from Memory

• Multiple machine cycles are required when reading from memory, because it responds much more slowly than the CPU. The steps are:• Cycle 1: address placed on address bus• Cycle 2: Read Line (RD) set low• Cycle 3: CPU waits one cycle for memory to respond• Cycle 4: Read Line (RD) goes to 1, indicating that the data is on the

data bus

Cycle 1 Cycle 2 Cycle 3 Cycle 4

Data

Address

CLK

ADDR

RD

DATA


Cache Memory• computers use high-speed cache memory to hold the most

recently used instructions and data. The first time a program reads a block of data, it leaves a copy

• in the cache. If the program needs to read the same data a second time, it looks for the data in cache.• Level-1 cache: inside the CPU• Level-2 cache: outside the CPU

• Cache hit: when data to be read is already in cache memory• Cache miss: when data to be read is not in cache memory.


How a Program RunsHow a Program Runs


MultitaskingMultitasking

• OS can run multiple programs at the same time.• Multiple threads of execution within the same

program.• Scheduler utility assigns a given amount of CPU time

to each running program.• Rapid switching of tasks

• gives illusion that all programs are running at once

• the processor must support task switching.


IA-32 Processor ArchitectureIA-32 Processor Architecture

• Modes of operation• Basic execution environment• Floating-point unit• Intel Microprocessor history


Modes of OperationModes of Operation

• Protected mode (programs given separate memory areas). The processor prevents programs from referencing memory outside their assigned segments.• (Windows, Linux)

• Real-address mode (implements programming environment of Intel 8086 processor)• native MS-DOS

• System management mode (provides OS)• power management, system security, diagnostics

• Virtual-8086 mode• hybrid of Protected

• each program has its own 8086 computer


Basic Execution EnvironmentBasic Execution Environment

• Addressable memory• General-purpose registers• Index and base registers• Specialized register uses• Status flags• Floating-point, MMX, XMM registers


General-Purpose RegistersGeneral-Purpose Registers

CS

SS

DS

ES

EIP

EFLAGS

16-bit Segment Registers

EAX

EBX

ECX

EDX

32-bit General-Purpose Registers

FS

GS

EBP

ESP

ESI

EDI

Named storage locations inside the CPU, optimized for speed.


Accessing Parts of RegistersAccessing Parts of Registers

• Primarily used for arithmetic and data movement• Use 8-bit name, 16-bit name, or 32-bit name• Applies to EAX, EBX, ECX, and EDX


Index and Base RegistersIndex and Base Registers

• Some registers have only a 16-bit name for their lower half:


Some Specialized Register Uses Some Specialized Register Uses (1 of 2)(1 of 2)

• General-Purpose• EAX – accumulator• ECX – loop counter• ESP – stack pointer• ESI, EDI – index registers• EBP – extended frame pointer (stack)

• Should not be used for arithmetic or data transfer

• Segment• CS – code segment• DS – data segment• SS – stack segment• ES, FS, GS - additional segments



Some Specialized Register Uses Some Specialized Register Uses (2 of 2)(2 of 2)

• EIP – instruction pointer• Contains address of next instruction to be executed

• EFLAGS• status and control flags

• each flag is a single binary bit

• A flag is set when it equals 1; it is clear (or reset) when it equals 0


Status FlagsStatus Flags• Carry

• unsigned arithmetic out of range• Overflow

• signed arithmetic out of range• Sign

• result is negative• Zero

• result is zero• Auxiliary Carry

• carry from bit 3 to bit 4• Parity

• sum of 1 bits is an even number

• MMX RegistersMMX technology was added onto the Pentium processor by Intel to improve the performance of advanced multimedia and communications applications. The eight 64-bit MMX registers support special instructions called SIMD (Single-Instruction, Multiple-Data). As the name implies,MMX instructions operate in parallel on the data values

• contained in MMX registers.


Documents

Fall 2012 Chapter 2: x86 Processor Architecture. Irvine, Kip R. Assembly Language for x86 Processors 6/e, 2010. 2 Chapter Overview General Concepts IA-32