fairchildcomboAN-42009

7/31/2019 fairchildcomboAN-42009

1/10

Application Note AN42009 (ML AN33)ML4824 Combo Controller Applications

www.fairchildsemi.com

REV. 1.0.3 2/5/02

General Description

This Application Note shows the step-by-step process to

design a high performance supply. The equations shown in

this document can also be used for different output voltages

and total power.

The complete power supply circuit shown in Figure 6 dem-

onstrates the ML4824s ability to manage high output power

while easily complying with international requirements

regarding AC line quality. The PFC section provides 380VDC

to a dual transistor current-mode forward converter. The out-

put of the converter delivers +12V at up to 16 amps. The cir-cuit operates from 80 to 264VAC with both power sections

switching at 100kHz.

The PFC Stage

Powering the ML4824

The ML4824 is initialized once C30 is charged to 13V

through R27 and R30 . PFC switching action now boosts the

voltage on C5 to 380V via T1s primary inductance. T1 then

supplies a well regulated 13V for the ML4824 from its sec-

ondary winding and full wave rectifier consisting of D3 , D4 ,

C10 and C11 . T1s primary to secondary turns ratio (NPRI /

NSEC ) is 25.5:1. For proper circuit operation, high fre-

quency bypassing with low ESR ceramic or film capacitors

on VCC and VREF is provided. Orderly PFC operation uponstart-up is guaranteed when D2 quick charges the boost

capacitor to the peak AC line voltage before the boost switch

Figure 1. The PFC Stage

AC INPUT

80 TO 264V

C1

Z1

Z2

Z3

Z4

R5

1

2

3

4

5

6

7

8

16

15

14

13

12

11

10

9

IEAO

IAC

ISENSE

VRMS

SS

VDC

RAMP1

RAMP2

VEAO

VFB

REF

VCC

VO1

VO2

GND

ILIM

ML4824

C6

C7

R12

D8 D10

D9C13 C14 C15 C16 C30

R11

C8 C9

CT

RT R10

C19

R4C2

R3

C3

R2

R1

R27

D2

D4

T1

D3

C10

C11

+

R30 R21

Q1

D1

C4 C5

R7

R8

R19

C17

C12

+

+


2/10

AN42009 APPLICATION NOTE

2

REV. 1.0.3 2/5/02

Q1 is turned on. This ensures the boost inductor current is

zero before PFC action begins. The value of the regulated

voltage on C5 must always be greater than the peak value of

the maximum line voltage delivered to the supply.

Because the ML4824 uses transconductance amplifiers the

loop compensation networks are returned to ground (see the

ML4824 data sheet for the error amplifier characteristics/

advantages). This eliminates the interaction of the resistive

divider network with the loop compensation capacitors per-

mitting a wide choice of divider values chosen only to mini-

mize amplifier offset voltages due to input bias currents. For

reliable operation R7 must have a voltage rating of at least

400 volts.

Calculate the resistor divider ratio R7/R8.

Selecting the Power Components

The ML4824 PFC section operates with continuous inductorcurrent to minimize peak currents and maximize the avail-

able power. The inductance value required for continuous

current operation in the typical application is found in

equation 3.

The boost diode D1 and switch Q1 are chosen with a reverse

voltage rating of 500V to safely withstand the 380V boost

potential. The average and peak currents respectively

through these components are:

The boost capacitor value is chosen to permit a given output

voltage hold-up time in the event the line voltage is suddenly

removed.

Where:

tHLD = hold-up time (sec)

VC5(MIN) = minimum voltage on C5 at which the PWM

stage can still deliver full output power

A key advantage of using leading/trailing edge modulation is

that a large portion of the inductor current is dumped

directly into the load (PWM stage transformer) and not theboost capacitor. This relaxes the ESR requirement of the

boost capacitor. For reference, equation 7 should be used as a

starting point when choosing C5s maximum ripple current

rating (at 120Hz).

Selecting the Power Setting Components

The maximum average power delivered by the PFC stage is

easily set using the following procedure:

1. Find the resistive divider ratio that results in the voltage

at the VRMS pin being equal to 1.20V at the lowest line

voltage. The voltage at this pin must be well filtered and

yet able to respond well to transient line voltage

changes.

V V

V

V V use V

C RMS MAX

C

C

5

5

5

2

1 414 264

373 380

>

>

>

( )

( . )( )(1)

R

R

V

R

R

R

R

C7

8

5

7

8

7

8

2 5 01

380

2 51

151

=

=

=

.

.(2)

TV

f P

T

T m H use mH

PRIRMS MAX

PFC OUT

PRI

PRI

12

12

5

1

0 445

0 445 264

1 10 200

1 5 5 1 5

( )( )

( )

( )

.

( )( )

( . )( )

( )( )

. .

=

=

=

(3)

IP

V

I

I A

AVGOUT

RMS MIN

AVG

AVG

=

=

=

2 2

3 1416 200

2 1 414 80

2 7 8

( )

( . )( )

( )( . )( )

.

(4)

II

I

I A

PEAKAVG

PEAK

PEAK

=

=

=

2

3 1416 2 78

2

4 3 7

( . )( . )

.

(5)

CP t

V VOUT HLD

C NOM C MIN5

5 2 5 2

2

( )( )

( ) ( )(6)

II

RMS COUT C

( )( )

55

2= (7)

I IPEAK RMS C=( )2 5( ) (7a)

R

R VTOT RMS MIN

4 1 2 0

2 2= .

( )

(8)


3/10

APPLICATION NOTE AN42009

REV. 1.0.3 2/5/02 3

The resistor and capacitor values in the typical example were

found empirically to offer the lowest ripple voltage and still

respond well to line voltage changes. Should a ratio be

required which is greatly different from that found in

equation 8, adjust the filter capacitor values according to

equations 9 and 10.

Where:

f1 = 15Hz, f2 = 23Hz

RTOT = R2 + R3 + R4

2. Find the constant of proportionality km of the multiplier

gain k in equation 11a. To obtain brown-out action

below the lowest input voltage the maximum gain of the

multiplier must be used when finding kM. The maxi-

mum gain (0.328) occurs when the VRMS input of the

multiplier is 1.20V. Equation 11(ref) is the general

expression for the multiplier gain versus the line

voltage.

3. Now select the value of R1 which permits the greatest

multiplier output current without saturating the output.

The maximum output current of the multiplier is 200A.

4. Selecting the value of the current sense resistor com-

pletes the calculations for the power setting compo-

nents.

Where:

RMULO = multiplier output termination resistance (3.5k)

Voltage Loop Compensation

Maximum transient response of the PFC section, without

instability, is obtained when the open loop crossover fre-

quency is one-half the line frequency. For this application the

compensation components (pole/zero pair) are chosen so that

the closed loop response decreases at 20dB/decade, crossing

unity gain at 30Hz, then immediately decreasing at 40dB/

decade. The error amplifier pole is placed at 30Hz and an

effective zero at one-tenth this frequency or 3Hz. First find

the crossover frequency (GPS = 1) of the power stage. Forreference, equation 15 finds the power stage pole, equation

16 the power stage DC gain.

Figure 2. Voltage Amp Compensation

C Rf R R R

TOT31 2 3 42

= + ( ) (9)

C

R R

R R R

f R

TOT

2

4

2 3 4

2 4

1

2=

++

( )

(10)

kk

VrefM

RMS

=2

( ) (11)

k k V

k

k

M RMS MIN

M

M

=

=

=

( )

( . )( )

2

20 328 80

2099

(11a)

Rk V V

R

R k use M

RMS MI N EAO1 6

1 6

1

2 1 5

200 10

0 328 2 80 6 8 1 5

200 10

983 1

( ) ( . )

( . ) ( )( . . )

(12)

RR V k

R P

R

R use

MULO EAO M

OUT5

1

5 6

5

1 5

3500 6 8 1 5 2099

1 1 0 200

0 195 0 15

( . )

( )( )

( ) ( . . )( )

( )( )

. .

(13)

VBOOST

15

R7

R8

+2.5

16

C8

C9R11

VEAO

FB

fP

V V C

f

f Hz

CIN AVG

C EAO MAX

C

C

=

=

=

( )

( )

( )( . )( )( . )( )

.

2

200

2 3 1416 380 5 3 270 10

58 5

5 5

6

(14)

fR C

f

f Hz

P

L

P

P

=

=

=

1

1

3 1416 722 270 10

1 63

5

6

( . )( )( )

.

(15)


4/10


4

REV. 1.0.3 2/5/02

Where:

Now the gain of the power stage at 30Hz is calculated.

The power stage gain will be attenuated by the resistive

divider R7/R8 according to equation 18.

The amount of error amplifier gain required to bring the open

loop gain to unity at 30Hz is the negative of the sum of the

power stage plus divider stage gain (attenuation):

The value of R11, which sets the high frequency gain of the

error amplifier, can now be determined.

Calculate C8 which together with R11 sets the zero frequency

at 3Hz.

Since the pole frequency is ten times the zero frequency the

pole capacitor C9 will be one-tenth the value of C8.

Current Loop Compensation

The current loop is compensated exactly like the voltage

loop with the exception of the choice of the open loop cross-

over frequency. To prevent interaction with the voltage loop,

the current loop bandwidth should be greater than ten times

the voltage loop crossover frequency but no more than one-

sixth the switching frequency or 16.7kHz. The power stage

crossover frequency is found in equation 23, the pole fre-

quency in 24 and for reference the power stage DC gain is

found in equation 25.

Figure 3. Current Amp Compensation

RV

PL

C

OUT

= 52

Gf

f

G

PS DCC

P

PS

GPS

DC

DC

( )

( )

( )

( . )( . )

( . )

=

=

=

2

1 414 58 5

1 63

50.1(34.1dB)

(16)

Gf

G

G

PS HzC

PS Hz

PS Hz

( )

( )

( )

.

30

30

30

30

58 5

30

1.95 (5.8dB)

=

=

=

(17)

GR

R R

G

G

RDIV

RDIV

RDIV

=+

=+

=

8

7 8

3

2 37

357 2 37

6.59 10

( . )

( . )

(43.6dB)

(18)

G G G

G

G

EA PS RDIV

EA

EA

= +

= +

=

( )

( . ( . ))

( )30

5 8 43 6

37.8dB (77.6V / V)

(19)

RG

g

R

R

EA

M11

11 6

11

77 6

85 10

915K use 910K

=

=

=

.

(20)

CR f

C

C nF use nF

Z8

11

8

8

1

2

1

2 3 1416 3

58 56

=

=

=

( )( . )(910K)( )

( )

(21)

CC

C

C

98

99

9

10

56 10

10

5.6nF

=

=

=

(22)

10

+

R5

C6

IEAO

3.5K

GND

3.5K

ISENSE3

IAC

VEAO

R12

C7

14

VREF

1


5/10


REV. 1.0.3 2/5/02 5

Find the gain of the power stage at 16.7kHz.

The current loop contains no attenuating resistors so proceed

to find the error amplifier gain in equation 27.

Now determine the value of the current error amplifier set-

ting resistor R12.

Calculate the value of C6 to form the zero at 1.6kHz.

The pole capacitor C7 is one-tenth the value of C6.

The PWM Stage

Soft-Starting the PWM Stage

The ML4824 features a dedicated soft-start pin for controlling

the rate of rise of the output voltage and preventing overshoot

during power on. The controller will not initiate soft-start

action until the PFC voltage reaches its nominal value thereby

preventing stalling of the output voltage due to excessive PFC

currents. Furthermore, PWM action will be terminated in the

event that the ML4824 loses power or if the PFC boost voltage

should fall below 228VDC. The soft-start capacitor value

(C19) for 25ms of delay is found in equation 31.

Setting the Oscillator Frequency

There are two versions of the ML4824. The ML4824-1

where the PFC and PWM run at the same frequency and

ML4824-2 where the PWM stage is 2X PFC frequency.

ML4824-1

In general it is best to choose a small valued capacitor C1 to

maximize the oscillator duty cycle (minimize the C1 dis-

charge time). Too small a value capacitor can increase the

oscillators sensitivity to phase modulation caused by stray

field voltage induction into this node. For the practical exam-

ple a 470pF capacitor was first chosen for C1. Equation 32 is

accurate with values of R1 greater than 10k.

fR V

T V

f

f kHz

CC5

PRI RAMP

C

C

P P

=

=

=

5

1

3

2

0 15 380

2 3 1416 1 5 10 2 5

2 42

( ) ( )

( . )( )

( )( . )( . )( . )

.

(23)

fR C

f

f Hz same as equation

PL

P

P

=

=

=

1

1

3 1416 722 270 10

1 63 15

5

6

( . )( )( )

.

(24)

Gf

f

G

G 66.4dB

PS DCC

P

PS DC

PS DC

( )

( )

( )

( . )( . )

( . )

( )

=

=

=

2

1 414 2 42 10

1 63

2099

3

(25)

Gf

G

G (16.8dB)

PS kHzC

PS kHz

PS kHz

( . )

( . )

( . )

.

.

.

16 7 3

16 73

3

16 71

16 7 10

2 42 10

16 7 10

1.45 10

=

=

=

(26)

G G

G

G 16.8dB (6.9V / V)

EA PS kHz

EA

EA

=

=

=

( )

( . )

( . )16 7

16 8(27)

R Gg

R

R k use k

EA

m12

12 6

12

6 9

195 10

35 4 36

=

=

=

.

.

(28)

CR f

C

C nF use nF

Z6

12

6 3 3

6

1

2

1

2 3 1416 36 10 1 67 10

2 6 2 7

=

=

=

( )( . )( )( . )

. ( . )

(29)

CC

C

C pF

76

79

7

10

2 7 10

10

270

=

=

=

.(30)

C t

C

C F

SS196

19

6

19

50 10

1 2 5

0 02550 10

1 2 5

1

=

=

=

( ).

( . ) .

(31)

Rf C

R

R

TSW T

T

T

1

0 51

1

0 511 10 470 10

41.2k

5 1 2

.

. ( )( ) (32)


6/10


6

REV. 1.0.3 2/5/02

Figure 4. The PWM Stage

1

2

3

4

5

6

7

8

16

15

14

13

12

11

10

9

IEAO

IAC

ISENSE

VRMS

SS

VDC

RAMP1

RAMP2

VEAO

VFB

REF

VCC

VO1

VO2

GND

ILIM

ML4824

C6

C7

R12

D8 D10

D9C13 C14 C15 C16 C30

R11

C8 C9

CT

RT R10

C19

R19

C17

C20

R15

C25

R16

T3

R17

D7

D6

R18

R20

Q3

Q2

D5

T2

D11C24 C21

L1

R24

C22R23

R22

R26

C23

SR1R25

VOUT+12V, 16A

R14

U2

+

+

+

ML4824-2

The ML4824-2 allows the user to operate the PWM stage at

twice the PFC frequency, thereby reducing the physical size

of the PWM stage magnetics and filter components. The PFCfrequency is the same as the external oscillator frequency.

The PWM frequency is formed by comparing the oscillator

ramp voltage to internal voltage references which ideally

make the duty cycle of the 2 waveforms generated during

each oscillator cycle identical. The PWM section duty cycle

must be balanced to minimize phase jitter. This is accom-

plished by making the oscillator dead-time (C1 discharge

time) equal to 2.5% of the total period. First choose the C1

value from equation 33.

Now R1 is found from equation (34) which is identical to

equation 32.

As a final test, an in-circuit check of 2 adjacent PWM cycles

should be examined for duty cycle balance. For more detail

involving duty cycle balancing please refer to Application

Note 34.

Current Limit

The PWM power stage operates in current mode using R20 to

generate the voltage ramp for duty cycle control. The

ML4824 limits the maximum primary current via an internal1V comparator which when exceeded terminates the drive to

the external power MOSFETs. Maximum primary current is:

Voltage Mode (Feed-Forward)

Should voltage mode control be used it is necessary to know

C5s peak voltage in order to choose the correct ramp gener-ating components. Equation 36 finds the worse case peak to

peak ripple voltage across C5. To find the peak voltage divide

the ripple voltage by two and add it to the regulated boost

voltage. Remember that since the ML4824 employs leading/

trailing modulation the actual peak to peak ripple voltage

will generally be much less than the calculated value.

Cfsw

T 0 025

490

.(33)

RfswC

TT

10 51.

(34)

IR

I

I Amps

PRI MAX

PRI MAX

PRI MAX

( )

( )

( )

.

=

=

=

1

1

0 5

2

20

(35)

V If C

ESR CR C OUT CL

( ) ( ) ( )5 55

2

521

4=

+

(36)


7/10


REV. 1.0.3 2/5/02 7

Where:

fL = line frequency

Solve equation 37 for the ramp resistor value. The ramp

capacitor value should be in the range of 470pF 10000pF.

Choose a resistor with an adequate voltage rating to with-

stand the boost voltage.

Where:

(MAX) = maximum PWM duty cycle (0.45 for the ML4824-1)

VR = peak to peak boost capacitor ripple voltage (equation 36)

The Power Transformer Turns Ratio

The minimum output voltage at the secondary of T2 is found

in equation 38.

The secondary voltage was chosen to be 30 volts to increase

the output voltage hold up time. The transformer turns ratio

is easily found from equation 39.

The maximum secondary current with the output shorted is

limited by equation 40.

The output inductor and rectifier were chosen with maxi-

mum current ratings larger than the maximum secondary

current.

Output Filter Component Filter Selection

L1s value was chosen to efficiently minimize output ripple

current thereby easing the ESR requirement of the filter

capacitor. C21s ESR value is the dominant contributor to theoutput ripple. The maximum ESR value required is found in

equation 41.

Where:

VR = peak to peak output ripple voltage

Output Voltage Compensation

A LM431 shunt regulator SR1 and opto-isolator U2 performoutput voltage setting and regulation. The opto crosses the

primary to secondary safety boundary varying the voltage on

the VDC pin to keep the output voltage constant against line

and load changes. Using current mode control simplifies

loop compensation leaving only a single pole and zero in the

output stage. The pole is created from the output capacitor

and equivalent load resistance. The zero is formed from the

filter capacitor and its ESR. In this example, the action of the

zero occurs well after the closed loop response has crossed

unity, so it was not compensated with a pole. The output pole

is canceled increasing the overall bandwidth by the addition

of R26 and C23 which form a zero with LM431. For more

information on using the LM431, including gain/phase ver-

sus frequency characteristics, please refer to the TexasInstruments Linear Data Handbook.

3.3V Output Design Changes

The latest microprocessors and support circuitry require a

3.3V supply for proper operation. The ML4824 is ideal for

these applications including the energy efficient, ecologi-

cally friendly Green PCs. If the total output power

required varies greatly from 200 watts it will be necessary to

re-select certain components beginning with the PFC stage.

T2s turn ratio must be adjusted according to equation 39 and

another low current secondary winding added using the same

turns ratio as originally found for the +12 volts. This second

winding is necessary to power the LM431/opto circuit as the3.3V output is not adequate to fully bias the feedback cir-

cuitry. C21 may be increased to reduce the output ripple volt-

age. The figure below displays a 3.3V output stage capable

of supplying 16 amps.

R

C f nV

V 0.5V

RAMPMAX

RAMP SWREF

C R

=

+

( )

1 15

(37)

VV

V

V

V Volts

SEC MINOUT

MAXF

SEC MIN

SEC MIN

( )( )

( )

( )

..

.

= +

= +

=

12

0 451 0

27 7

(38)

N

N

V

V

N

N

N

N

PRI

SEC

C

SEC MIN

PRI

SEC

PRI

SEC

=

=

=

5

380

30

38 3

( )

:

(39)

II N

N

I

I Amps

SEC MAXPRI MAX PRI

SEC

SEC MAX

SEC MAX

( )( )

( )

( )

( )( )

.

=

=

=

2 38

3

25 3

(40)

ESRV

VC

RL1 fSW

SEC MAX( )

( )21 (41)


8/10


8

REV. 1.0.3 2/5/02

Figure 5. 3.3V Output Stage

Note: For more information see Application Note 34.

T2

D11

C24 C21

L1

C22

R23

R2210.2K

R26

C23

SR1

LM431R25

31.6K

VOUT+3.3V, 16A

U2

F4001


9/10

REV.1.0.32/5/02

9

Figure6.Complete200WCircuit

AC INPUT80 TO 264V

C1

Z1

Z2

Z3

Z4

R5

1

2

3

4

5

6

7

8

16

15

14

13

12

11

10

9

IEAO

IAC

ISENSE

VRMS

SS

VDC

RAMP1

RAMP2

VEAO

VFB

REF

VCC

VO1

VO2

GND

ILIM

ML4824

C6

C7

R12

D8 D10

D9C13 C14 C15 C16 C30

R11

C8 C9

CT

RT R10

C19

R4C2

R3

C3

R2

R1

R27

D2

D4

T1

D3

C10

C11

+

R30 R21

Q1

D1

C4 C5

R7

R8

R19

C17

C12

+

C20

R15

R20

Q3

Q2

D5

R14

+


10/10


2/5/02 0.0m 001Stock#AN30000056

2002 Fairchild Semiconductor Corporation

DISCLAIMER

FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANYPRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANYLIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHERDOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS.

LIFE SUPPORT POLICYFAIRCHILDS PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICESOR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTORCORPORATION. As used herein:

1. Life support devices or systems are devices or systemswhich, (a) are intended for surgical implant into the body,or (b) support or sustain life, or (c) whose failure to performwhen properly used in accordance with instructions for useprovided in the labeling, can be reasonably expected toresult in significant injury to the user.

2. A critical component is any component of a life supportdevice or system whose failure to perform can bereasonably expected to cause the failure of the life supportdevice or system, or to affect its safety or effectiveness.

www.fairchildsemi.com

Documents

fairchildcomboAN-42009