FACULTY OF MEDIA, INFORMATION &COMMUNICATION TECHNOLOGY

MICROPROCESSORS 700

YEAR 3 SEMESTER 2

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Registered with the Department of Higher Education as a Private Higher Education Institution under the Higher Education Act 1997. Registration Certificate No. 2000/HE07/008

FACULTY OF MEDIA INFORMATION AND COMMUNICATION TECHNOLOGY

LEARNER GUIDE

MODULE: MICROPROCESSORS 700 (2ND SEMESTER)

AUTHOR: Mr Blessing Chibamu Matanyaire

EDITOR: Mr Caston Zimunhu

FACULTY HEAD: Mr. Isaka Reddy

Copyright © 2016

RICHFIELD GRADUATE INSTITUTE OF TECHNOLOGY (PTY) LTD Registration

Number: 2000/000757/07

All rights reserved; no part of this publication may be reproduced in any form

or by any means, including photocopying machines, without the written

permission of the Institution.

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LESSON PLAN ALIGNED TO MOBILE CONTENT [MO ODLE]

Section Subject Matter BSc IT

Page No

1 MICROPROCESSORS

1.1 Introduction to Microprocessors Lesson 1 4

1.2 8085 Microprocessor

Lesson 2

8

1.2.1 Interrupts 10

1.3 8085 Microprocessor Architecture Lesson 3 14

1.3.1 Memory

Lesson 4

14

1.3.2 Registers 15

1.4 Instruction Set Lesson 5 16

1.5 Addressing Modes Lesson 6 16

1.6 Internal Architecture

Lesson 7

17

1.7 8085 Microprocessor System Bus 20

1.8 8085 Programming Model Lesson 8 29

1.9 Instruction Set Classification

Lesson 9

32

1.9.1 Data Transfer Operations 32

1.9.2 Arithmetic Operations 33

1.9.3 Logical Operations 33

1.9.4 Branching Operations 34

1.9.5 Machine Control Operations 34

1.10 Levels of Programming Languages Lesson 10 42

2 8086 MICROPROCESSOR ASPECTS

2.1 Properties of 8086 Microprocessor Lesson 11 46

2.2 8086 Internal Architecture Lesson 12

47

2.2.1 Bus Interface 48

2.2.2 Execution Unit 49

2.3 Maximum and Minimum Modes Lesson 13 49

2.4 Signal Description Lesson 14 50

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3 MICROCONTROLLERS

3.1 Introduction to Microcontrollers

Lesson 15

55

3.2 The Controller 56

3.3 Embedded Systems Lesson 16 57

3.4 Microprocessors versus Microcontrollers Lesson 17 58

3.5 The 8051 Standard Lesson 18 59

3.6 Pin Description

Lesson 19

60

3.7 Input/ Output Ports 60

3.8 Memory Organisation Lesson 20 66

3.9 Special Function Registers (SFRs) Lesson 21 71

3.10 Universal Asynchronous Receiver Transmitter (UART) Lesson 22 81

INTERACTIVE ICONS USED IN THIS LEARNER GUIDE

Learning Outcomes

Study

Read

Writing Activity

Think Point

Research

Glossary

Key Point

4

Review Questions

Case Study

Bright Idea

Problem(s)

Web

Resource

Multimedia Resource References Worked Example

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TOPIC ONE | MICROPROCESSORS

LEARNING OUTCOMES

1. Demonstrate a sound understanding of Microprocessors.

2. Demonstrate an understanding of the 8085 microprocessor Architecture.

3. Demonstrate a sound understanding of the Instruction set

4. Demonstrate the ability to write programs in the 8085 microprocessor

1.1 Introduction to Microprocessors

Microprocessor is a single chip CPU which is use to perform arithmetic and

(Logical Unit) or calculation on the given data. The data will be provided by any

input device and result will be given to any output device. Microprocessor has

no uses unless and until interface with input or output device.

The Microprocessor is the most important chip in any system. It's considered

to be the brain of the computer. Microprocessor is an Integrated Circuit (IC)

which has only the CPU inside them i.e. only the processing powers such as

Intel’s Pentium 1,2,3,4, core 2 duo, i3, i5 etc. These microprocessors don’t have

RAM, ROM, and other peripheral on the chip. A system designer has to add

them externally to make them functional. Application of microprocessor

includes Desktop PC’s, Laptops, notepads etc.

History of Microprocessors

The first microprocessor was introduced in

1970 by Intel (named 4004). It ran at the

speed of 108 KHz. Four years later, Intel

created the 8080 running at just over 2

MHz. This microprocessor was used on the

world's firs personal computer, named

Altair. Motorola created their 68000 series

of microprocessors in 1979. These were

implemented later in the Macintosh

computer by Apple. Another significant

role was held by Sun Microsystems when

introducing Sparc (Scaleable Processor) in

RESEARCH

Go on the Internet and find

the definition of a

microprocessor. What is it

made up of and what is its

function?

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1987. This generation of microprocessors used RISC (Reduced Instruction Set)

making the processing operations faster.

How Microprocessors Operate

Regardless of their speed or physical form they have, the operation that most

of the microprocessors do is to execute a sequence of stored instructions.

Devices running according to the Von Neumann's architecture work in four

steps: fetch, decode, execute and write.

Figure 1.1 How the microprocessor works

Fetching involves getting an instruction from the program memory. An

instruction is represented typically by a sequence of numbers (e.g. 101000101).

This fetching operation forced researching for better memory technologies; the

memory was slow enough to make the microprocessor's power unusable. The

next step is to decode the information, by breaking it into process able parts.

Every part of the information goes to a portion of the CPU that can process it.

This choice is made by considering the opcodes, and indicator posted before

the information that signals what operation is needed (e.g. addition).

Executing involves connecting various portions of the CPU together to serve the

desired operation. Different schemes and connections between the parts form

logical circuits that perform and act after Boolean rules. For example if a

multiplication must be processed, the ALU (Arithmetic Logical Unit) will be

linked with an Input and an Output address.

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The final part, writing, takes place after the processing (execution) was

completed. It involves writing the results to a memory address given by a

memory addressing scheme.

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As far

as the

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physical layout, microprocessors are usually connected to the motherboard

through a socket using a PGA (Pin Grid Array).

Figure 1.2: Removing or Adding a Microprocessor

Removing or adding a microprocessor can be an easy and safe operation if one

knows what he is doing. It has a system called ZIF (Zero Insertion Force) that

protects the processor's pins. As a caution, just remember to try not to touch

the golden pins when working with a processor. After inserting it, it's wise to

use a drop of thermal conductor paste between the microprocessor and a heat

sink, to allow thermal transfer in the best conditions possible. Overheating due

to heavy usage with poor ventilation will make the system instable and can

harm it permanently.

Figure 1.3: Older versions of the Intel Pentium generation

These types of processors usually had no ventilation, since their surface was

large enough to cool itself. In the 1990s, when both slot and socket were used,

some adapters also appeared on the market, like slot card with socket.

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Figure 1.4: Integrated Circuit

Microprocessor incorporates most or all of the functions of a central processing

unit (CPU) on a single integrated circuit (IC). The first microprocessors emerged

in the early 1970s and were used for electronic calculators, using BCD

arithmetic on 4-bit words. Other embedded uses of 4 and 8-bit

microprocessors, such as terminals, printers,

various kinds of automation etc., followed

rather quickly. Affordable 8-bit

microprocessors with 16-bit addressing also

led to the first general purpose

microcomputers in the mid-1970s.

Processors were for a long period THINK POINT constructed out of small

and medium-scale The processor is often ICs containing the equivalent of a few

to a referred to as the brain of the few hundred transistors. The integration of

computer. In what ways does the whole CPU onto a single VLSI chip the human

brain and the therefore greatly reduced the cost of processor resemble each

processing capacity. From their humble other? How to they differ? beginnings,

continued increases in microprocessor capacity have rendered other forms of

computers almost completely obsolete (see history of computing hardware),

with one or more microprocessor as processing element in everything from the

smallest embedded systems and handheld devices to the largest mainframes.

Since the early 1970s, the increase in processing capacity of evolving

microprocessors has been known to generally follow Moore's Law.

1.2 Introduction to 8085 Microprocessor

The microprocessor is a small very large scale integration (VLSI) chip with many

pins. It processes information and manage the exchange between the

Input/output units and main memory. It is controlled by a sequence of

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instructions called microprocessor program, and the result of this program in

sent to the appropriate peripheral (input and output). The microprocessor

consists of the following sections:

Several register which stores data.

Arithmetic and logic unit (ALU)

Control and timing unit.

Registers

Registers main function is storing data, some of them can be used by the

programmer and some cannot, and used only by the processor. Most important

registers: Accumulator: also known as A-register, is used for storing the results

of mathematical operations. Instruction register: used to store the current

instruction those are being executed in the microprocessor.

Program counter: stores the address of the next instruction to be

executed.

Buffer register: stores data temporarily.

Status register: stores the current state of the instruction that are

being executed at the microprocessor.

Stack pointer: points to (stores the location of) the place in the main

memory called stack.

Arithmetic Logic Unit (ALU)

This unit executes the arithmetic and

logical instructions.

The microprocessor can be

programmed to perform functions on

given data by writing

specific instructions into its

memory. The microprocessor reads one

instruction at a time, matches it with its

instruction set, and performs

the data manipulation

specified. The result is either stored back

into memory or displayed on an output

device. The 8085 uses three separate

buses to perform its operations:

The address bus.

The data bus.

The control bus.

BRIGHT IDEA

You can think of a bus as a

highway on which data travels

within a computer. All buses

consist of an address bus and a

data bus. The data bus transfers

actual data whereas the address

bus transfers information about

where the data should go.

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The Address Bus

It is a group of wires or lines that are used to transfer the addresses of Memory

or I/O devices. It is unidirectional. In Intel 8085 microprocessor, Address bus

was of 16 bits. This means that Microprocessor 8085 can transfer maximum 16

bit address which means it can address 65,536 different memory locations. This

bus is multiplexed with 8 bit data bus. So the most significant bits (MSB) of

address goes through Address bus (A7-A0) and LSB goes through multiplexed

data bus (AD0-AD7). When the 8085 wants to access a peripheral or a memory

location, it places the 16-bit address on the address bus and then sends the

appropriate control signals.

The Data Bus

As name tells that it is used to transfer data within Microprocessor and

Memory/Input or Output devices. It is bidirectional as Microprocessor requires

to send or receive data. The data bus also works as address bus when

multiplexed with lower order address bus. Data bus is 8 Bits long. The word

length of a processor depends on data bus, that’s why Intel 8085 is called 8 bit

Microprocessor because it have an 8 bit data bus.

The Control Bus

Microprocessor uses control bus to process data that is what to do with the

selected memory location. Some control signals are Read, Write and Opcode

fetch etc. Various operations are performed by microprocessor with the help

of control bus. This is a dedicated bus, because all timing signals are generated

according to control signal.

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Figure 1.5: The Microprocessor Organisation

1.2.1 Interrupts

An interrupt is a condition that causes the microprocessor to temporarily work

on a different task, and then later return to its previous task. Interrupts can be

internal or external. Internal interrupts, or "software interrupts," are triggered

by a softwa re instruction and operate similarly to a jump or branch instruction.

An external interrupt, or a "hardware interrupt," is caused by an external

hardware module. As an example, many computer systems use interrupt driven

I/O, a process where pressing a key on the keyboard or clicking a button on the

mouse triggers an interrupt. The processor stops what it is doing, it reads the

input from the keyboard or mouse, and then it returns to the current program.

The diagram below shows conceptually how an interrupt happens:

Figure 1. 6: Interrupt handling

The grey bars represent the control flow. The top line is the program that is

currently running, and the bottom bar is the interrupt service routine (ISR).

Notice that when the interrupt (Int) occurs, the program stops executing and

the microcontroller beg ins to execute the ISR. Once the ISR is complete, the

microcontroller returns to processing the program where it left off. 8085

Interrupts Interrupt is a process where an external device can get the attention

of the microprocessor. The process starts from the I/O device and is

asynchronous.

Classification of Interrupts

Interrupts can be classified into two types:

Maskable Interrupts (Can be delayed or Rejected)

Non - Maskable Interrupts ( Cannot be delayed

or

Rejected)

Interrupts can also be c lassified into:

Vectored (the address of the service routine is hardwired)

Non - vectored (the address of the service routine needs to be

supplied externally by the device)

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An interrupt is considered to be an emergency signal that may be serviced. The

Microprocessor may respond to it as soon as possible.

What happens when the microprocessor is interrupted?

When the Microprocessor receives an interrupt signal, it suspends the currently

executing program and jumps to an Interrupt Service Routine (ISR) to respond

to the incoming interrupt. Each interrupt will most probably have its own ISR.

Responding to an interrupt may be immediate or delayed depending on

whether the interrupt is mask able or non-mask able and whether interrupts

are being masked or not.

WEB RESOURCE

https://www.youtube.com/watch?v=sfzAABHcq_Y

Watch this complete series of Lecture on Microprocessor

and its applications.

There are two ways of redirecting the execution to the ISR depending on

whether the interrupt is vectored or non-vectored.

When a device interrupts, it actually wants the microprocessor to give a service

which is equivalent to asking the MP to call a subroutine. This subroutine is

called ISR (Interrupt Service Routine).

The ‘EI’ instruction is a one byte instruction and is used to enable the non-mask

able interrupts. The ‘DI’ instruction is a one byte instruction and is used to

disable the non-mask able interrupts. The 8085 has a single Non-Maskable

interrupt. The non-maskable interrupt is not affected by the value of the

Interrupt Enable flip flop.

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Table 1.1: 8085 Microprocessor Interrupts

An interrupt vector is a pointer to where the ISR is stored in memory. All

interrupts (vectored or otherwise) are mapped onto a memory area called the

Interrupt Vector Table (IVT). The IVT is usually located in memory page 00

(0000H – 00FFH). The purpose of the IVT is to hold the vectors that redirect the

microprocessor to the right place when an interrupt arrives.

Let, a device interrupts the Microprocessor using the RST 7.5 interrupt line.

Because the RST 7.5 interrupt is vectored, Microprocessor knows, in which

memory location it has to go using a call instruction to get the ISR address.

RST7.5 is knows as Call 003Ch to Microprocessor. Microprocessor goes to 003C

location and will get a JMP instruction to the actual ISR address. The

microprocessor will then, jump to the ISR location.

1. The interrupt process should be enabled using the EI instruction.

2. The 8085 checks for an interrupt during the execution of every instruction.

3. If INTR is high, MP completes current instruction, disables the interrupt and

sends INTA (Interrupt acknowledge) signal to the device that interrupted.

4. A allows the I/O device to send a RST instruction through data bus.

5. Upon receiving the INTA signal, MP saves the memory location of the next

instruction on the stack and the program is transferred to ‘call’ location (ISR

Call) specified by the RST instruction 6- Microprocessor Performs the ISR.

6. ISR must include the ‘EI’ instruction to enable the further interrupt within

the program.

7. RET instruction at the end of the ISR allows the MP to retrieve the return

address from the stack and the program is transferred back to where the

program was interrupted.

8085 Interrupts II Restart Sequence

The restart sequence is made up of three machine cycles In the

first machine cycle:

The microprocessor sends the INTA signal. While INTA is active the

microprocessor reads the data lines expecting to receive, from the interrupting

device, the opcode for the specific RST instruction.

In the second and third machine cycles:

The 16-bit address of the next instruction is saved on the stack.

Then the microprocessor jumps to the address associated with the specified

RST instruction.

How does the external device produce the opcode for the appropriate RST

instruction?

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The opcode is simply a collection of bits. So, the device needs to set the bits of

the data bus to the appropriate value in response to an INTA signal. During the

interrupt acknowledge machine cycle. The Microprocessor activates the INTA

signal. This signal will enable the Tri-state buffers, which will place the value

EFH on the data bus.

Issues in Implementing INTR Interrupts How

long must INTR remain high?

The microprocessor checks the INTR line one clock cycle before the last T-state

of each instruction. The INTR must remain active long enough to allow for the

longest instruction.

The longest instruction for the 8085 is the conditional CALL instruction which

requires 18 T-states.

Therefore, the INTR must remain active for 17.5 T-states. If f= 3MHZ then T=1/f

and so, INTR must remain active for [ (1/3MHZ) * 17.5 ≈ 5.8 micro seconds].

How long can the INTR remain high?

The INTR line must be deactivated before the EI is executed. Otherwise, the

microprocessor will be interrupted again. Once the microprocessor starts to

respond to an INTR interrupt, INTA becomes active (=0). Therefore, INTR should

be turned off as soon as the INTA signal is received.

Can the microprocessor be interrupted again before the completion of the ISR?

As soon as the 1st interrupt arrives, all mask able interrupts are disabled. They

will only be enabled after the execution of the EI instruction. Therefore, the

answer is: “only if we allow it to”. If the EI instruction is placed early in the ISR,

other interrupt may occur before the ISR is done.

How do we allow multiple devices to interrupt using the INTR line?

The microprocessor can only respond to one signal on INTR at a time.

Therefore, we must allow the signal from only one of the devices to reach the

microprocessor. We must assign some priority to the different devices and

allow their signals to reach the microprocessor according to the priority. The

solution is to use a circuit called the priority encoder (74LS148). This circuit has

8 inputs and 3 outputs. The inputs are assigned increasing priorities according

to the increasing index of the input. Input 7 has highest priority and input 0 has

the lowest. The 3 outputs carry the index of the highest priority active input.

This circuit can be used with a Tri-state buffer to implement an interrupt

priority scheme.

Multiple Interrupts & Priorities

Note that the opcodes for the different RST instructions follow a set pattern.

Bit D5, D4 and D3 of the opcodes change in a binary sequence from RST 7 down

to RST 0. The other bits are always 1. This allows the code generated by the

74366 to be used directly to choose the appropriate RST instruction. The one

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drawback to this scheme is that the only way to change the priority of the

devices connected to the 74366 is to reconnect the hardware.

1.3 Intel 8085 Microprocessor Architecture

1.3.1 Memory

Program, data and stack memories occupy the same memory space. The total

addressable memory size is 64 KB.

Program memory

Program can be located anywhere in memory. Jump, branch and call

instructions use 16-bit addresses, i.e. they can be used to jump/branch

anywhere within 64 KB. All jump/branch instructions use absolute addressing.

Data memory

The data can be placed anywhere as the 8085 processor always uses 16-bit

addresses.

Stack memory

Is limited only by the size of memory. Stack grows downward. First 64 bytes in

a zero memory page should be reserved for vectors used by RST instructions.

Interrupts

The 8085 microprocessor has 5 interrupts. They are presented below in the

order of their priority (from lowest to highest):

INTR is mask able 8080A compatible interrupt. When the interrupt occurs the

processor fetches from the bus one instruction, usually one of these

instructions:

One of the 8 RST instructions (RST0 - RST7). The processor saves

current program counter into stack and branches to memory

location N * 8 (where N is a 3-bit number from 0 to 7 supplied with

the RST instruction).

CALL instruction (3 byte instruction). The processor calls the

subroutine, address of which is specified in the second and third

bytes of the instruction.

RST5.5 is a mask able interrupt. When this interrupt is received the processor

saves the contents of the PC register into stack and branches to 2Ch

(hexadecimal) address.

RST6.5 is a mask able interrupt. When this interrupt is received the processor

saves the contents of the PC register into stack and branches to 34h

(hexadecimal) address.

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RST7.5 is a mask able interrupt. When this interrupt is received the processor

saves the contents of the PC register into stack and branches to 3Ch

(hexadecimal) address.

Trap is a non-mask able interrupt. When this interrupt is received the processor

saves the contents of the PC register into stack and branches to 24h

(hexadecimal) address. All maskable interrupts can be enabled or disabled

using EI and DI instructions. RST 5.5, RST6.5 and RST7.5 interrupts can be

enabled or disabled individually using SIM instruction.

1.3.2 Registers

Accumulator or A register is an 8-bit register used for arithmetic, logic, I/O and

load/store operations.

Flag is an 8-bit register containing 5 1-bit flags:

Sign - set if the most significant bit of the result is set. Zero - set if

the result is zero.

Auxiliary carry - set if there was a carry out from bit 3 to bit 4 of the

result.

Parity - set if the parity (the number of set bits in the result) is even.

Carry - set if there was a carry during addition, or borrow during

subtraction/comparison. General registers:

8-bit B and 8-bit C registers can be used as one 16-bit BC register

pair. When used as a pair the C register contains low-order byte.

Some instructions may use BC register as a data pointer.

8-bit D and 8-bit E registers can be used as one 16-bit DE register

pair. When used as a pair the E register contains low-order byte.

Some instructions may use DE register as a data pointer.

8-bit H and 8-bit L registers can be used as one 16-bit HL register

pair. When used as a pair the L register contains low-order byte. HL

register usually contains a data pointer used to reference memory

addresses.

Stack pointer is a 16 bit register. This register is always is incremented or

decremented by 2.Program counter is a 16-bit register.

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Web Resource

http://www.slideshare.net/ParveshGautam/8085-

microprocessorarchitecture-ppt?next_slideshow=1

Learn in detail about the functions and working of flags, the timing and

control unit, Interrupt control and various other signals associated with it.

Also learn about the data bus and address bus present in 8085

microprocessor and how these units combine to process a data

altogether.

1.4 Instruction Set

Instruction set of Intel 8085 microprocessor consists of the following

instructions:

Data moving instructions.

Arithmetic - add, subtract, increment and decrement.

Logic - AND, OR, XOR and rotate.

Control transfer - conditional, unconditional, call subroutine, return

from subroutine and restarts.

Input/output instructions.

Other - setting/clearing flag bits, enabling/disabling interrupts,

stack operations, etc.

1.5 Addressing modes

Every instruction of a program has to operate on a data.

The method of specifying the data to be operated by the instruction is called

Addressing.

The 8085 has the following 5 different types of addressing.

Immediate Addressing

Direct Addressing

Register Addressing

Register Indirect Addressing

Implied Addressing

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Immediate Addressing:

In immediate addressing mode, the data is specified in the instruction itself.

The data will be a part of the program instruction e.g. MVI B, 3EH - Move the

data 3EH given in the instruction to B register; LXI SP, 2700H.

Direct Addressing:

In direct addressing mode, the address of the data is specified in the instruction.

The data will be in memory. In this addressing mode, the program instructions

and data can be stored in different memory e.g. LDA 1050H - Load the data

available in memory location 1050H in to accumulator; SHLD 3000H Register

Addressing:

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In register addressing mode, the instruction specifies the name of the register

in which the data is available, e.g. MOV A, B - Move the content of B register to

A register; SPHL; ADD C.

Register Indirect Addressing:

In register indirect addressing mode, the instruction specifies the name of the

register in which the address of the data is available. Here the data will be in

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memory and the address will be in the register pair e.g. MOV A, M - The

memory data addressed by H L pair is moved to A register. LDAX B.

Implied Addressing:

In implied addressing mode, the instruction itself specifies the data to be

operated e.g. CMA - Complement the content of accumulator; RAL

1.6 Microprocessor Internal Architecture

Modern microprocessors are among the most complex systems ever created

by humans. A single silicon chip, roughly the size of a fingernail, can contain a

complete high-performance processor, large cache memories, and the logic

required to interface it to external devices. In terms of performance, the

processors implemented on a single chip today dwarf the room-sized

supercomputers that cost over $10 million just 20 years ago. Even the

embedded processors found in everyday appliances such as cell phones,

personal digital assistants, and handheld game systems are far more powerful

than the early developers of computers ever envisioned.

Control Unit

Generates signals within uP to carry out the instruction, which has been

decoded. In reality causes certain connections between blocks of the uP to be

Figure 1. 7 8085 Microprocessor Architecture

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opened or closed, so that data goes where it is required, and so that ALU

operations occur.

Arithmetic Logic Unit

The ALU performs the actual numerical and logic operation such as ‘add’,

‘subtract’, ‘AND’, ‘OR’, etc. Uses data from memory and from Accumulator to

perform arithmetic. Always stores result of operation in Accumulator.

Registers

The 8085/8080A-programming model includes six registers, one accumulator,

and one flag register, as shown in Figure1.8. In addition, it has two 16-bit

registers: the stack pointer and the program counter. They are described briefly

as follows. The 8085/8080A has six general-purpose registers to store 8-bit

data; these are identified as B, C, D, E, H, and L as shown in the figure. They can

be combined as register pairs - BC, DE, and HL - to perform some 16bit

operations. The programmer can use these registers to store or copy data into

the registers by using data copy instructions. Accumulator

The accumulator is an 8-bit register that is a part of arithmetic/logic unit (ALU).

This register is used to store 8-bit data and to perform arithmetic and logical

operations. The result of an operation is stored in the accumulator. The

accumulator is also identified as register A.

Flags

The ALU includes five flip-flops, which are set or reset after an operation

according to data conditions of the result in the accumulator and other

registers. They are called Zero (Z), Carry (CY), Sign (S), Parity (P), and Auxiliary

Carry (AC) flags; they are listed in the Table and their bit positions in the flag

register are shown in the Figure below. The most commonly used flags are Zero,

Carry, and Sign. The microprocessor uses these flags to test data

conditions. For example, after an addition of

two numbers, if the sum in the accumulator

id larger than eight bits, the flip-flop uses to

indicate a carry -- called the Carry flag (CY) –

is set to one. When an arithmetic operation

results in zero, the flipflop called the Zero (Z)

flag is set to one. The first Figure shows an

8bit register, called the flag register,

adjacent to the accumulator. However, it is

not used as a register; five bit positions out

of eight are used to store the outputs of the

THINK POINT

In an 8085 microprocessor

which one is called a High

order Register and which one

is called a Low order

Register?

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five flip-flops. The flags are stored in the 8bit register so that the

programmer can examine these flags (data conditions) by accessing the

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register through an instruction. These flags have critical importance in the

decision-making process of the microprocessor.

The conditions (set or reset) of the flags are tested through the software

instructions. For example, the instruction JC (Jump on Carry) is implemented

to change the sequence of a program when CY flag is set. The thorough

understanding of flag is essential in writing assembly language programs.

Program Counter (PC) This 16-bit registers deals with sequencing the execution

of instructions. This register is a memory pointer. Memory locations have 16bit

addresses, and that is why this is a 16-bit register.

The microprocessor uses this register to sequence the execution of the

instructions.

The function of the program counter is to point to the memory address from

which the next byte is to be fetched. When a byte (machine code) is being

fetched, the program counter is incremented by one to point to the next

memory location

Stack Pointer (SP)

The stack pointer is also a 16-bit register used as a memory pointer. It points

to a memory location in R/W memory, called the stack. The beginning of the

stack is defined by loading 16-bit address in the stack pointer.

Instruction Register/Decoder

Temporary store for the current instruction of a program. Latest instruction

sent here from memory prior to execution. Decoder then takes instruction and

‘decodes’ or interprets the instruction. Decoded instruction then passed to

next stage.

Memory Address Register

Holds address, received from PC, of next program instruction. Feeds the

address bus with addresses of location of the program under execution.

Control Generator

Generates signals within μP to carry out the instruction which has been

decoded. In reality causes certain connections between blocks of the uP to be

opened or closed, so that data goes where it is required, and so that ALU

operations occur.

Register Selector

This block controls the use of the register stack in the example. Just a logic

circuit which switches between different registers in the set will receive

instructions from Control Unit.

27

Figure 1. 8 : System Bus

General Purpose Registers μP requires extra registers for versatility. Can be

used to store additional data during a program. More complex processors may

have a variety of differently named registers.

Microprogramming

How the μP does knows what an instruction means, especially when it is only

a binary number? The micro program in an μP /μC is written by the chip

designer and tells the μP /μC the meaning of each instruction μP /μC can then

carry out operation.

1.7 8085 Microprocessor System Bus

Typical system uses a number of busses, collection of wires, which transmit

binary numbers, one bit per wire. A typical microprocessor communicates with

memory and other devices (input and output) using three busses: Address Bus,

Data Bus and Control Bus.

Address Bus

One wire for each bit, therefore 16 bits = 16 wires. Binary number carried alerts

memory to ‘open’ the designated box. Data (binary) can then be put in or taken

out. The Address Bus consists of 16 wires, therefore 16 bits. Its "width" is 16

bits. A 16 bit binary number allows 216 different numbers, or 32000 different

numbers, i.e. 0000000000000000 up to 1111111111111111. Because memory

consists of boxes, each with a unique address, the size of the address bus

determines the size of memory, which can be used. To communicate with

memory the microprocessor sends an address on the address bus, e.g.

0000000000000011 (3 in decimal), to the memory. The memory selects box

number 3 for reading or writing data. Address bus is unidirectional, i.e.

numbers only sent from microprocessor to memory, not the other way. If you

have a memory chip of size 256 kilobytes (256 x 1024 x 8 bits), how many wires

does the address bus need, in order to be able to specify an address in this

28

memory? Note: the memory is organized in groups of 8 bits per location,

therefore, how many locations must you be able to specify?

Data Bus

Data Bus: carries ‘data’, in binary form,

between μP and other external units,

such as memory. Typical size is 8 or 16

bits. Size determined by size of boxes in

memory and μP size helps determine

performance of μP. The Data Bus

typically consists of 8 wires. Therefore,

28 combinations of binary digits. Data

bus used to transmit "data", i.e.

information, results of arithmetic, etc.,

between memory and

the microprocessor.

Data Bus also carries instructions from

memory to the microprocessor. Size of

the bus therefore limits the number of

possible instructions to 256, each

specified by a separate number.

Control Bus

Control Bus is various lines which have specific functions for coordinating and

controlling microprocessor operations. For example, Read/Not write line,

single binary digit. Control whether memory is being ‘written to’ (data stored

in memory) or ‘read from’ (data taken out of memory) 1 = Read, 0 = Write. May

also include clock line(s) for timing/synchronizing, ‘interrupts’, ‘reset’ etc.

Typically μP has 10 control lines. Cannot function correctly without these vital

control signals.

The Control Bus carries control signals partly unidirectional, partly

bi-directional.

Controls signals are things like "read or write". This tells memory that we are

reading from a location, specified on the address bus, or writing to a location

specified. Various other signals to control and coordinate the operation of the

system.

Modern day microprocessors, like 80386, 80486 have much larger busses.

Typically 16 or 32 bit busses, which allow larger number of instructions, more

memory location, and faster arithmetic. Microcontrollers organized along

same lines, except: because microcontrollers have memory etc. inside the chip,

BRIGHT IDEA

Data bus is bi-directional and it is

the size of the data bus determines

what arithmetic can be done. If

only 8 bits wide then largest

number is 11111111 (255 in

decimal). Therefore, larger

numbers have to be broken down

into chunks of 255. This slows

microprocessor

29

the busses may all be internal. In the microprocessor the three busses are

external to the chip (except for the internal data bus). In case of external

30

busses, the chip connects to the busses via buffers, which are simply an

electronic connection between external bus and the internal data bus.

8085 Pin description

8085 is a general purpose microprocessor having 40 pins and works on single

power supply.

Single + 5V Supply

4 Vectored Interrupts (One is Non Mask able)

Serial In/Serial Out Port

Decimal, Binary, and Double Precision Arithmetic

Direct Addressing Capability to 64K bytes of memory

The Intel 8085A is a new generation, complete 8 bit parallel central processing

unit (CPU). The 8085A uses a multiplexed data bus. The address is split

between the bit address bus and the 8bit data bus. Figures are at the end of

the document.

Pin Description

The following describes the function of each pin:

A6 - A1s (Output 3 State) Address Bus;

The most significant 8 bits of the memory address or the 8 bits of the

I/0 address, 3 stated during Hold and Halt modes.

AD0 - 7 (Input/output 3state) Multiplexed Address/Data Bus; Lower

8 bits of the memory address (or I/0 addresses) appear on the bus

during the first clock cycle of a machine state.

It then becomes the data bus during the second and third clock cycles.

3 stated during Hold and Halt modes.

Address Latch Enable: It occurs during the first clock cycle of a machine state

and enables the address to get latched into the on chip latch of peripherals.

The falling edge of ALE is set to guarantee setup and hold times for the address

information.

ALE can also be used to strobe the status information. ALE is never 3stated. SO,

S1 (Output) Data Bus Status. Encoded status of the bus cycle:

S1 S0

0 0 HALT

0 1 WRITE

1 0 READ

1 1 FETCH

31

S1 can be used as an advanced R/W status. RD

(Output 3state)

READ; indicates the selected memory or 1/0 device is

to be read and that the Data Bus is available for the

data transfer.

WR (Output 3state)

WRITE indicates the data on the Data Bus is to be written into the selected

memory or 1/0 location. Data is set up at the trailing edge of WR. 3 stated

during Hold and Halt modes.

READY (Input)

If Ready is high during a read or writes cycle, it indicates that the memory or

peripheral is ready to send or receive data. If Ready is low, the CPU will wait

for Ready to go high before completing the read or write cycle.

HOLD (Input)

HOLD; indicates that another Master is requesting the use of the Address and

Data Buses. The CPU, upon receiving the Hold request. Will relinquish the use

of buses as soon as the completion of the current machine cycle. Internal

processing can continue.

The processor can regain the buses only after the Hold is removed. When the

Hold is acknowledged, the Address, Data, RD, WR, and IO/M lines are 3stated.

HLDA (Output)

HOLD ACKNOWLEDGE; indicates that the CPU has received the Hold request

and that it will relinquish the buses in the next clock cycle. HLDA goes low after

the Hold request is removed. The CPU takes the buses one half clock cycle after

HLDA goes low.

INTR (Input)

INTERRUPT REQUEST; is used as a general purpose interrupt. It is sampled only

during the next to the last clock cycle of the instruction. If it is active, the

Program Counter (PC) will be inhibited from incrementing and an INTA will be

issued. During this cycle a RESTART or CALL instruction can be inserted to jump

to the interrupt service routine. The INTR is enabled and disabled by software.

It is disabled by Reset and immediately after an interrupt is accepted. INTA

(Output)

INTERRUPT ACKNOWLEDGE; is used instead of (and has the same timing as)

RD during the Instruction cycle after an INTR is accepted. It can be used to

activate the 8259 Interrupt chip or some other interrupt port.

RST 5.5

32

RST 6.5 - (Inputs)

RST 7.5

33

RESTART INTERRUPTS; These three inputs have the same timing as I

NTR except they cause an internal RESTART to be automatically

inserted.

RST 7.5 ~~ Highest Priority

RST 6.5

RST 5.5 o Lowest Priority

The priority of these interrupts is ordered as sh own above. These interrupts

have a higher priority than the INTR.

TRAP (Input)

Trap interrupt is a non - mask able restart interrupt. It is recognized at the same

time as INTR. It is unaffected by any mask or Interrupt Enab le. It has the highest

priority of any interrupt.

RESET IN (Input)

Reset sets the Program Counter to zero and resets the Interrupt Enable and

HLDA flip - flops. None of the other flags or registers (except the instruction

register) are affected The CPU is held in the reset condition as long as Reset is

applied.

Figure 1. 9 : Pin diagram of 8085 microprocessor

34

RESET OUT (Output)

Indicates CPlJ is being reset. Can be used as a system RESET. The signal is

synchronized to the processor clock.

X1, X2 (Input)

Crystal or R/C network connections to set the internal clock generator X1 can

also be an external clock input instead of a crystal. The input frequency is

divided by 2 to give the internal operating frequency.

CLK (Output)

Clock Output for use as a system clock when a crystal or R/ C network is used

as an input to the CPU. The period of CLK is twice the X1, X2 input period.

IO/M (Output)

IO/M indicates whether the Read/Write is to memory or l/O Tri-stated during

Hold and Halt modes.

SID (Input)Serial input data line the data on this line is loaded into accumulator

bit 7 whenever a RIM instruction is executed.

SOD (output)Serial output data line. The output SOD is set or reset as specified

by the SIM instruction. Vcc +5 volt supply.

Vss Ground Reference.

For the execution of an

instruction a microprocessor fetches

the instruction from the memory and executes

it. The time taken for the execution of an

instruction is called instruction cycle (IC). An

instruction cycle (IC). An instruction cycle

consists of a fetch cycle (FC) and an execute

cycle (EC). A fetch cycle is the time required for

the fetch operation in which the machine code

of the instruction (opcode) is fetched from the

memory. This time is a fixed slot of time. An

execute cycle is of variable width

which depends on the instruction to be executed. The total time for the

execution is given by: IC = FC + EC.

THINK POINT

In an 8085

microprocessor what is

the function of HOLD and

HLDA signal?

35

Fetch Operation

In fetch operation the microprocessor gets the 1st byte of the instruction,

which is operation code (opcode), from the memory. The program counter

keeps the track of address of the next instruction to be executed. In the

beginning of the fetch cycle the content of the program counter is sent to the

memory. This takes one clock cycle. The memory first reads the opcode. This

operation also takes one clock cycle. Then the memory sends the opcode to

the microprocessor, which takes one clock period.

The total time for fetch operation is the time required for fetching an opcode

from the memory. This time is called fetch cycle. Having received the address

from the microprocessor the memory takes two clock cycles to respond as

explained above. If the memory is slow, it may take more time. In that case the

microprocessor has to wait for some time till it receives the opcode from the

memory. The time for which the microprocessor waits is called wait cycle.

Most of the microprocessor have provision for wait cycles to cope with slow

memory.

Execute Operation

The opcode fetched from the memory goes to the data register, DR

(data/address buffer in Intel 8085) and then to instruction register, IR. From

the instruction register it goes to the decoder circuitry is within the

microprocessor. After the instruction is decoded, execution begins. If the

operand is in the general purpose registers, execution is immediately

performed. The time taken in decoding and the address of the data, some read

cycles are also necessary to receive the data from the memory. These read

cycle are similar to opcode fetch cycle. The fetch quantities in these cycles are

address or data.

Machine Cycle

An instruction cycle consists of one or more machine cycles as shown in Figure

5. This figure is for MVI instruction. A machine cycle consists of a number of

clock cycles. One clock cycle is known as state.

Figure 1. 10 : Typical Instruction Set

36

8085 Microprocessor Functional Description

The 8085A is a complete 8 bit parallel central processor. It requires a single +5

volt supply. Its basic clock speed is 3 MHz thus improving on the present 8080's

37

performance with higher system speed. Also it is designed to fit into a minimum system

of three IC's: The CPU, a RAM/ IO, and a ROM or PROM/IO chip.

The 8085A uses a multiplexed Data Bus. The address is split between the higher bit

Address Bus and the lower 8bit Address/Data Bus. During the first cycle the address is

sent out. The lower 8bits are latched into the peripherals by the

Address Latch Enable (ALE). During the rest of the machine cycle the Data Bus is used

for memory or l/O data.

The 8085A provides RD, WR, and lO/Memory signals for bus control. An Interrupt

Acknowledge signal (INTA) is also provided. Hold, Ready, and all Interrupts are

synchronized. The 8085A also provides serial input data (SID) and serial output data

(SOD) lines for simple serial interface.

In addition to these features, the 8085A has three mask able, restart interrupts and one

non-mask able trap interrupt. The 8085A provides RD, WR and IO/M signals for Bus

control.

Status Information

Status information is directly available from the 8085A. ALE serves as a status strobe.

The status is partially encoded, and provides the user with advanced timing of the type

of bus transfer being done. IO/M cycle status signal is provided directly also. Decoded

So, S1 Carries the following status information:

HALT, WRITE, READ, FETCH.

S1 can be interpreted as R/W in all bus transfers. In the 8085A the 8 LSB of address are

multiplexed with the data instead of status. The ALE line is used as a strobe to enter the

lower half of the address into the memory or peripheral address latch. This also frees

extra pins for expanded interrupt capability.

Interrupt and Serial l/O The8085A has5 interrupt inputs: INTR, RST5.5, RST6.5, RST 7.5,

and TRAP. INTR is identical in function to the 8080 INT. Each of these three RESTART

inputs, 5.5, 6.5. 7.5, has a programmable mask. TRAP is also a RESTART interrupt except

it is non-mask able.

The three RESTART interrupts cause the internal execution of RST (saving the program

counter in the stack and branching to the RESTART address) if the interrupts are

enabled and if the interrupt mask is not set. The non-mask able TRAP causes the internal

execution of a RST independent of the state of the interrupt enable or masks. The

interrupts are arranged in a fixed priority that determines which interrupt is to be

recognized if more than one is pending as follows: TRAP highest priority, RST 7.5, RST

6.5, RST 5.5, INTR lowest priority This priority scheme does not take into account the

priority of a routine that was started by a higher priority interrupt. RST 5.5 can

interrupt a RST 7.5 routine if the interrupts were reenabled before the end of the RST

7.5 routine. The TRAP interrupt is useful for catastrophic errors such as power failure

or bus error. The TRAP input is recognized just as any other interrupt but has the highest

38

priority. It is not affected by any flag or mask. The TRAP input is both edge and

level sensitive.

Basic System Timing

The 8085A has a multiplexed Data Bus. ALE is used as a strobe to sample the

lower 8bits of address on the Data Bus. Figure 2 shows an instruction fetch,

memory read and l/ O write cycle (OUT). Note that during the l/O write and

read cycle that the l/O port address is copied on both the upper and lower half

of the address. As in the 8080, the READY line is used to extend the read and

write pulse lengths so that the 8085A can be used with slow memory. Hold

causes the CPU to relinquish the bus when it is through with it by floating the

Address and Data Buses.

System Interface

8085A family includes memory components, which are directly compatible to

the 8085A CPU. For example, a system consisting of the three chips, 8085A,

8156, and 8355 will have the following features:

2K Bytes ROM

256 Bytes RAM

1 Timer/Counter

4 8bit l/O Ports

1 1 6bit l/O Port

4 Interrupt Levels

Serial In/Serial Out Ports

In addition to standard l/O, the memory mapped I/O offers an efficient l/O

addressing technique. With this technique, an area of memory address space is

assigned for l/O address, thereby, using the memory address for I/O

manipulation. The 8085A CPU can also interface with the standard memory that

does not have the multiplexed address/data bus.

39

40

Accumulator

The accumulator is an 8-bit register that is a part of arithmetic/logic unit (ALU).

This register is used to store 8-bit data and to perform arithmetic and logical

operations. The result of an operation is stored in the accumulator. The

accumulator is also identified as register A.

Flags

The ALU includes five flip-flops, which are set or reset after an operation

according to data conditions of the result in the accumulator and other

registers. They are called Zero (Z), Carry (CY), Sign (S), Parity (P), and Auxiliary

Carry (AC) flags; their bit positions in the flag register are shown in the Figure

below. The most commonly used flags are Zero, Carry, and Sign. The

microprocessor uses these flags to test data conditions.

Program Counter (PC)

This 16-bit register deals with sequencing the execution of instructions. This

register is a memory pointer. Memory locations have 16-bit addresses, and that

is why this is a 16-bit register. The microprocessor uses this register to sequence

the execution of the instructions.

The function of the program counter is to point to the memory address from

which the next byte is to be fetched. When a byte (machine code) is being

fetched, the program counter is incremented by one to point to the next

memory location.

41

Web Resource

https://www.youtube.com/watch?v=_lvm_MPeY5w

Learn in detail about the microprocessor 8085 architecture and

programing model from this video lecture.

Stack Pointer (SP)

The stack pointer is also a 16-bit register used as a memory pointer. It points to a

memory location in R/W memory, called the stack. The beginning of the stack is defined

by loading 16-bit address in the stack pointer.

This programming model will be used in subsequent tutorials to examine how these

registers are affected after the execution of an instruction.

42

43

44

45

contents of the source are destroyed when, in fact, the contents are retained without

any modification.

The various types of data transfer (copy) are listed below together with examples of

each type:

Types Examples

1. Between Registers. 1. Copy the contents of the register B

into register D.

2. Specific data byte to a register

or a memory location.

2. Load registers B with the data byte

32H.

3. Between a memory location

and a register.

3. From a memory location 2000H to

register B.

4. Between an I/O device and the

accumulator.

4. From an input keyboard to the

accumulator.

1.9.2 Arithmetic Operations

These instructions perform arithmetic operations such as addition, subtraction,

increment, and decrement.

Addition - Any 8-bit number, or the contents of a register or the contents of a

memory location can be added to the contents of the accumulator and the sum is

stored in the accumulator. No two other 8-bit registers can be added directly (e.g., the

contents of register B cannot be added directly to the contents of the register C). The

instruction DAD is an exception; it adds 16-bit data directly in register pairs.

Subtraction - Any 8-bit number, or the contents of a register, or the contents of

a memory location can be subtracted from the contents of the accumulator and the

results stored in the accumulator. The subtraction is performed in 2's compliment, and

the results if negative, are expressed in 2's complement. No two other registers can be

subtracted directly.

Increment/Decrement - The 8-bit contents of a register or a memory location

can be incremented or decrement by 1. Similarly, the 16-bit contents of a register pair

(such as BC) can be incremented or decrement by 1. These increment and

decrement operations differ from addition and subtraction in an important way;

i.e., they can be performed in any one of the registers or in a memory location.

46

1.9.3 Logical Operations

These instructions perform various logical operations with the contents of the

accumulator.

AND, OR Exclusive-OR - Any 8-bit number, or the contents of a register,

or of a memory location can be logically ANDed, Ored, or Exclusive-ORed with

the contents of the accumulator. The results are stored in the accumulator.

Rotate- Each bit in the accumulator can be shifted either left or right to

the next position.

Compare- Any 8-bit number or the contents of a register, or a memory

location can be compared for equality, greater than, or less than, with the

contents of the accumulator.

Complement - The contents of the accumulator can be complemented.

All 0s are replaced by 1s and all 1s are replaced by

0s.

1.9.4 Branching Operations

This group of instructions alters the sequence of program execution either

conditionally or unconditionally.

Jump - Conditional jumps are an important aspect of the decisionmaking

process in the programming. These instructions test for a certain conditions

(e.g., Zero or Carry flag) and alter the program sequence when the condition is

met. In addition, the instruction set includes an instruction called unconditional

jump.

Call, Return, and Restart - These instructions change the sequence of a

program either by calling a subroutine or returning from a subroutine. The

conditional Call and Return instructions also can test condition flags.

1.9.5 Machine Control Operations

These instructions control machine functions such as Halt, Interrupt, or do

nothing.

The microprocessor operations related to data manipulation can be

summarized in four functions:

Copying data

Performing arithmetic operations

Performing logical operations

Testing for a given condition and alerting the program sequence Some

important aspects of the instruction set are noted below:

47

In data transfer, the contents of the source are not destroyed; only the

contents of the destination are changed. The data copy instructions do not

affect the flags.

Arithmetic and Logical operations are performed with the contents of

the accumulator, and the results are stored in the accumulator (with some

expectations). The flags are affected according to the results.

Any register including the memory can be used for increment and

decrement. A program sequence can be changed either conditionally or by

testing for a given data condition.

Instruction Format

An instruction is a command to the microprocessor to perform a given task on

a specified data. Each instruction has two parts: one is task to be performed,

called the operation code (opcode), and the second is the data to be operated

on, called the operand. The operand (or data) can be specified in various ways.

It may include 8-bit (or 16-bit) data, an internal register, a memory location, or

8-bit (or 16-bit) address.

In some instructions, the operand is implicit.

Instruction word size

The 8085 instruction set is classified into the following three groups according

to word size:

One-word or 1-byte instructions

Two-word or 2-byte instructions

Three-word or 3-byte instructions

48

In the 8085, "byte" and "word" are synonymous because it is an 8-bit microprocessor.

However, instructions are commonly referred to in terms of bytes rather than words.

One-Byte Instructions

A 1-byte instruction includes the opcode and operand in the same byte.

Task Opcode Operand Binary

Code

Hex Code

Load an 8-bit

data byte in

the

accumulator.

MVI A, Data 0011 1110 3E

Data

First

Byte

Second

Byte

49

Operand(s) are internal register and are coded into the instruction. For

example:

Task Op code Operand Binary

Code

Hex

Code

Copy the contents of the

accumulator in the register C.

MOV C,A 0100

1111

4FH

Add the contents of register

B to the contents of the

accumulator.

ADD B 1000

0000

80H

Invert (compliment) each bit

in the accumulator.

CMA 0010

1111

2FH

These instructions are 1-byte instructions performing three different tasks. In the first

instruction, both operand registers are specified. In the second instruction, the operand

B is specified and the accumulator is assumed. Similarly, in the third instruction, the

accumulator is assumed to be the implicit operand. These instructions are stored in 8-

bit binary format in memory; each requires one memory location.

Two-Byte Instructions

In a two-byte instruction, the first byte specifies the operation code and the second byte

specifies the operand. Source operand is a data byte immediately following the opcode.

For example:

DATA

50

Three-Byte Instructions

In a three-byte instruction, the first byte specifies the opcode, and the following

two bytes specify the 16-bit address. Note that the second byte is the low-order

address and the third byte is the highorder address. opcode + data byte + data

byte.

This instruction would require three memory locations to store in memory.

51

Task Opcode Operand Binary code Hex

Code

Transfer the

program

sequence to

the memory

location 2085H.

JMP 2085H 1100 0011

1000 0101

0010 0000

C3

85

20

First byte

Second

Byte

Third Byte

Three byte instructions - opcode + data byte + data byte LXI rp, data16 rp is one of the

pairs of registers BC, DE, HL used as 16-bit registers. The two data bytes are 16-bit data

in L H order of significance. rp <-- data16 Example:

LXI H,0520H coded as 21H 20H 50H in three bytes. This is also immediate addressing.

LDA addr

A <-- (addr) Addr is a 16-bit address in L H order. Example: LDA 2134H coded as 3AH 34H

21H. This is also an example of direct addressing.

52

53

54

Worked Examples

55

56

57

1.1 Write an assembly program to add two numbers.

58

Solution: Program:

59

MVI D, 8BH

60

MVI C, 6FH

61

MOV A, C

62

1100 0011

63

1000 0101

64

0010 0000

65

ADD D

66

OUT PORT1

67

HLT

68

1.2 Write an assembly program to multiply a number by 8.

69

Solution: Program:

70

MVI A, 30H

71

RRC

72

RRC

73

RRC

74

OUT PORT1

75

HLT

1.3 Write an assembly program to find greatest between two

numbers

Solution:

Program:

MVI B, 30H

MVI C, 40H

MOV A, B

CMP C

JZ EQU

JC GRT

OUT PORT1

HLT

EQU: MVI A, 01H

OUT PORT1

HLT

GRT: MOV A, C

OUT PORT1 HLT

76

77

Data Transfer Group

The data transfer instructions move data between registers or between memory and

registers.

MOV Move MVI Move Immediate

Memory

LDA Load Accumulator Directly from

STA Store Accumulator Directly in Memory

LHLD Load H & L Registers Directly from Memory

SHLD Store H & L Registers Directly in Memory

An 'X' in the name of a data transfer instruction implies that it deals with a register pair

(16-bits);

LXI Load Register Pair with Immediate data

LDAX Load Accumulator from Address in Register Pair

STAX Store Accumulator in Address in Register Pair

XCHG Exchange H & L with D & E

XTHL Exchange Top of Stack with H & L

Arithmetic Group:

78

The arithmetic instructions add, subtract, increment, or decrement data in

registers or memory.

79

ADD Add to Accumulator

ADI Add Immediate Data to Accumulator

ADC Add to Accumulator Using Carry Flag

ACI Add Immediate data to Accumulator Using Carry

SUB Subtract from Accumulator

SUI Subtract Immediate Data from Accumulator

SBB Subtract from Accumulator Using Borrow (Carry)

Flag

SBI Subtract Immediate from Accumulator Using Borrow

(Carry) Flag

INR Increment Specified Byte by One

DCR Decrement Specified Byte by One

INX Increment Register Pair by One

DCX Decrement Register Pair by One

DAD Double Register Add; Add Content of Register

Pair to H & L Register Pair

Logical Group:

This group performs logical (Boolean) operations on data in registers and memory and

on condition flags. The logical AND, OR, and Exclusive OR instructions enable you to set

specific bits in the accumulator ON or OFF.

ANA Logical AND with Accumulator

ANI Logical AND with Accumulator Using Immediate Data

ORA Logical OR with Accumulator

OR Logical OR with Accumulator Using Immediate Data

XRA Exclusive Logical OR with Accumulator

XRI Exclusive OR Using Immediate Data

The Compare instructions compare the content of an 8-bit value with the contents of

the accumulator; CMP Compare

CPI Compare Using Immediate Data

The rotate instructions shift the contents of the accumulator one bit position to the left

or right:

RLC Rotate Accumulator Left

RRC Rotate Accumulator Right

RAL Rotate Left Through Carry

RAR Rotate Right Through Carry

80

Complement and carry flag instructions:

CMA Complement Accumulator

CMC Complement Carry Flag

STC Set Carry Flag

Branch Group:

The branching instructions alter normal sequential program flow, either

unconditionally or conditionally. The unconditional branching instructions are

as follows:

JMP Jump

CALL Call

RET Return

Conditional branching instructions examine the status of one of four condition

flags to determine whether the specified branch is to be executed. The

conditions that may be specified are as follows:

NZ Not Zero (Z = 0) Z Zero (Z = 1)

NC No Carry (C = 0)

C Carry (C = 1)

PO Parity Odd (P = 0)

PE Parity Even (P = 1)

P Plus (S = 0)

M Minus (S = 1)

Thus, the conditional branching instructions are specified as follows:

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Jumps Calls Returns

C CC RC (Carry)

INC CNC RNC (No Carry)

JZ CZ RZ (Zero)

JNZ CNZ RNZ (Not Zero)

JP CP RP (Plus)

JM CM RM (Minus)

JPE CPE RPE (Parity Even)

JP0 CPO RPO (Parity Odd)

Two other instructions can affect a branch by replacing the contents or the program

counter:

PCHL Move H & L to Program Counter \RST Special Restart

Instruction Used with Interrupts

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Stack I/O, and Machine Control Instructions: The following

instructions affect the Stack and/or Stack Pointer:

PUSH Push Two bytes of Data onto the Stack

POP Pop Two Bytes of Data off the Stack

XTHL Exchange Top of Stack with H & L

SPHL Move content of H & L to Stack Pointer

The I/O instructions are as follows:

IN Initiate Input Operation

OUT Initiate Output Operation

The Machine Control instructions are as follows:

EI Enable Interrupt System

DI Disable Interrupt System

HLT Halt

NOP No Operation

Addition of two 8 bit numbers.

MVI B, 06

//Load Register B with the Hex value 06

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MOV A, B

//Move the value in B to the Accumulator or register A

MVI C, 07

//Load the Register C with the second number 07

ADD C

//Add the content of the Accumulator to the Register C

STA 8200

//Store the output at a memory location e.g. 8200

HLT

//Stop the program execution

Addition of two 8 bit n umbers stored in memory Code:

LDA 8500

//Load the accumulator with the address of memory viz 8500

MOV B, A

Move the accumulator value to the register B

LDA 8501

//Load the accumulator with the address of memory viz 8501

ADD B

//Add the content of the Accumulator to the Register B

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STA 8502

//Store the output at a memory location e.g. 8502

HLT

//Stop the program execution

Addition of two 8 bit numbers stored in memory and storing the carry Code:

LDA 8500

//Load the accumulator with the address of memory viz 8500 MOV

B, A

Move the accumulator value to the register B

LDA 8501

//Load the accumulator with the address of memory viz 8501 ADD B

//Add the content of the Accumulator to the Register B

STA 8502

//Store the output at a memory location e.g. 8502

MVI A, 00

//clear the accumulator with 00

ADC A

//Add with carry the content of the accumulator

STA 8503

//Store the output at a memory location e.g. 8503

HLT

//Stop the program execution

Statement: Store the data byte 32H into memory location 4000H.

Program 1:

MVI A, 52H : Store 32H in the accumulator STA 4000H

: Copy accumulator contents at address 4000H HLT

: Terminate program execution

Program 2:

LXI H : Load HL with 4000H MVI M

:Store 32H in memory location pointed by HL register pair (4000H) HLT

: Terminate program execution

Statement: Exchange the contents of memory locations 2000H and 4000H

Program 1:

LDA 2000H :Get the contents of memory location 2000H into

accumulator

MOV B, A : Save the contents into B register

LDA 4000H : Get the contents of memory location 4000Hinto

accumulator

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Figure 1. 13 Levels of Programming Languages

STA 2000H : Store the contents of accumulator at address 2000H

MOV A, B : Get the saved contents back into A register

STA 4000H : Store the contents of accumulator at address 4000H

Instruction Set Architecture

ISA Includes the information needed to interact with the microprocessor. Does

not include information as to how microprocessor is designed or implemented

Includes microprocessor instruction set, which would be the set of all assembly

languages instructions. Also includes the complete set of accessible registers.

1.10 Levels of Programming Languages

Programming languages are divided into three categories.

High level languages hide the details of the computer and operating system. Are

also referred to as platform-independent. Examples include C++, Java, and

FORTRAN.

Assembly language is an example of a lower level language. Each

microprocessor has its own assembly language. A program written in the

assembly language of one microprocessor cannot be run on a different

microprocessor.

Backward compatibility used in order to have old programs that ran on an old

microprocessor, can run on a newer model. Assembly language can manipulate

the data stored in a microprocessor. Assembly language is not platform

independent.

Lowest levels of languages are machine language. Contains binary values to

cause microprocessor to perform operations. Microprocessor understands the

machine language, and thus it is in this state that it executes an instruction set.

High level language and assembly language are converted to machine language.

A programming language such as C, FORTRAN, or Pascal that enables a

programmer to write programs that are more or less independent of a

particular type of computer. Such languages are considered high-level because

they are closer to human languages and further from machine languages. In

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contrast, assembly languages are considered low-level because they are very

close to machine languages.

The main advantage of high-level languages over low-level languages is that

they are easier to read, write, and maintain. Ultimately, programs written in a

high-level language must be translated into machine language by a compiler or

interpreter.

Compilers

Compiler checks statement in a program is valid. If every instruction is

syntactically correct, then the compiler generates an object code. Linker

combines object code as an executable file.

Executable file copied into memory and

microprocessor then runs the machine code

contained in that file.

A high-level language statement is usually

converted to a sequence of several machine

code instructions. Every high-level language

statement might have more than one valid

conversion of a statement. Every statement

in assembly language

however corresponds to one unique

machine code instruction. The assembler

converts source code to object code, and

then the linking, and the loading of

procedures occur.

1.11 Closer look at Assembly Language

Assembly language is very important part of an instruction set architecture.

Assembly instructions can be grouped together based on their functions.

Instructions related with this category perform the following transfers:

Load data from memory into microprocessor.

Store data from the microprocessor into memory.

Move data within the microprocessor. Input data to the

microprocessor.

Output data from the microprocessor.

Data operation instructions modify their data values. They require one or two

operands, and then they store the result Arithmetic instructions make up a large

part of the data operation instructions. Logic instructions perform basic logical

operations on data. Shift instructions shift bits of data values in a register. For

Assembly languages, the jump or branch instruction is commonly used to go to

THINK POINT

the diffe Identify rence

between an interpreter and a

compiler. What are the

advantages level of high

lan guages level over low

languages?

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another part of the program. An assembly language instruction set may include

instructions to call and return from subroutines. Microprocessor can also be

designed to accept interrupts, which basically causes a microprocessor to stop

its current process, and execute another set of instructions.

Data Types

Numeric data can be represented as integers:

Unsigned integers of n-bit values can range from 0 to 2𝑛−1.

Signed n-bit integers can have values between –2𝑛−1 to 2𝑛−1−1

Other types include:

Float: Microprocessor may have special registers only for floating point data,

and its corresponding instruction set.

Boolean: Instructions can perform logical operations on these values.

Characters: Stored as binary values. Operations include concatenation,

replacing characters, or character string manipulation.

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1.1 Expand the following acronyms:

IC, ALU, EI, DI, RISC.

1.2 What are the basic units of a microprocessor?

1.3 Name and explain the three special registers of an 8085

microprocessor.

1.4 Define opcode and operand?

1.5 List the limitations of 8 bit microprocessor.

1.6 What do you mean by T-state, instruction cycle, and machine

cycle?

1.7 Describe the function of HOLD and HLDA signal.

1.8 Discuss the difference between an assembly language and a high

level language? Use practical examples in your answer.

1.9 There are five types of instruction used in 8085 microprocessor. List

and explain these five instruction sets.

1.10 Discuss the different types of addressing modes.

1.11 Which type of architecture 8085 has?

1.12 Expand the acronym ALE. Explain the functions of ALE in 8085.

1.13 Differentiate between software and hardware interrupts.

Explain what happens when the microprocessor is interrupted.

1.14 Differentiate between symmetrical and asymmetrical

multiprocessing.

1.15 What is the need for timing diagram?

1.16 Draw and specify the complete bit configuration of 8085 flag

Register?

1.17 Explain the interrupt process in 8085.

Review Ques tions

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1.18 Distinguish between an assembler and a linker and explain their

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use in program development.

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TOPIC TWO | 8086 SOFTWARE ASPECTS, SYSTEM DESIGN AND I/O

INTERFACING

LEARNING OUTCOMES

1. Demonstrate a sound understanding of the properties of 8086 microprocessor.

2. Demonstrate an understanding of the 8086 microprocessor maximum and minimum mode.

3. Demonstrate a sound understanding of the block diagram of 8086 microprocessor.

4. Demonstrate an understanding internal architecture of 8086

microprocessor

2.1 Properties of 8086 Microprocessor

It is a 16-bit Microprocessor housed in a 40-pin Dual-Inline-Package (DIP) and

capable of addressing 1Megabyte of memory, various versions of this chip can

operate with different clock frequencies ranging from 5 MHz.

The term 16-bit means that its Arithmetic Logic Unit (ALU), its internal registers

and most of its instructions are designed to work with 16-bit binary word. The

8086 microprocessor has a 16-bit data bus, so it can read from or write data to

memory and ports either 16-bits or 8-bits at a time. The 8086 Microprocessor

has 20-bit address bus, so it can address any one of 220 or 1,048,576 memory

locations. Here 16-bit words will be stored in two consecutive memory

locations. If the first byte of a word is at an even address, the 8086 can read

entire word in one operation, if the first byte of the word is at an odd address

the 8086 will read the first byte with one bus operation and the second byte

with another bus operation.

Some inherent properties of the 8086 microprocessor family are:

It can support up to 64K I/O ports.

It provides 14, 16 -bit registers.

It has multiplexed address and data bus AD0- AD15 and A16 – A19.

It requires single phase clock with 33% duty cycle to provide

internal timing.

8086 microprocessor is designed to operate in two modes,

Minimum and Maximum.

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It can prefaces up to 6 instruction bytes from memory and queues

them in order to speed up instruction execution. It requires +5V

power supply.

2.2 8086 Internal Architecture

The internal architecture 8086 microprocessor is as shown in the Fig 2.1. The

8086 CPU is divided into two independent functional parts, the Bus interface

unit (BIU) and execution unit (EU).

The Bus Interface Unit contains Bus Interface Logic, Segment registers, Memory

addressing logic and a six byte instruction object code queue. The execution

unit contains the Data and Address registers, the Arithmetic and Logic Unit, the

Control Unit and flags.

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Figure 2.1 8086 Microprocessor Internal Architecture The BIU sends out address,

fetches the instructions from memory, read data from ports and memory, and

writes the data to ports and memory. In other words the BIU handles all transfers of

data and addresses on the buses for the execution unit. The execution unit (EU) of

the 8086 tells the BIU where to fetch instructions or data from, decodes instructions

and executes instruction. The EU contains control circuitry which directs internal

operations. A decoder in the EU translates instructions fetched from memory into a

series of actions which the EU carries out.

The EU is has a 16-bit ALU which can add, subtract, AND, OR, XOR, increment,

decrement, complement or shift binary numbers. The EU is decoding an

instruction or executing an instruction which does not require use of the buses.

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2.2.1 Bus Interface Unit

Specifically it has the following functions:

Instruction fetch, Instruction queuing, Operand fetch and storage,

Address relocation and Bus control.

The BIU uses a mechanism known as an instruction stream queue

to implement a pipeline architecture.

This queue permits prefetch of up to six bytes of instruction code.

Whenever the queue of the BIU is not full, it has room for at least

two more bytes and at the same time the EU

These prefetching instructions are held in its FIFO queue. With its 16 bit data

bus, the BIU fetches two instruction bytes in a single memory cycle. After a

byte is loaded at the input end of the queue, it automatically shifts up through

the FIFO to the empty location nearest the output.

The EU accesses the queue from the output end. It reads one instruction byte

after the other from the output of the queue. If the queue is full and the EU is

not requesting access to operand in memory.

These intervals of no bus activity, which may occur between bus cycles are

known as idle state.

If the BIU is already in the process of

fetching an instruction when the EU

request it to read or write operands from

memory or I/O, the BIU first completes the

instruction fetch bus cycle before initiating

the operand read / write cycle. The BIU

also contains a dedicated adder which is

used to generate the 20bit physical

address that is output on the address bus.

This address is formed by adding an

appended 16 bit segment address and a 16

bit offset address. The BIU is also

responsible for generating

bus control signals such as those for memory read or write and I/O read or

write.

2.2.2 Execution Unit

The Execution unit is responsible for decoding and executing all instructions.

The EU extracts instructions from the top of the queue in the BIU, decodes

them, generates operands if necessary, passes them to the BIU and requests it

to perform the read or write bus cycles to memory or I/O and perform the

operation specified by the instruction on the operands.

THINK POINT

What are the functions played

by the Bus Interface Unit ( BIU)

and Execution Unit ( EU ) ?

How does the two

complement each other?

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During the execution of the instruction, the EU tests the status and

control flags and updates them based on the results of executing

the instruction.

If the queue is empty, the EU waits for the next instruction byte to

be fetched and shifted to top of the queue.

When the EU executes a branch or jump instruction, it transfers

control to a location corresponding to another set of sequential

instructions.

Whenever this happens, the BIU automatically resets the queue

and then begins to fetch instructions from this new location to refill

the queue.

2.3 Minimum and Maximum Modes

In a minimum mode 8086 system, the microprocessor 8086 is operated in

minimum mode by strapping its MN/MX* pin to logic1. In this mode, all the

control signals are given out by the microprocessor chip itself. There is a single

microprocessor in the minimum mode

system. The remaining components in

the system are latches, transreceivers,

clock generator, memory and I/O

devices. Some type of chip selection

logic may be required for selecting

memory or I/O devices, depending upon

the address map of the system.

In the maximum mode, the 8086 is

operated by strapping the MN/MX* pin

to ground. In this mode, the processor

derives the status signals S2*, S1* and

S0*. Another chip called bus controller

derives the control signals using this

status information. In the maximum mode, there may be more than one

microprocessor in the system configuration. The other components in the

system are the same as in the minimum mode system.

The minimum mode is selected by applying logic 1 to the MN / MX

input pin. This is a single microprocessor configuration. The

maximum mode is selected by applying logic 0 to the MN / MX

input pin. This is a multi-microprocessors configuration.

RESEARCH

With the aid of a block diagram

discuss the functions of the 8086

microprocessor in the minimum

mode of operation.

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Signal Description of 8086 2.4

The 8086 Microprocessor is a 16 - bit CPU available in 3 clock rates, i.e. 5, 8 and

10 MHz, packaged in a 40 pin CERDIP or plastic package. The 8086

microprocessor operates in single processor or multiprocessor configurations

to achieve high performance. The pin configuration is as shown in Figure 2.2.

Some of the pins serve a particular function in minimum mode (single processor

mode) and others function in maximum mode (multiprocessor mode)

configuration.

The 8086 signals can be categorized in three groups:

The first are the signal having common functions in minimum as

well as maximum mode.

The second are the signals which have special functions for

minimum mode.

The third are the signals having specia l functions for maximum

mode.

Figure 2.3 8086 Microprocessor Pin Diagram

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The following signal descriptions are common for both modes:

AD15-AD0: These are the time multiplexed memory I/O address

and data lines.

Address remains on the lines during T1 state, while the data is

available on the data bus during T2, T3, Tw and T4.

These lines are active high and float to a tri-state during interrupt

acknowledge and local bus hold acknowledge cycles.

A19/S6, A18/S5, A17/S4, and A16/S3: These are the time

multiplexed address and status lines.

During T1 these are the most significant address lines for memory

operations.

During I/O operations, these lines are low. During memory or I/O

operations, status information is available on those lines for T2, T3,

Tw and T4.

The status of the interrupt enable flag bit is updated at the

beginning of each clock cycle.

The S4 and S3 combined indicate which segment register is

presently being used for memory accesses as in below fig.

These lines float to tri-state off during the local bus hold

acknowledge. The status line S6 is always low.

The address bits are separated from the status bit using latches

controlled by the ALE signal.

Table 2.1: Bus High Enable/Status

BHE/S7: The bus high enable is used to indicate the transfer of data

over the higher order (D15-D8) data bus as shown in Table 2.1

above. It goes low for the data transfer over D15-D8 and is used to

derive chip selects of odd address memory bank or peripherals. BHE

is low during T1 for read, write and interrupt acknowledge cycles,

whenever a byte is to be transferred on higher byte of data bus. The

status information is available during T2, T3 and T4. The signal is

active low and tri-stated during hold. It is low during T1 for the first

pulse of the interrupt acknowledges cycle.

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RDRead: This signal on low indicates the peripheral that the

processor is performing s memory or I/O read operation. RD is

active low and shows the state for T2, T3, and Tw of any read cycle.

The signal remains tri-stated during the hold acknowledge.

READY: This is the acknowledgement from the slow device or

memory that they have completed the data transfer. The signal

made available by the devices is synchronized by the 8284A clock

generator to provide ready input to the 8086. The signal is active

high.

INTR-Interrupt Request: This is a triggered input. This is sampled

during the last clock cycles of each instruction to determine the

availability of the request. If any interrupt request is pending, the

processor enters the interrupt acknowledge cycle.

TEST This input is examined by a ‘WAIT’ instruction. If the TEST pin

goes low, execution will continue, else the processor remains in an

idle state. The input is synchronized internally during each clock

cycle on leading edge of clock.

CLK- Clock Input: The clock input provides the basic timing for

processor operation and bus control activity. It’s an asymmetric

square wave with 33% duty cycle.

MN/MX: The logic level at this pin decides whether the processor

is to operate in either minimum or maximum mode.

The following pin functions are for the minimum mode operation of 8086:

M/IO – Memory/IO: This is a status line logically equivalent to S2 in

maximum mode. When it is low, it indicates the CPU is having an

I/O operation, and when it is high, it indicates that the CPU is having

a memory operation. This line becomes active high in the previous

T4 and remains active till final T4 of the current cycle. It is tri-stated

during local bus “hold acknowledge “.

INTA Interrupt Acknowledge: This signal is used as a read strobe

for interrupt acknowledge cycles. i.e. when it goes low, the

processor has accepted the interrupt.

ALE – Address Latch Enable: This output signal indicates the

availability of the valid address on the address/data lines, and is

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connected to latch enable input of latches. This signal is active high

and is never tri-stated.

DT/R – Data Transmit/Receive: This output is used to decide the

direction of data flow through the transceivers (bidirectional

103

buffers). When the processor sends out data, this signal is high and when the

processor is receiving data, this signal is low.

DEN – Data Enable: This signal indicates the availability of valid data over

the address/data lines. It is used to enable the transceivers (bidirectional

buffers) to separate the data from the multiplexed address/data signal. It is

active from the middle of T2 until the middle of T4. This is tristated during ‘

hold acknowledge’ cycle.

HOLD, HLDA- Acknowledge: When the HOLD line goes high, it indicates to

the processor that another master is requesting the bus access. The

processor, after receiving the HOLD request, issues the hold acknowledge

signal on HLDA pin, in the middle of the next clock cycle after completing

the current bus cycle At the same time, the processor floats the local bus

and control lines. When the processor detects the HOLD line low, it lowers

the HLDA signal. HOLD is an asynchronous input, and is should be externally

synchronized.

The following pin functions are applicable for maximum mode operation of

8086 microprocessor:

S2, S1, S0 – Status Lines: These are the status lines which reflect the type of

operation, being carried out by the processor. These become activity during

T4 of the previous cycle and active during T1 and T2 of the current bus

cycles.

Web Resource

http://nptel.ac.in/courses/106108100/pdf/Teacher_Slides/mod1/M1L3.

pdf

Follow the above link to some informative PowerPoint slides on the 8086

microprocessor architecture.

the address to memory or I/O and the ALE signal for Demultiplexing?

67

66

1.1 In which T - state does the CPU sends

Review Questions

A. T1

68

B. T2

69

C. T3

70

D. T4

71

ANSWER: During the first clocking period in a bus cycle, which is called

T1,

72

the address of the memory or I/O location is sent out and the control

73

signals ALE, DT/R’ and IO/M’ are also output. Hence answer is (A).

74

1.2 Ready pin of a microprocessor is used …………..

75

A. to indicate that the microprocessor is ready to receive inputs

76

B. to indicate that the microprocessor is ready to receive outputs

77

C. to introduce wait states

78

D. to provide direct memory access

79

ANSWER: This input is controlled to insert wait states into the timing of

the

80

microprocessor. Hence answer is (C)

81

1.3 Identify the correct statement from the following.

82

A. The group of machine cycle is called a state

83

B. A machine cycle consists of one or more instruction cycle

84

C. An instruction cycle is made up of machine cycles and a machine

85

cycle is made up of number of states

86

D. A state is a set of instructions

87

ANSWER: An instruction cycle consists of several machine cycles. Hence

88

Answer is (B)

89

1.4 Which microprocessor pins are used to request and acknowledge a

90

DMA

91

transfer?

92

A. Reset and Ready

93

B. Ready and Wait

94

C. HOLD and HLDA

95

D. Reset and Wait

96

ANSWER: The HOLD pin is an input that is used request a DMA action and

97

the HLDA pin is an output that that acknowledges the DMA action. Hence

98

answer is (C).

99

100

2.1 How do you classify the instruction set of the 8086 microprocessor?

101

2.2 Distinguish between the minimum and maximum mode of operation.

102

176

177

TOPIC THREE | MICROCONTROLLERS

LEARNING OUTCOMES

178

1. Demonstrate a sound understanding of the 8051 standard.

2. Demonstrate an understanding of the 8051 microcontroller's pins

and it’s Input/output Ports (I/O Ports)

3. Demonstrate a specialist knowledge on 8051 microcontroller

memory organisation.

4. Demonstrate an understanding of Special Function Registers (SRF),

Counters and Timers.

5. Demonstrate a sound understanding of the Universal

Asynchronous Receiver and Transmitter (UART)

6. Demonstrate a specialist knowledge on 8051 Microcontroller

Interrupts and 8051 Microcontroller Power Consumption Control.

3.1 Introduction to Microcontrollers

The purpose of this chapter is to introduce the concept of a microcontrollers,

how they differ from microprocessors, and different types of commercial

microcontrollers available as well as their applications.

A microcontroller is a highly integrated chip, which includes on single chip, all

or most of the parts needed for a controller. The microcontroller typically

includes:

Central Processing Unit (CPU)

Random Access Memory (RAM)

Read Only Memory (ROM)

Programmable Read Only Memory (PROM)

Erasable Programmable Read Only Memory

(EPROM)

Input/Output (I/O) – serial and parallel, timers,

interrupt controller. By only including the features specific to

the task (control), cost is relatively low. A typical

microcontroller has bit manipulation instructions, easy and

direct access to I/O (input/output), and quick and efficient

interrupt processing. Unlike a general-purpose computer,

which also includes all of these components, a microcontroller

is designed for a very specific task - to control a particular

system. A microcontroller differs from a microprocessor, which

is a generalpurpose chip that is used to create a multi-function

computer or device and requires multiple chips to handle

various tasks.

179

The great advantage of microcontrollers, as opposed to using larger

microprocessors, is that the parts-count and design costs of the item being

controlled can be kept to a minimum. They are typically designed using CMOS

(complementary metal oxide semiconductor) technology, an efficient

fabrication technique that uses less power and is more immune to power spikes

than other techniques. Figure 3.1 below shows the block diagram of a typical

microcontroller.

Figure 3.1: A block diagram of a

microcontroller

Microcontrollers are sometimes referred to as an embedded microcontroller,

which just means that they are part of an embedded system that is, one part of

a larger device or system.

3.2 The Controller

A device that controls the transfer of data from a computer to a peripheral

device and vice versa. For example, disk drives, display screens, keyboards and

printers all require controllers. In personal computers, the controllers are often

single chips. When you purchase a computer, it comes with all the necessary

controllers for standard components, such as the display screen, keyboard, and

disk drives. If you attach additional devices, however, you may need to insert

new controllers that come on expansion boards. Controllers must be designed

to communicate with the computer's expansion bus.

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There are three standard bus architectures for PCs - the AT bus, Peripheral

Component Interconnect (PCI) and SCSI. When you purchase a controller,

therefore you must ensure that it conforms to the bus architecture of your PC.

3.3 Embedded Systems

A general-purpose definition of embedded systems is that they are devices

used to control, monitor or assist the operation of equipment, machinery or

plant. “Embedded” reflects the fact that they are an integral part of the system.

In many cases, their “embeddedness” may be such that their presence is far

from obvious to the casual observer. An embedded system is a system that has

software embedded into hardware, which makes a system dedicated for an

application (s) or specific part of an application or product or part of a larger

system. It processes a fixed set of pre-programmed instructions to control

electromechanical equipment which may be part of an even larger system (not

a computer with keyboard, display, etc). The block diagram of a typical

embedded system is shown in Fig 3.2.

Figure 3.2: Block Diagram of an Embedded System

A specialized computer system that is part of a larger system or machine.

Typically, an embedded system is housed on a single microprocessor board

with the programs stored in ROM. Virtually all appliances that have a digital

Interface- watch, microwaves, VCRs, cars -utilize embedded systems. Some

embedded systems include an operating system, but many are so specialized

that the entire logic can be implemented as a single program.

3.3.1 Characteristics of Embedded Systems

Embedded systems are application specific & single functioned; application

is known apriori, the programs are executed repeatedly.

Efficiency is of paramount importance for embedded systems. They are

optimized for energy, code size, execution time, weight & dimensions, and

cost.

181

Embedded systems are typically designed to meet real time constraints; a

real time system reacts to stimuli from the controlled object/ operator

within the time interval dictated by the environment.

Embedded systems often interact (sense, manipulate & communicate) with

external world through sensors and actuators and hence are typically

reactive systems; They generally have minimal or no user interface.

3.4 Microprocessors versus Microcontrollers

Microprocessor is a single chip CPU, microcontroller contains, a CPU

and much of the remaining circuitry of a complete microcomputer

system in a single chip.

Microcontroller includes RAM, ROM, serial and parallel interface,

timer, interrupt schedule circuitry (in addition to CPU) in a single

chip. RAM is smaller than that of even an ordinary microcomputer,

but enough for its applications. Interrupt system is an important

feature, as microcontrollers have to respond to control oriented

devices in real time. E.g., opening of microwave oven’s door cause

an interrupt to stop the operation. (Most microprocessors can also

implement powerful interrupt schemes, but external components

are usually needed).

Microprocessors are most commonly used as the CPU in

microcomputer systems. Microcontrollers are used in small,

minimum component designs performing control-oriented

activities.

Microprocessor instruction sets are “processing intensive”,

implying powerful addressing modes with instructions catering to

large volumes of data. Their instructions operate on nibbles, bytes,

etc. Microcontrollers have instruction sets catering to the control of

Figure 3.3: Microcontroller and Microprocessor

182

inputs and outputs. Their instructions operate also on a single bit.

E.g., a motor may be turned ON and OFF by a 1-bit output port.

Microprocessors and microcontrollers are widely used in embedded systems’

products. An embedded project uses a microprocessor or a microcontroller to

do one task only. For example, a printer is an embedded system that does one

task, get data and print it.

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3.5 The 8051 Standard

Microcontroller manufacturers have been competing for a long time for

attracting choosy customers and every couple of days a new chip with a higher

operating frequency, more memory and upgraded A/D converters appeared on

the market. However, most of them h ad the same or at least very similar

architecture known in the world of microcontrollers as “8051 compatible”. The

whole story has its beginnings in the far 80s when Intel launched the first series

of microcontrollers called the MCS 051. Even though thes e microcontrollers

had quite modest features in comparison to the new ones, they conquered the

world very soon and became a standard for what nowadays is called the

microcontroller.

The main reason for their great success and popularity is a skilfully chosen

configuration which satisfies different needs of a large number of users

allowing at the same time constant expansions (refers to the new types of

microcontrollers). Besides, the software has been developed in great extend in

the meantime, and it simply was not profitable to change anything in the

microcontroller’s basic core. This is the reason for having a great number of

various microcontrollers which basically are solely upgrad ed versions of the

8051 family. What makes this microcontroller so special and universal so that

almost all manufacturers all over the world manufacture it today under

different name?

Figure 3.5: 8051 Microcontroller

As seen in figure above, the 8051 microcontroller has nothing impressive in

appearance:

4 Kb of ROM is not much at all.

b of RAM (including SFRs) satisfies the user's basic needs. 128

4 ports having in total of 32 input/output lines are in most cases

sufficient to make all necessary connections to peripheral

environment.

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The whole configuration is obviously thought of as to satisfy the needs of most

programmers working on development of automation devices. One of its

advantages is that nothing is m issing and nothing is too much. In other words,

it is created exactly in accordance to the average user‘s taste and needs.

Another advantages are RAM organization, the operation of Central Processor

Unit (CPU) and ports which completely use all recourses a nd enable further

upgrade.

Pin Description 3.6 8051

The 8051 microcontroller uses a 40 PIN Integrated Circuit. Figure 3.6 shows the

Pins of IC of 8051 micro - controller.

Figure 3.6: The 8051 Microcontroller Pins

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Explanation for each PIN is given below:

Pins 1 to 8(Port 1): The Pins 1.0 to 1.7 are 8 Pins of port 1. Each of them can be

configured as input or output pin.

Pin 9: It is used to Reset Microcontroller 8051. A positive pulse is given on this

Pin to reset Microcontroller.

Pin 10 to 17(Port 3): These Pins are similar to Pins of Port 1. These Pins can be

used as universal Input or output. These are dual function Pins. Function of each

Pin is given as:

Pin 10: It is Serial Asynchronous Communication Input or Serial

Asynchronous Communication Output.

Pin 11: Serial Asynchronous Communication Output or Serial

Synchronous Communication Output.

Pin 12: Interrupt 0 input Pin 13: Interrupt 1 input.

Pin 14: Counter 0 clock input.

Pin 15: Counter 1 clock input.

Pin 16: Writing Signal for writing content on external RAM.

Pin 17: Reading Signal to read contents of external RAM. Pin 18 and 19:

These are input output PINS for oscillator. An internal oscillator is connected to

Micro controller through these PINS.

Pin 20: Pin 20 is grounded.

Pin 21 to 28 (Port 2): These Pins can be configured as Input Output Pins. But this

is only possible in case when we don't use any external memory. If we use

external memory then these pins will work as high order address bus (A8 to

A15).

Pin 29: If we uses an external ROM then it should has a logic 0 which indicates

Micro controller to read data from memory.

Pin 30: This Pin is used for ALE that is Address Latch Enable. If we uses multiple

memory chips then this pin is used to distinguish between them. This Pin also

gives program pulse input during programming of EPROM.

Pin 31: If we have to use multiple memories then by applying logic 1 to this pin

instructs Micro controller to read data from both memories first internal and

afterwards external.

Pin 32 to 39(Port 0): Similar to port 2 and 3, these pins can be used as input

output pins when we don't use any external memory. When ALE or Pin 30 is at

1 then this port is used as data bus, when ALE pin at 0, then this port is used as

lower order address bus(A0 to A7).

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Input and Output Ports (I/O Ports) 3.7

All 8051 microcontrollers have four I/O ports each comprising 8 bits which can

be configured as inputs or outputs. Accordingly, in total of 32 input/output pins

enabling the microcontroller to be connected to peripheral devices are

available for use.

Pin configuration, i.e. whether it is to be configured as an input (1) or an output

(0) , depends on its logic state. In order to configure a microcontroller pin as an

input, it is necessary to apply a logic zero (0) to appropriate I/O port bit. In this

case, voltage level on appropriate pin will be 0.

Similarly, in order to configure a microcontroller pin as an input, it is necessary

to apply a logic one (1) to appropriate port. In this case, voltage level on

appropriate pin will be 5V (as is the case with any TTL input). This may seem

confusing but don't lose your patience. It all becomes clear after studying

simple electronic circuits connected to an I/O pin.

Figure 3.7: Circuitry inside the Microcontroller

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Input/Output Pin

Figure 3.8 below illustrates a simplified schematic of all circuits within the

microcontroller connected to one of its pins. It refers to all the pins except

those of the P0 port which do not have pull-up resistors built-in.

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Output pin

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A

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logic zero (0) is applied to a bit of the P register. The output FE transistor is

turned on, thus connecting the appropriate pin to ground.

Input pin

A logic one (1) is applied to a bit of the P register. The output FE transistor is

turned off and the appropriate pin remains connected to the power supply

voltage over a pull-up resistor of high resistance.

Figure 3.10: Input pin circuitry

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Port 1

P1 is a true I/O port, because it doesn't have any alternative functions as is the

case with P0, but can be configured as general I/O only. It has a pull-up resistor

built-in and is completely compatible with TTL circuits.

Port 2

P2 acts similarly to P0 when external memory is used. Pins of this port occupy

addresses intended for external memory chip. This time it is about the higher

address byte with addresses A8-A15. When no memory is added, this port can

be used as a general input/output port showing features similar to P1. Port 3

All port pins can be used as general I/O, but they also have an alternative

function. In order to use these alternative functions, a logic one (1) must be

applied to appropriate bit of the P3 register. In terms of hardware, this port is

similar to P0, with the difference that its pins have a pull-up resistor built-in.

Pin's Current Limitations

When configured as outputs (logic zero (0)), single port pins can receive a

current of 10mA. If all 8 bits of a port are active, a total current must be limited

to 15mA (port P0: 26mA). If all ports (32 bits) are active, total maximum current

must be limited to 71mA. When these pins are configured as inputs (logic 1),

built-in pull-up resistors provide very weak current, but strong enough to

activate up to 4 TTL inputs of LS series.

As seen from description of some ports, even though all of them have more or

less similar architecture, it is necessary to pay attention to which of them is to

be used for what and how.

For example, if they shall be used as outputs with high voltage level (5V), then

P0 should be avoided because its pins do not have pull-up resistors, thus giving

low logic level only. When using other ports, one should have in mind that pull-

up resistors have a relatively high resistance, so that their pins can give a current

of several hundred microamperes only.

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Web Resource

https://www.youtube.com/watch?v=pz57y4BHIy0

This video covers the internal architecture, pin diagram, registers, RAM

memory location and some of the special function registers of 8051

microcontroller. Hereby, you can learn each and every block of

architecture and also explained its pin details specially port pins and how

all the registers are stored in memory, it may be general purpose or

special purpose registers and what is its specified address.

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3.8 Memory Organization

The 8051 has two types of memory and these are Program Memory and Data

Memory. Program Memory (ROM) is used to permanently save the program

being executed, while Data Memory (RAM) is used for temporarily storing data

and intermediate results created and used during the operation of the

microcontroller. Depending on the model in use (we are still talking about the

8051 microcontroller family in general) at most a few Kb of ROM and 128 or 256

bytes of RAM is used. All 8051 microcontrollers have a 16-bit addressing bus and

are capable of addressing 64 kb memory. It is neither a mistake nor a big

ambition of engineers who were working on basic core development. It is a

matter of smart memory organization which makes these microcontrollers a

real “programmers’ goody“.

The 8051 microprocessor has 128 byte Random Access memory for data

storage. Random access memory is non-volatile memory. During execution for

storing the data the RAM is used. RAM consists of the register banks, stack for

temporary data storage. It also consists of some special function register (SFR)

which are used for some specific purpose like timer, input output ports etc.

Normally microcontroller has 256 byte RAM in which 128 byte is used for user

space which is normally Register banks and stack.

Figure 3.13: Memory Addressing

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containing it. The next memory block (address 20h-2Fh) is bit- addressable,

which means that each bit has its own address (0-7Fh).

Since there are 16 such registers, this block contains in total of 128 bits with

separate addresses (address of bit 0 of the 20h byte is 0, while address of bit 7

of the 2Fh byte is 7Fh). The third group of registers occupy addresses 2Fh-7Fh,

i.e. 80

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Imagine for a moment that you're an

engineer designing a new 8051based product. Not unexpectedly, the

application's code size will greatly exceed the 64KB architectural limit

of the 8051's program memory. Which of the following two methods

would you chose to get the needed extra program memory space? Do

you expand the program memory space using a method that wastes a

large amount of physical memory; makes some of the 8051 I/O pins

unusable; segments the memory into disjointed pages; slows down

the execution of the program; and uses extra bytes in the 8051's

internal data memory?

Or do you expand the program memory space using a method that

employs all available physical memory up to 512KB; uses no 8051 I/O

pins; provides a linear, no segmented 512KB of program memory;

executes the program at full speed with no performance penalty; and

uses no internal data memory resources?

locations, and does not have any special functions or features.

Additional RAM

In order to satisfy the programmers’ constant hunger for Data Memory, the

manufacturers decided to embed an additional memory block of 128 locations

into the latest versions of the 8051 microcontrollers. However, it’s not as

simple as it seems to be… The problem is that electronics performing

addressing has 1 byte (8 bits) on disposal and is capable of reaching only the

first 256 locations, therefore. In order to keep already existing 8-bit

architecture and compatibility with other existing models a small trick was

done.

What does it mean? It means that additional memory block shares the same

addresses with locations intended for the SFRs (80h-FFh). In order to

differentiate between these two physically separated memory spaces,

different ways of addressing are used. The SFRs memory locations are accessed

by direct addressing, while additional RAM memory locations are accessed by

indirect addressing.

THINK POINT

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3.9 Memory Expansion

In case memory (RAM or ROM) built in the microcontroller is not sufficient, it is

possible to add two external memory chips with capacity of 64Kb each. P2 and

P3 I/O ports are used for their addressing and data transmission. From the user’s

point of view, everything works quite simply when properly connected because

most operations are performed by the microcontroller itself.

The 8051 microcontroller has two pins for data read RD# (P3.7) and PSEN#. The

first one is used for reading data from external data memory (RAM), while the

other is used for reading data from external program memory (ROM). Both pins

are active low. A typical example of memory expansion by adding RAM and ROM

chips (Hardware architecture), is shown in figure above. Even though additional

memory is rarely used with the latest versions of the microcontrollers, we will

describe in short what happens when memory chips are connected according

to the previous schematic. The whole process described below is performed

automatically. When the program during execution encounters an instruction

which resides in external memory (ROM), the microcontroller will activate its

control output ALE and set the first 8 bits of address (A0-A7) on P0. IC circuit

74HCT573 passes the first 8 bits to memory address pins. A signal on the ALE pin

latches the IC circuit 74HCT573 and immediately afterwards 8 higher bits of

address (A8-A15) appear on the port. In this way, a desired location of additional

program memory is addressed. It is left over to read its content. Port P0 pins are

configured as inputs, the PSEN pin is activated and the microcontroller reads

from memory chip. Similar occurs when it is necessary location from external

RAM.

Figure 3.15 Expanding 8051 Memory

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Addressing

While operating, the processor processes data as per program instructions. Each

instruction consists of two parts. One part describes what should be done, while

the other explains HOW to do it. The latter part can be a data (binary number)

or the address at which the data is stored. Two ways of addressing are used for

all 8051 microcontrollers depending on which part of memory:

Direct Addressing

On direct addressing, the address of memory location containing data to be read

is specified in instruction. The address may contain a number being changed

during operation (variable). For example, since the address is only one byte in

size (the largest number is 255), only the first 255 locations of RAM can be

accessed this way. The first half of RAM is available for use, while another half

is reserved for SFRs.MOV A, 33h; Means: move a number from address 33 hex

to accumulator.

Indirect Addressing

On indirect addressing, a register containing the address of another register is

specified in instruction. Data to be used in the program is stored in the letter

register. For example: Indirect addressing is only used for accessing RAM

locations available for use (never for accessing SFRs). This is the only way of

accessing all the latest versions of the microcontrollers with additional memory

block (128 locations of RAM). Simply put, when the program encounters

instruction including “@” sign and if the specified address is higher than 128 (7F

hex.), the processor knows that indirect addressing is used and skips memory

space reserved for SFRs.

On indirect addressing, registers R0, R1 or Stack Pointer are used for specifying

8-bit addresses. Since only 8 bits are available, it is possible to access only

registers of internal RAM this way (128 locations when speaking of previous

models or 256 locations when speaking of latest models of microcontrollers). If

an extra memory chip is added then the 16-bit DPTR Register (consisting of the

registers DPTRL and DPTRH) is used for specifying address. In this way it is

possible to access any location in the range of 64K.

MOV A, @R0; Means: Store the value from the register whose address is in the

R0 register into accumulator.

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This is how it looks in the program:

MOV A, R3; Means: move number from R3 into accumulator

ADD A, R4; Means: add number from R4 to accumulator (result

remains in accumulator)

MOV R5, A; Means: temporarily move the result from

accumulator into R5

MOV A, R1; Means: move number from R1 to accumulator

ADD A, R2; Means: add number from R2 to accumulator

SUBB A, R5; Means: subtract number from R5 (there are R3+R4)

Program Status Word (PSW) Register

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PSW register is one of the most important SFRs. It contains several status bits

that reflect the current state of the CPU. Besides, this register contains Carry bit,

Auxiliary Carry, two register bank select bits, Overflow flag, parity bit and user-

definable status flag.

P - Parity bit. If a number stored in the accumulator is even then this bit will be

automatically set (1), otherwise it will be cleared (0). It is mainly used during

data transmit and receive via serial communication.

Bit 1. This bit is intended to be used in the future versions of microcontrollers.

OV Overflow occurs when the result of an arithmetical operation is larger than

255 and cannot be stored in one register. Overflow condition causes the OV bit

to be set (1). Otherwise, it will be cleared (0).

RS0, RS1 - Register bank select bits. These two bits are used to select one of

four register banks of RAM. By setting and clearing these bits, registers R0-R7

are stored in one of four banks of RAM.

F0 - Flag 0. This is a general-purpose bit available for use.

AC - Auxiliary Carry Flag is used for BCD operations only.

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CY - Carry Flag is the (ninth) auxiliary bit used for all arithmetical operations and

shift instructions.

Data Pointer Register (DPTR)

DPTR register is not a true one because it doesn't physically exist. It consists of

two separate registers: DPH (Data Pointer High) and (Data Pointer Low). For this

reason it may be treated as a 16 - bit register or as two independent 8 - bit

registers. Their 16 bits are primarily used for external memory addressing.

Besides, the DPTR Register is usually used for storing data and intermediate

results.

Stack Pointer (SP) Register

A value stored in the Stack Pointer points to the first free stack address and

permits stack availability. Stack pushes increment the value in the Stack Pointer

by 1. Likewise, stack pops decrement its value by 1. Upon any reset and

poweron, the value 7 is stored in the Stack Pointer, which means that the space

of RAM reserved for the stack starts at this location. If another value is written

to this register, the entire Stack is moved to the new memory location.

P0, P1, P2, P3 - Input/ Output Register s

If neither external memory nor serial communication system are used then 4

ports within total of 32 input/output pins are available for connection to

peripheral environment. Each bit within these ports affects the state and

Figure 3. 17 Data pointer Register

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performance of appropriate pin of the microcontroller. Thus, bit logic state is

reflected on appropriate pin as a voltage (0 or 5 V) and vice versa, voltage on a

pin reflects the state of appropriate port bit. As mentioned, port bit state

affects performance of port pins, i.e. whether they will be configured as inputs

or outputs. If a bit is cleared (0), the appropriate pin will be configured as an

output, while if it is set (1), the appropriate pin will be configured as an input.

Upon reset and power-on, all port bits are set (1), which means that all

appropriate pins will be configured as inputs. I/O ports are directly connected

to the microcontroller pins. Accordingly, logic state of these registers can be

checked by voltmeter and vice versa, voltage on the pins can be checked by

inspecting their bits!

Counters and Timers

As you already know, the microcontroller oscillator uses quartz crystal for its

operation. As the frequency of this oscillator is precisely defined and very

stable, pulses it generates are always of the same width, which makes them

ideal for time measurement. Such crystals are also used in quartz watches. In

order to measure time between two events it is sufficient to count up pulses

coming from this oscillator. That is exactly what the timer does. If the timer is

properly programmed, the value stored in its register will be incremented (or

decremented) with each coming pulse, i.e. once per each machine cycle. A

single machine-cycle instruction lasts for 12 quartz oscillator periods, which

means that by embedding quartz with oscillator frequency of 12MHz, a number

stored in the timer register will be changed million times per second, i.e. each

microsecond.

The 8051 microcontroller has 2 timers/counters called T0 and T1. As their

names suggest, their main purpose is to measure time and count external

events. Besides, they can be used for generating clock pulses to be used in serial

communication, so called Baud Rate.

Timer T0

As seen in figure below, the timer T0 consists of two registers – TH0 and TL0

representing a low and a high byte of one 16-digit binary number.

Figure 3.18: Timer T0

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Timer 0 in Mode 0 (13 – bit Timer)

This is one of the rarities being kept only for the purpose of compatibility with

the previous versions of microcontrollers. This mode configures timer 0 as a

13 bit timer which consists o f all 8 bits of TH0 and the lower 5 bits of TL0. As a

result, the Timer 0 uses only 13 of 16 bits. How does it operate? Each coming

pulse causes the lower register bits to change their states. After receiving 32

pulses, this register is loaded and automati cally cleared, while the higher byte

( TH0) is incremented by 1. This process is repeated until registers count up 8192

pulses. After that, both registers are cleared and counting starts from 0.

Timer 0 in Mode 1 (16 - bit timer)

Mode 1 configures timer 0 as a 16 - bit timer comprising all the bits of both

registers TH0 and TL0. That's why this is one of the most commonly used modes.

Timer operates in the same way as in mode 0, with difference that the registers

count up to 65 536 as allowable by the 16 bits.

Figure 3.22: Timer 0 in Mode 1

Figure 3.21: Time 0 in Mode 0

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Thus, its operation is restricted when timer 0 is in mode 3. The only application

of this mode is when two timers are used and the 16-bit Timer 1 the operation

of which is out of control is used as a baud rate generator.

Timer 0 in mode 3 becomes two completely separate 8-bit counters. TL0 is

controlled by the gate arrangement of Figure 11 and sets timer flag TF0

whenever it overflows from FFh to 00h. TH0 receives the timer clock (the

oscillator divided by 12) under the control of TR 1 only and sets the TF1 flag

when it overflows.

Timer 1 may still be used in modes 0, 1, and

2, while timer 0 is in mode 3 with one

important exception: No interrupts will be

generated by timer I while timer 0 is using

the TF1 overflow flag. Switching timer I to

mode 3 will stop it

(and hold whatever count is in timer 1).

Timer 1 can be used for baud rate

generation for the serial port, or any other

mode 0, 1, or 2 function that does not

depend upon an interrupt (or any other use

of the TF1 flag) for proper operation.

Counting

The only difference between counting and timing is the source of the clock

pulses to the counters. When used as a timer, the clock pulses are sourced from

RESEARCH

Write an essay outlining the

difference between a timer and a

counter operation of the 8051

microcontroller. In your essay

explain how one would start/stop

the timer/counter when:

i. GATE control is not used ii.

GATE control is used

Figure 3.24: Timer 0 in Mode 3

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the oscillator through the divide-by-12d circuit. When used as a counter, pin T0

(P3.4) supplies pulses to counter 0 and pin T1 (P3.5) to counter 1.

The input pulse on TX is sampled during P2 of state 5 every machine cycle. A

change on the input from high to low between samples will increment the

counter. Each high and low state of the input pulse must thus be held constant

for at least one machine cycle to ensure reliable counting. Since this takes 24

pulses, the maximum input frequency that can be accurately counted is the

oscillator frequency divided by 24 for our 6 megahertz crystal. The calculation

yields a maximum external frequency of 250 kilohertz. The 8051 timer has three

general functions:

Keeping time and calculating the amount of time between events.

Counting events.

Generating baud rates for serial ports.

When used as a timer, the 8051’s crystal is used as the source of frequency.

However, when used as a counter, it is a pulse outside of the 8051 that

increments the TH and TL registers.

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Web Resource

https://www.youtube.com/watch?v=0SZPr4iGACg

Follow the link above to learn in the basics of Timer/ Counter operations

from the video tutorial presented.

The link below will take you to some tutorial slides on how a counter

works.

http://www.slideshare.net/ankit3991/8051-timer-counter

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Mode 1

In mode 1, 10 bits are transmitted through the TXD pin or received through the

RXD pin in the following manner: a START bit (always 0), 8 data bits (LSB first)

and a STOP bit (always 1). The START bit is only used to initiate data receive,

while the STOP b it is automatically written to the RB8 bit of the SCON register.

Multiprocessor Communication

As you may know, additional 9th data bit is a part of message in mode 2 and 3.

It can be used for checking data via parity bit. Another useful application of this

bit is in communication between two or more microcontrollers, i.e.

multiprocessor communicati on. This feature is enabled by setting the SM2 bit

of the SCON register. As a result, after receiving the STOP bit, indicating end of

the message, the serial port interrupt will be generated only if the bit RB8 = 1

the 9th bit). (

Suppose there are severa l microcontrollers sharing the same interface. Each of

them has its own address. An address byte differs from a data byte because it

has the 9th bit set (1), while this bit is cleared (0) in a data byte. When the

microcontroller A (master) wants to transmi t a block of data to one of several

slaves, it first sends out an address byte which identifies the target slave. An

address byte will generate an interrupt in all slaves so that they can examine

the received byte and check whether it matches their address .

Of course, only one of them will match the address and immediately clear the

SM2 bit of the SCON register and prepare to receive the data byte to come.

Other slaves not being addressed leave their SM2 bit set ignoring the coming

data bytes.

Figure 3.25 Mode 0

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8051 Microcontroller Interrupts

There are five interrupt sources for the 8051, which means that they can

recognize 5 different events that can interrupt regular program execution. Each

interrupt can be enabled or disabled by setting bits of the IE register. Likewise,

the whole interrupt system can be disabled by clearing the EA bit of the same

register. Now, it is necessary to explain a few details referring to external

interrupts- INT0 and INT1. If the IT0 and IT1 bits of the TCON register are set, an

interrupt will be generated on high to low transition, i.e. on the falling pulse

edge (only in that moment). If these bits are cleared, an interrupt will be

continuously executed as far as the pins are held low.

IE Register (Interrupt Enable)

Interrupt Priorities

It is not possible to foresee when an interrupt request will arrive. If several

interrupts are enabled, it may happen that while one of them is in progress,

another one is requested. In order that the microcontroller knows whether to

continue operation or meet a new interrupt request, there is a priority list

instructing it what to do.

The priority list offers 3 levels of interrupt priority:

1. Reset! The absolute master. When a reset request arrives, everything is

stopped and the microcontroller restarts.

2. Interrupt priority 1 can be disabled by Reset only.

3. Interrupt priority 0 can be disabled by both Reset and interrupt priority

1. The IP Register (Interrupt Priority Register) specifies which one of existing

interrupt sources have higher and which one has lower priority. Interrupt

priority is usually specified at the beginning of the program. According to that,

there are several possibilities:

If an interrupt of higher priority arrives while an interrupt is in progress,

it will be immediately stopped and the higher priority interrupt will be executed

first.

If two interrupt requests, at different priority levels, arrive at the same

time then the higher priority interrupt is serviced first.

If the both interrupt requests, at the same priority level, occur one after

another, the one which came later has to wait until routine being in progress

ends.

If two interrupt requests of equal priority arrive at the same time then

the interrupt to be serviced is selected according to the following priority list:

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Handling Interrupts

When an interrupt request arrives the following occurs:

Instruction in progress is ended.

The address of the next instruction to execute is pushed on the stack.

Depending on which interrupt is requested, one of 5 vectors

(addresses) is written to the program counter in accordance to the table below:

These addresses store appropriate subroutines processing interrupts.

Instead of them, there are usually jump instructions specifying locations on

which these subroutines reside.

When an interrupt routine is executed, the address of the next

instruction to execute is poped from the stack to the program counter and

interrupted program resumes operation from where it left off.

From the moment an interrupt is enabled, the microcontroller is on

alert all the time. When an interrupt request arrives, the program execution is

stopped, electronics recognizes the source and the program “jumps” to the

appropriate address (see the table above). This address usually stores a jump

instruction specifying the start of appropriate subroutine. Upon its execution,

the program resumes operation from where it left off.

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INTERRUPT SOURCE VECTOR (ADDRESS)

IE0 3 h

B h

1B h

TF0

TF1

RI, TI 23 h

All addresses are in hexadecimal format

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Reset

Reset occurs when the RS pin is supplied with a positive pulse in duration of at

least 2 machine cycles (24 clock cycles of crystal oscillator). After that, the

microcontroller generates an internal reset signal which clears all SFRs, except

SBUF registers, Stack Pointer and ports (the state of the first two ports is not

defined, while FF value is written to the ports configuring all their pins as inputs).

Depending on surrounding and purpose of device, the RS pin is usually

connected to a power-on reset push button or circuit or to both of them. Figure

below illustrates one of the simplest circuits providing safe power-on reset.

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Figure 3.27 Reseting

Basically, everything is very simple: after turning the power on, electrical capacitor is being charged for

several milliseconds through a resistor connected to the ground. The pin is driven high during this process.

When the capacitor is charged, power supply voltage is already stable and the pin remains connected to the

ground, thus providing normal operation of the microcontroller. Pressing the reset button causes the

capacitor to be temporarily discharged and the microcontroller is reset. When released, the whole process

is repeated.

8051 Microcontroller Power Consumption Control

Generally speaking, the microcontroller is inactive for the most part and just waits for some external signal

in order to takes its role in a show. This can cause some problems in case batteries are used for power supply.

In extreme cases, the only solution is to set the whole electronics in sleep mode in order to minimize

consumption. A typical example is a TV remote controller: it can be out of use for months but when used

again it takes less than a second to send a command to TV receiver. The AT89S53 uses approximately 25mA

for regular operation, which doesn't make it a power-saving microcontroller. Anyway, it doesn’t have to be

always like that, it can easily switch the operating mode in order to reduce its total consumption to

approximately 40uA. Actually, there are two power saving modes of operation: Idle and Power Down.

Idle mode

Upon the IDL bit of the PCON register is set, the microcontroller turns off the greatest power consumer- CPU

unit while peripheral units such as serial port, timers and interrupt system continue operating

normally consuming 6.5mA. In Idle mode, the state of all registers and I/O ports remains

unchanged.

226

In order to exit the Idle mode and make the microcontroller operate normally,

it is necessary to enable and execute any interrupt or reset. It will cause the IDL

bit to be automatically cleared and the program resumes operation from

instruction having set the IDL bit. It is recommended that first three instructions

to execute now are NOP instructions. They don't perform any operation but

provide some time for the microcontroller to stabilize and prevents undesired

changes on the I/O ports.

Power Down mode

By setting the PD bit of the PCON register from within the program, the

microcontroller is set to Power down mode, thus turning off its internal

oscillator and reduces power consumption enormously. The microcontroller can

operate using only 2V power supply in power- down mode, while total power

consumption is less than 40uA. The only way to get the microcontroller back to

normal mode is by reset.

While the microcontroller is in Power Down mode, the state of all SFR registers

and I/O ports remains unchanged. By setting it back into the normal mode, the

contents of the SFR register is lost, but the content of internal RAM is saved.

Reset signal must be long enough, approximately 10mS, to enable stable

operation of the quartz oscillator.

Figure 3.28: Idle and Power Down mode

227

Identify the electronic components that are not found on ordinary Integrated

142

Circuits.

A. Diodes

144

B. Transistors

C. Resistors

146

D. Inductors

141 SECTION A: MULTI PLE CHOICE QUESTIONS

Review Questions

Which one is not the function of the Microprocessor?

148

A. Receive data from an input device

B. Process data

150

C. Regulates power

D. Send data to an output device

152

What type of control pins are needed in a microprocessor to regulate traffic on

the bus, in order to prevent two devices from trying to use it at the same time?

154

A. Bus control

B. Interrupts

156

C. Bus arbitration

D. Status

158

Which instruction cannot force the 8086 processor out of ‘halt’ state?

A. Interrupt request

160

B. Reset

C. Interrupt request and Reset

162

D. Hold

The circuits in the 8085 microprocessor that provide the arithmetic and logic

164

functions are called the:

A. CPU

166

B. ALU

C. I/O

168

D. PC

Single-bit indicators that may be set or cleared to show the results of logical or

170

arithmetic operations are the called ……………….

A. flags

172

B. registers

C. buses

174

D. monitors

176

178

a mnemonic is …………………

180

A. a short abbreviation for the operand address

B. a short abbreviation for the operation to be performed

182

C. a short abbreviation for the data word stored at the operand address D.

shorthand for machine language

184

When referring to instruction words,

Review Questions

A register in the microprocessor that keeps track of the answer or results of any

arithmetic or logic operation is the ………………

186

A. stack pointer

B. program counter

188

C. instruction pointer

D. accumulator

190

In 8085 microprocessor, an example of a non maskable interrupts is ……..

A. TRAP

192

B. RST 5.5

C. RST 6.5

194

D. INTR

What is used to store critical pieces of data during subroutines and interrupts?

196

A. Stack

B. Queue

198

C. Accumulator

D. Data register

200

Which of the following buses is primarily used to carry signals that direct other

ICs to find out what type of operation is being performed?

202

A. data bus

B. control bus

204

C. address bus

D. memory bus

206

Identify the addressing mode that is not possible in the 8085 microprocessor.

A. Indexed addressing

208

B. Indirect addressing

C. Direct addressing

210

D. Indirect register address

What does the microprocessor speed depend on ……………..

212

A. the clock

B. the data bus width

214

C. the address bus width

D. the size of register

216

218

flag is set when ………………

220

A. the sum is more than 16 bit

B. signed numbers go out of their range after an arithmetic operation

222

C. the carry and sign flags are set.

D. the zero flag is set.

224

The cache usually gets its data from the ………….. whenever the instruction or

In 8086 microprocessor the over flow

Review Questions

data is required by the CPU.

226

A. main memory

B. secondary memory

228

C. control memory

D. cycle memory

230

Different components on the motherboard of a PC unit are linked together by

sets of parallel electrical conducting lines. What are these lines called?

232

A. Conductors B.

Buses

234

C. Connectors

D. Consecutives

236

The Central Processing Unit (CPU) can read & write data by using …………………….

A. control bus

238

B. data bus

C. address bus

240

D. utility bus

With interrupt-driven I/O, if two or more devices request service at the same

242

time, ..

A. the device closest to the CPU gets priority

244

B. the device that is fastest gets priority

C. the device assigned the highest priority is serviced first

246

D. the system is likely to crash

The necessary steps carried out to perform the operation of accessing either

248

memory or I/O device, constitute a ……………

A. fetch operation

250

B. execute operation

C. machine cycle

252

D. instruction cycle

254

250

252

90

254

In vectored interrupts, how

does the device identify itself

to the processor?

A. By sending the starting

address of the service routine

B. By sending its device id

C. By sending the machine code

for the interrupt service routine D. By sending the last address of the

service routine

What do you understand by the term Op - code?

A. The instruction that is to be executed

B. The value in which an operation acts upon

C. A mnemonic that defines a data size

D. The compiled assembly code

Execution of two or mo re programs by a single CPU is known as …………….

A. multiprocessing

B. multiprogramming

C. multitasking

D. timesharing

Interrupts which are initiated by an I/O drive are called ………………

A. internal interrupts

B. external interrupts

C. software interrupts

D. hardware interrupts

The synchronization between microprocessor and memory is done by …….

A. ALE signal

B. HOLD signal

C. READY signal

D. WAIT signal

When the READY pin of 8085 microprocessor is low …………….

A. the processor will be ready to execute program

B. the processor will enter into wait state for one clock period

C. the processor will enter into wait state until the READY pin is made high

D. the processor will return back from its READY state

Review Questions

255

256

257

258

259

2.1 Describe the

different buses

found in microprocessors. What is the purpose of each of the buses you have

identified?

2.2 Explain priority interrupts of 8085 microprocessor. How does the processor

handle the situation where two or more interrupts go high at the same time?

3.1 The invention of the microprocessor has touched our lives and changed the

world. Do you agree with this statement? Write an argumentative essay

illustrating your viewpoints. Support your answer with practical examples and

theory.

4. Follow the link below to some aptitude questions on microprocessors and

microcontrollers:http://www.slideshare.net/manishpatel_79/questionpaperwith-

solution-the-8051-microcontroller-based-embedded-systemsjunejuly2013-vtu

5. An instruction is a binary pattern designed inside a microprocessor to

perform a specific function. The entire group of instructions, called the instruction

set, determines what functions the microprocessor can perform. These

instructions can be classified into five functional categories.

List and explain these five categories. Explain what may happen if one of the

categories is not functioning correctly.

6. List the four major categories of the benefits of multithreaded

programming. Briefly explain each.

7. Multicore systems present certain challenges for multithreaded

programming. Briefly describe these challenges.

8. Write an argumentative essay on the following topic: Is it feasible for

quantum processors to replace the silicon microprocessors used in

classical computers of today?

Review Questions

SECTION B: ESSAY TYPE QUESTIONS

260

261

GLOSSARY OF TERMS

Ampere: Ampere(s), the unit of electrical current. Current is defined as the amount of charge

that flows past a give point, per unit of time. The symbol I is used for current in equations and

A is the abbreviation for ampere.

Bandwidth: Bandwidth (BW) is a range of frequencies, or information, that a circuit can

handle or the range of frequencies that a signal contains or occupies. Example: An AM

broadcast radio channel in the US has a bandwidth of 10kHz, meaning that it occupies a

10kHz-wide band, such as the frequencies from 760kHz to 770kHz.

262

Bus: Data path that connects to a number of devices. A typical example is the

bus a computer's circuit board or backplane. Memory, processor, and I/O

devices may all share the bus to send data from one to another. A bus acts as a

shared highway and is in lieu of the many devoted connections it would take to

hook every device to every other device. Often misspelled "buss."

Capacitor: A capacitor is a passive electronic component that consists of two

conductive plates separated by an insulating dielectric. A voltage applied to the

plates develops an electric field across the dielectric and causes the plates to

accumulate a charge. When the voltage source is removed, the field and the

charge remain until discharged, storing energy. Capacitance (or C, measured in

farads), dictates the amount of charge that can be stored at a given voltage (a

one-farad capacitor charged to one volt will hold one Coulomb of charge).

Coulomb: Coulomb (abbreviated C) is the standard measure of electrical charge.

Named after Charles-Augustin de Coulomb, it is the amount of charge

accumulated on a one-farad capacitor charged to one volt; or the amount of

charge transported by a one ampere current in one second.

Current: See Ampere

Diode: A two-terminal device that rectifies signals (passes current in only one

direction). Most commonly, a semiconductor consisting of a P-N junction, but

diodes can also be realized using vacuum tube, point-contact,

metalsemiconductor junction (Schottky), and other technologies.

DRAM: Dynamic RAM: Random-Access Memory that uses a continuous clock.

Unlike SRAM, when DRAM is no longer clocked, its data is lost.

EPROM: Erasable programmable read-only memory.

ESD: Electrostatic Discharge: Release of stored static electricity. The potentially

damaging discharge of many thousands of volts that occurs when an electronic

device is touched by a charged body.

Embedded System: A system in which the computer (generally a

microcontroller or microprocessor) is included as an integral part of the system.

Often, the computer is relatively invisible to the user, without obvious

applications, files, or operating systems. Examples of products with invisible

embedded systems are the controller that runs a microwave oven or the engine

control system of a modern automobile.

Gate: The controlling terminal of a FET. A voltage on the gate controls the

current flow between the source and drain. A basic logic element (e.g. AND, OR,

NOT, NAND, NOR, XOR, etc.).

Half - Duplex: Data transmission over a circuit capable of transmitting in either

direction, but not simultaneously.

Heat Sink: Mechanical device that is thermally-connected to a heat-producing

electronic component, designed to conduct heat away from the device. Most

263

heat sinks are aluminium and employ fins to increase surface area and

encourage the transfer of heat to the ambient environment.

Hot Swap: A power supply line controller which allows circuit boards or other

devices to be removed and replaced while the system remains powered up.

Hotswapable devices typically protect against overvoltage, undervoltage, and

inrush current that can cause faults, errors, and hardware damage. Hertz; Hz: A

measure of frequency. An older term is cycles per second, or cps. IC: Integrated

circuit: A semiconductor device that combines multiple transistors and other

components and interconnects on a single piece of semiconductor material.

Microcontroller: A highly integrated microprocessor designed specifically for

use in embedded systems. Microcontrollers typically include an integrated CPU,

memory (a small amount of RAM, ROM, or both), and other peripherals on the

same chip. Common examples are Microchip's PIC, the 8051, Intel's 80196, and

Motorola's 68HCxx series.

Microprocessor: A piece of silicon containing a general-purpose CPU. The most

common examples are Intel's 8085 and 8086 families.

Multiprocessing: The use of more than one processor in a single computer

system. So-called multiprocessor systems usually have a common memory

space through which all of the processors can communicate and share data. In

addition, some multiprocessor systems support parallel processing.

Multitasking: The execution of multiple software routines in pseudoparallel.

Each routine represents a separate thread of execution. The operating system

is responsible for simulating parallelism by parceling out the processor's time to

the individual threads.

264

REFERENCES

Prescribed Material:

265

Krishna, K. 2011.Microprocessors and Microcontrollers: Architecture,

Program and System Design 8085, 8086, 8051, 8096 1𝑠𝑡 Edition, Osca

Publications, India.

Other Referenced Material

Hall, D.V. 1990 Microprocessors and Interfacing: Programming and

Hardware 1𝑠𝑡 Edition,. 1990, McGraw-Hill C, Inc. Place of publication

Gaonkar, R. S. 2002. Microprocessor Architecture, Programming, and

Applications with the 8085 5𝑡ℎ Edition, Prentice Hall.