FABRICATION OF LATERAL OXIDE BARRIERS FOR METAL SINGLE

FABRICATION OF LATERAL OXIDE BARRIERS FOR METAL SINGLE

ELECTRON TRANSISTORS

A DISSERTATION

SUBMITTED TO THE DEPARTMENT OF ELECTRICAL ENGINEERING

AND THE COMMITTEE ON GRADUATE STUDIES

OF STANFORD UNIVERSITY

IN PARTIAL FULFILLMENT OF THE REQUIREMENTS

FOR THE DEGREE OF

DOCTOR OF PHILOSOPHY

Barden N. Shimbo

May 2009

c© Copyright by Barden N. Shimbo 2009

All Rights Reserved

ii

I certify that I have read this dissertation and that, in my opinion, it is fully

adequate in scope and quality as a dissertation for the degree of Doctor of

Philosophy.

(James S. Harris, Jr.) Principal Adviser



Philosophy.

(R. Fabian W. Pease)



Philosophy.

(Krishna Saraswat)

Approved for the University Committee on Graduate Studies.

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Abstract

Single electron transistors (SETs) have been proposed as a successor to silicon CMOS

devices, with the potential to maintain the pace of Moore’s Law into the future. Based

on the principles of Coulomb blockade, SETs in thin, metal films generally consist of a

small, conductive island separated from source and drain leads by tunnel junctions. Room

temperature operation of SETs requires device dimensions on the nanometer scale, generally

achievable only with great difficulty and cost.

We investigated the development of a novel, relatively simple fabrication process for

SETs. Two methods were studied for the creation of lateral oxide barriers for SET tunnel

junctions: atomic force microscope (AFM) oxidation, a versatile direct-write patterning

technique, and current-induced local oxidation (CILO), which produced a self-limiting oxide

barrier aligned to a pre-patterned feature. AFM oxidation was used to produce arbitrary

patterns and lateral oxide barriers in thin films of gallium arsenide, nickel aluminum, and

titanium (Ti). CILO was used to form lateral oxide barriers in Ti, and the underlying

mechanism was examined.

Characterization of the two methods, and the oxide barriers they produced, demon-

strated that both techniques suffered from limitations. In particular, AFM oxidation was

not sufficiently reproducible, and CILO barriers were not thin enough to allow tunneling.

The CILO process was then combined with self-assembled gold islands, relaxing the oxide

barrier fabrication requirements. The result was a device consisting of a disordered two-

dimensional array of islands with diameters less than 15 nm, isolated between two leads

separated by less than 100 nm.

The electrical characteristics of fabricated devices were measured at low temperatures

with drain and gate voltage sweeps, and demonstrated features consistent with Coulomb

blockade. However, these features were apparent only at low temperatures, indicating that

the islands were too large to allow for room temperature operation. In addition, the low

iv

conductance region at low drain-source bias was observed in devices both with and without

gold islands. The thin Ti film, shown to be electrically discontinuous, may have been

only partially oxidized by CILO. Nanocrystalline grains of Ti, separated by oxidized grain

boundaries, were possibly the source of the observed features.

The combination of CILO with self-assembly addressed one of the limitations of the self-

assembly method. The ultimate feasibility of this approach to SET fabrication, however,

may rely on the development of a defect-tolerant circuit architecture that accounts for

nonuniformity.

v

Acknowledgements

It is not possible for me to fully express my gratitude to my advisor, James Harris, for his

seemingly infinite supply of patience and support. This thesis was a long effort, but he

never gave up on me, despite the many times when I felt like giving up on myself.

Gail Chun-Creech unfailingly kept the research group running smoothly and insulated

us from the many challenges of the University bureaucracy.

Ted Kamins met with a small group of us every few weeks to offer his advice. Although

not directly involved in my area of research, his insights were always valuable. Professors

Yoshitaka Okada and Rick Kiehl also helped guide me during the time they were at Stanford.

Dan Grupp, Glenn Solomon, and Thorsten Hesjedal provided guidance and asked the

tough questions. It was often the case that I failed to see the wisdom of their advice until

I had stubbornly made the mistake from which they had been trying to steer me away.

Bartev Vartanian initiated this project after spending a summer in Japan working on

AFM oxidation with Kazuhiko Matsumoto. Upon his return, we worked together with

Serguei Komarov to set up our local effort, with initial assistance from Scott Manalis of

Prof. Calvin Quate’s group.

Many (countless?) generations of Harris Group students have provided emotional and

technical support when I needed it. It was a pleasure and an honor to be able to work

alongside so many brilliant and dedicated people.

Professor Joseph Goodman kindly served as the chair for my oral defense. He was my

advisor when I first declared as an undergraduate electrical engineering major many eons

ago. Professors Fabian Pease and Krishna Saraswat generously agreed to serve on my orals

committee and my thesis reading committee. In addition, the courses they taught helped

fuel my interest in electrical engineering.

Professor David Goldhaber-Gordon allowed me to make measurements on his group’s

probe station. Nick Koshnick guided me through the process, and Prof. Goldhaber-Gordon’s

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post-docs and senior students were consistently generous with their time and expertise.

Professor Byung Gook Park and his student Kyung Rok Kim, of the Inter-University

Semiconductor Research Center of Seoul National University, performed electron beam

lithography for this project when the system at Stanford proved incapable of delivering the

resolution and repeatability I required.

The technical staff of the Stanford Nanofabrication Facility and the Laboratory for

Advanced Materials did a fine job of maintaining the equipment on which my work relied

for fabrication and analysis, and providing training and assistance in their use.

Many thanks to my friends and family who helped keep me sane and taught me so many

things that cannot be learned through lectures and labs. The numerous friends I have made

in Stanford Taiko and the Palo Alto Kendo Dojo have given me so much and enriched my

life.

My parents’ love and support these many years has been invaluable. They have given

me the freedom to pursue my dreams, and I do not think that any child could ask for more.

vii

Contents

Abstract iv

Acknowledgements vi

1 Introduction 1

1.1 Motivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

1.2 Single Electron Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

1.3 History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

1.4 Fabrication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

1.4.1 Lithographic Methods . . . . . . . . . . . . . . . . . . . . . . . . . . 5

1.4.2 Self-Assembly Methods . . . . . . . . . . . . . . . . . . . . . . . . . 6

1.5 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

2 Single Electron Tunneling 9

2.1 Single Tunnel Junction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

2.2 Double Tunnel Junctions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

2.3 Arrays . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

2.3.1 1D Arrays . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

2.3.2 2D Arrays . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

2.3.3 Simulations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

3 Atomic Force Microscope Oxidation 33

3.1 History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

3.2 Oxidation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

3.3 Oxidation of GaAs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

3.3.1 Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

viii

3.3.2 Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

3.3.3 Discussion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

3.4 Oxidation of NiAl . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

3.5 Oxidation of Ti . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

3.5.1 Ti Oxide Barrier Height Characterization . . . . . . . . . . . . . . . 47

3.5.2 Ti Film Characterization . . . . . . . . . . . . . . . . . . . . . . . . 52

3.5.3 Ti SET Fabrication and Measurement . . . . . . . . . . . . . . . . . 54

4 Current Induced Local Oxidation 59

4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

4.2 Background . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

4.3 Barrier Height Determination . . . . . . . . . . . . . . . . . . . . . . . . . . 64

4.3.1 Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

4.3.2 Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

4.3.3 Discussion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

4.4 Minimum Current Density for CILO . . . . . . . . . . . . . . . . . . . . . . 66

4.4.1 Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

4.4.2 Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

4.4.3 Discussion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

4.5 Heating and XPS Characterization of Ti Films . . . . . . . . . . . . . . . . 69

4.5.1 Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

4.5.2 Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

4.5.3 Discussion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

4.6 Improved Device Resistance Model . . . . . . . . . . . . . . . . . . . . . . . 80

4.6.1 Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

4.6.2 Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

4.6.3 Discussion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

5 SET Fabrication and Measurement 87

5.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

5.2 Fabrication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88

5.2.1 Electron Beam Lithography . . . . . . . . . . . . . . . . . . . . . . . 88

5.2.2 Au Island Deposition . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

5.2.3 Ti Film Deposition . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92

ix

5.2.4 Liftoff and Cleaning . . . . . . . . . . . . . . . . . . . . . . . . . . . 92

5.2.5 Contact Pads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93

5.2.6 CILO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93

5.3 Low Temperature Probe Station Measurement . . . . . . . . . . . . . . . . 93

5.3.1 Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93

5.3.2 Results and Discussion . . . . . . . . . . . . . . . . . . . . . . . . . . 95

5.4 Liquid Helium Dewar Measurement . . . . . . . . . . . . . . . . . . . . . . . 104

5.4.1 Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104

5.4.2 Results and Discussion . . . . . . . . . . . . . . . . . . . . . . . . . . 105

6 Conclusions 116

6.1 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116

6.2 Future Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117

A Low Temperature Gate Current 120

A.1 Characterization and Simple Modeling . . . . . . . . . . . . . . . . . . . . . 120

A.2 Physical Explanation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123

A.3 Simulations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124

References 126

x

List of Tables

4.1 ARXPS data from 6 nm Ti film prior to baking. . . . . . . . . . . . . . . . 75

4.2 Ti and Ti oxide volumes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

xi

List of Figures

1.1 Schematic diagram of single electron transistor structure . . . . . . . . . . . 3

2.1 Schematic diagram of a current-biased single tunnel junction . . . . . . . . 10

2.2 Schematic diagram of a voltage-biased double junction . . . . . . . . . . . . 11

2.3 Voltage diagram of a single island . . . . . . . . . . . . . . . . . . . . . . . . 12

2.4 Adding and removing an electron from a single island . . . . . . . . . . . . 13

2.5 Single island Coulomb blockade region . . . . . . . . . . . . . . . . . . . . . 15

2.6 Drain voltage sweep of a single island, simple calculation . . . . . . . . . . . 16

2.7 Drain voltage sweep of a single island, MOSES simulation . . . . . . . . . . 16

2.8 Gate voltage sweep of a single island, MOSES simulation . . . . . . . . . . 17

2.9 Schematic diagram of the 4× 5 array used in MOSES simulations . . . . . 23

2.10 MOSES simulations of current through a 4× 5 disordered array . . . . . . . 24

2.11 MOSES simulations showing influence of background charge on current . . 26

2.12 Application of the Kurdak method to determine VT from simulation results 27

2.13 Fitting array current to the Middleton-Wingreen model . . . . . . . . . . . 29

2.14 Extraction of array parameters using Coulomb blockade thermometry . . . 30

2.15 MOSES simulations of ID v. VD for a 4× 5 disordered array . . . . . . . . . 30

2.16 MOSES simulation of ID v. VG for a 4× 5 array at T = 4 K . . . . . . . . . 32

3.1 Schematic diagram of AFM oxidation process . . . . . . . . . . . . . . . . . 36

3.2 AFM image of oxide lines on GaAs, drawn by AFM oxidation . . . . . . . . 38

3.3 Oxide line dimensions for different AFM tip bias voltages and translation

speeds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

3.4 Oxide line dimensions for different AFM tip bias voltages and translation

speeds with increased humidity increased . . . . . . . . . . . . . . . . . . . 40

xii

3.5 Oxide line heights for different AFM tip bias voltages and translation speeds

compared to Stievenard model . . . . . . . . . . . . . . . . . . . . . . . . . 43

3.6 SEM images of contact mode AFM tips used for lithography . . . . . . . . 44

3.7 AFM image of AFM-oxidized barrier across NiAl wire . . . . . . . . . . . . 47

3.8 AFM image of Ti MIM junction fabricated by AFM oxidation . . . . . . . . 48

3.9 I-V measurements through an AFM-oxidized MIM junction . . . . . . . . . 49

3.10 Barrier height determination of AFM-oxidized MIM junction . . . . . . . . 50

3.11 I-V measurements through Ti channel defined by AFM oxidation . . . . . . 51

3.12 Ti film resistivity increased as deposited film thickness decreased . . . . . . 53

3.13 Nossek plot indicated that Ti film was discontinuous for thicknesses below

11.5 nm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

3.14 Plan view TEM image showing polycrystalline Ti film grains with diameters

less than 10 nm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

3.15 AFM image of three terminal structure . . . . . . . . . . . . . . . . . . . . . 56

3.16 AFM image of central channel of Ti SET . . . . . . . . . . . . . . . . . . . 57

3.17 Room temperature I-V measurement of single electron device structure . . 58

4.1 Avouris et al. used AFM oxidation to define a 100–200 nm wide channel in

a Ti wire . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

4.2 Electromigration as a driver of the CILO process . . . . . . . . . . . . . . . 61

4.3 The total resistance consisted of the constant lead resistance and the variable

channel resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

4.4 Current through the channel during the CILO process . . . . . . . . . . . . 63

4.5 Current through a device before and after the CILO process . . . . . . . . . 63

4.6 AFM image of CILO barrier formed in a channel defined by AFM oxidation 65

4.7 Barrier height determination of MIM junction fabricated by CILO . . . . . 65

4.8 Minimum current to initiate CILO in channels defined by e-beam lithography 67

4.9 AFM image of CILO barrier and halo formed slightly downwind of a channel

defined by AFM oxidation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

4.10 AFM image of CILO damage located downwind of a channel defined by

electron beam lithography . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

4.11 CILO current and channel conductance during multiple, partial oxidations . 70

xiii

4.12 Effects of hotplate bake temperature and time on the thickness of a Ti film

measured by AFM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

4.13 Estimate of activation energy of Ti oxidation . . . . . . . . . . . . . . . . . 73

4.14 Effects of hotplate bake temperature and time on the normalized conductance

of a Ti wire . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

4.15 Effects of hotplate bake time on the normalized conductance of two 4 nm

thick Ti films . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

4.16 Expected layer structure for a nominally 6 nm thick film deposited on SiO2 75

4.17 Graphical analysis of ARXPS data . . . . . . . . . . . . . . . . . . . . . . . 76

4.18 High resolution XPS scans of Ti 2p peaks . . . . . . . . . . . . . . . . . . . 77

4.19 XPS depth profiles of Ti film after hotplate bake . . . . . . . . . . . . . . . 79

4.20 Simulation of the XPS depth profile data . . . . . . . . . . . . . . . . . . . 80

4.21 AFM measurement of partial CILO oxide barrier . . . . . . . . . . . . . . . 82

4.22 Initial oxide barrier height measurement correlation . . . . . . . . . . . . . 83

4.23 Fuchs-Sondheimer thin film resistivity . . . . . . . . . . . . . . . . . . . . . 85

4.24 Improved oxide barrier height measurement correlation . . . . . . . . . . . . 86

5.1 Use of Au islands to ease SET fabrication requirements . . . . . . . . . . . 88

5.2 Overview of the SET fabrication process . . . . . . . . . . . . . . . . . . . . 89

5.3 AFM image of Au islands . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91

5.4 Histogram of Au island diameters . . . . . . . . . . . . . . . . . . . . . . . . 91

5.5 AFM image of completed device . . . . . . . . . . . . . . . . . . . . . . . . 94

5.6 Schematic of measurement apparatus . . . . . . . . . . . . . . . . . . . . . . 95

5.7 Differential conductance through a high-resistance device with Au islands for

T=1–70 K . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96

5.8 Differential conductance through a low-resistance device with Au islands for

T=1–70 K . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96

5.9 Differential conductance through a high-resistance device without Au islands

for T=10–30 K . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97

5.10 Differential conductance through a low-resistance device without Au islands

for T=1–70 K . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97

5.11 Coulomb blockade thermometry analysis of a low-resistance device without

Au islands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98

xiv

5.12 Current through a high-resistance device with Au islands . . . . . . . . . . 99

5.13 Measured current not explained by Schottky emission . . . . . . . . . . . . 100

5.14 Measured current not explained by Frenkel-Poole emission . . . . . . . . . . 101

5.15 Measured current not explained by space-charge-limited current . . . . . . . 101

5.16 Measured current not explained by low voltage tunneling . . . . . . . . . . 102

5.17 Fit of higher voltage current to Fowler-Nordheim tunneling current behavior 103

5.18 Current through a high-resistance device with Au islands . . . . . . . . . . 106

5.19 Current through a low-resistance device with Au islands . . . . . . . . . . . 106

5.20 Current through a high-resistance device without Au islands . . . . . . . . . 107

5.21 Current through a low-resistance device without Au islands . . . . . . . . . 107

5.22 Middleton-Wingreen plot of the current through a high-resistance device with

Au islands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108

5.23 Middleton-Wingreen plot of the current through a low-resistance device with

Au islands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109

5.24 Middleton-Wingreen plot of the current through a high-resistance device

without Au islands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109

5.25 Middleton-Wingreen plot of the current through a low-resistance device with-

out Au islands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110

5.26 Drain and gate currents for VDS = 0 V . . . . . . . . . . . . . . . . . . . . . 111

5.27 Drain current for VDS = 44 V . . . . . . . . . . . . . . . . . . . . . . . . . . 111

5.28 Drain currents v. gate-source voltage sweep from 0 to 20 V . . . . . . . . . 112

5.29 Drain currents v. gate-source voltage sweep from 0 to 20 V, smoothed and

with offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113

5.30 Drain currents v. gate-source voltage sweep from 20 to 0 V . . . . . . . . . 114

5.31 Drain currents v. gate-source voltage sweep from 0 to 20 V, with negative

drain bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114

5.32 Drain currents v. gate-source voltage sweep from 0 to 20 V, with smaller gate

voltage increment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115

A.1 Characterization of measurement apparatus capacitance . . . . . . . . . . . 121

A.2 Simple simulation of gate current for gate voltage sweep . . . . . . . . . . . 122

A.3 Calculated hole dwell time on acceptor at T = 4.2 K . . . . . . . . . . . . . 124

xv

Chapter 1

Introduction

In 1965, Gordon Moore observed that the number of transistors per chip was doubling every

one and a half years, a rate that was soon dubbed “Moore’s Law” [1]. Since that time,

the semiconductor industry has been able to sustain this remarkable rate of improvement,

primarily made possible by the ability to shrink the size of the workhorse device of modern

electronics, the silicon (Si) complementary metal-oxide-semiconductor (CMOS) transistor.

In his famous lecture on the possibilities of miniaturization, physicist Richard Feynman

noted, “There’s plenty of room at the bottom” [2], but there are limits to how much further

the size of the transistor can be scaled down.

1.1 Motivation

There are three primary challenges to the continued scaling of transistors. The first set

of challenges involves the physical assumptions underlying the operation of these devices,

and the way that some of these assumptions break down as physical dimensions shrink.

Oxides, for example, are used in several parts of integrated circuits to provide insulation

between conducting regions. As oxide thicknesses approach the order of a few nanometers,

however, electrons can increasingly tunnel through these barriers, leading to unacceptable

levels of leakage current. Another problem arises when device volumes become small enough

that statistical variations in the dopant distribution result in substantial differences in

characteristics from one device to the next. Third, the device dimensions are approaching

the depletion region width, causing problems for device isolation, and forming parasitic,

unintended devices. These issues limit the ultimate performance of not only Si CMOS, but

1

CHAPTER 1. INTRODUCTION 2

also such proposed devices as carbon nanotube transistors whose operation often relies on

similar principles [3].

The second set of challenges arises from growing power consumption and the related

dissipation of generated heat. As transistors become smaller, they operate at higher speeds

and can be fabricated at higher densities, leading to increased generation of heat. Limits to

the ability to dissipate the generated heat may ultimately put an upper bound on the tran-

sistor operating speed and device density, requiring that future performance improvements

come from other areas, such as device functionality [4].

Finally, it is becoming increasingly difficult to fabricate transistors with the minuscule

dimensions required. Device structures are becoming increasingly complicated and require

the incorporation of growing numbers of new materials. The nanometer-scale features of

future scaled transistors will require extremely high-resolution patterning, strict alignment,

and tight process controls beyond current capabilities. Even in cases where the technology

is feasible, the practical manufacturing costs may be prohibitive [5].

Si CMOS transistors have overcome many obstacles in their past, but it is unlikely

that solutions can be found to all three challenges described above. A new approach to

computation may be required, and single electron devices are a strong candidate to form the

basis of this new technology [6, 7]. These devices rely on different physical assumptions than

Si CMOS, and are not as adversely affected by tunneling currents, nor do they necessarily

rely on uniform doping statistics. They also have the potential to achieve lower power

operation than Si CMOS. They have not, however, been particularly easy to fabricate.

Having overcome two of the challenges to future electronics, a key to the success of single

electron devices lies in developing a capable, yet economic, fabrication method.

The research in this thesis focused on the use of two different oxidation processes for

the fabrication of lateral oxide barrier tunneling junctions, which are critical elements in

single electron devices. Atomic force microscope oxidation is a versatile direct-write pat-

terning technique that locally oxidizes the surface beneath a scanning probe microscope

tip. Current-induced local oxidation (CILO) oxidizes the material in a constriction in a

wire by taking advantage of the high current density there. The two processes proved to

have limits, however, and we devised a way to use CILO to isolate small, gold islands. The

result was a novel fabrication process taking advantage of self-assembly, self-alignment, and

self-limitation to produce single electron device structures without the need for the highest

resolution lithography, precise alignment, or tight process control.


1.2 Single Electron Devices

While the operation of a typical modern transistor may involve many millions of electrons,

a digital switch composed of single electron devices can be turned on or off by a single

electron. The addition (or subtraction) of an electron to a conductive island from a nearby

lead requires a classical charging energy Ec based on the island’s capacitance C:

Ec = e2/2C (1.1)

where e is the electronic charge. If the potential difference between the lead and the island is

less than this charging energy, current cannot flow. The current passing through the island

between adjacent source and drain electrodes can then be governed by a gate electrode

controlling the potential of the island. This forms the basis of what is known as the single

electron transistor (SET). A diagram of this structure is shown in Fig. 1.1.

Figure 1.1: In a single electron transistor, current flows between source and drain electrodes onlywhen a charging energy condition is met. A gate electrode can modulate the current by controllingthe island potential.

There are two primary requirements that a single electron device must meet in order

to function [8]. First, the island must be sufficiently disconnected from the leads so that

the electron is localized on the island. This is satisfied if the tunneling resistance RT of the

lead-island junctions is much larger than the quantum resistance:

RT RQ = h/e2 ≈ 25.8 kΩ. (1.2)


Second, the island charging energy must be much larger than the thermal energy:

e2/2C kBT. (1.3)

In order to operate at room temperature, the island capacitance must be on the order

of 1 aF, requiring device dimensions at the nanometer scale. Reliable fabrication of de-

vices with these small dimensions is one of the main challenges facing single electron de-

vices.

1.3 History

The first observations of single electron effects arose from investigations of extremely thin

metal films that were discontinuous and composed of separate grains. In 1951, Gorter

proposed an explanation for the high resistances that had been observed in these films at

low fields and temperatures [9]. His model included a field- and temperature-dependent

resistance resulting from the separation of positive and negative charges. In 1962, Neuge-

bauer and Webb observed similar effects in a discontinuous gold (Au) film, and derived

a conductivity based on the creation of charge and field-dependent tunneling between is-

lands [10]. Several years later, Giaever and Zeller investigated charge transport through a

layer of tin particles embedded in oxide, and used a capacitor-charging model to account

for the high resistance behavior at low bias [11]. Lambe and Jaklevic, in 1969, followed a

similar approach in describing the discrete transfer of charge onto a layer of indium droplets

in oxide [12].

Interest was revived several decades later when electron beam lithography enabled the

fabrication of artificial structures small enough to demonstrate single electron effects at

cryogenic temperatures. The first experimental demonstration of an SET was by Fulton

and Dolan, who developed a multiple-angle shadow evaporation process which used thin,

overlapping aluminum films to form small tunnel junctions [13]. Through control of the two

evaporation angles, they were able to fabricate junctions with dimensions below the litho-

graphic limits. Applying a voltage to the substrate, they were able to modulate the current

through their devices in a manner consistent with the theory being developed concurrently

by Averin and Likharev [8].


1.4 Fabrication

Methods for the fabrication of single electron tunneling devices can be roughly divided into

two categories. One approach uses advanced lithography and etching, lift-off, or oxidation

techniques to pattern the necessary small features, offering good control over critical dimen-

sions and uniformity, but often hampered by the limitations of the lithography in achieving

the smallest features. The other method relies on self-assembly: taking advantage of natural

processes in which small structures are energetically favorable. Self-assembly, however, suf-

fers from poor control over structure sizes and uniformity, as well as the placement of those

structures. Many fabrication schemes feature aspects of both approaches to take advantage

of their individual strengths.

1.4.1 Lithographic Methods

Electron beam lithography has been used in combination with various other techniques to

push feature sizes below what is possible with lithography alone. The shadow evaporation

technique was expanded by Kuzmin et al. to fabricate more complicated metal structures,

such as one-dimensional arrays of devices [14]. Another approach was developed by Alt-

meyer et al., who used the discontinuity of a titanium (Ti) wire deposited across a step as

a tunnel junction [15]. Continuous Ti wires deposited across shallow trenches have been

employed by Hofmann et al., with islands being defined by the tunnel junctions formed at

the bends in the wire [16].

The first observation of single electron effects in a semiconductor was by Scott-Thomas

et al., who used the inversion layer in a Si metal-oxide-semiconductor structure for verti-

cal confinement, and depletion regions under metal gates to confine the electrons in one

lateral dimension [17]. The islands were believed to be defined in the third dimension by

random interface charges. A similar structure was formed in a two-dimensional electron

gas (2DEG) formed at a gallium arsenide/aluminum gallium arsenide (GaAs/AlGaAs) het-

erojunction by Meirav et al., with islands defined by additional metal gate structures that

formed tunable tunneling barriers [18]. Takahashi et al. used a silicon-on-insulator (SOI)

structure for vertical confinement, and pattern-dependent oxidation to form tunnel junc-

tions at each end of a Si wire [19]. Leobandung et al. also used SOI, but relied on electron

beam lithography alone to define the island [20]. While the previous devices involved hor-

izontal electron flow, Austing et al. formed the first vertical device in a GaAs/AlGaAs


double barrier structure, where the gate was used to influence the lateral size of the is-

land [21].

Other patterning methods such as focused ion beam [22] and nano-imprint lithogra-

phy [23] have also been employed for the fabrication of single electron devices. Direct

patterning with scanning probe microscopes has also been used, and is the subject of Chap-

ter 3 of this thesis.

1.4.2 Self-Assembly Methods

Another fabrication method used in this thesis is a technique which relies on the deposition

of small amounts of material, for which it is energetically favorable to form clusters instead

of evenly spreading out. This is the phenomenon behind the earliest observations of single

electron effects mentioned before, and discontinuous thin films of aluminum (Al) [24], gold

palladium (AuPd) [25], and Au have continued to be used for single electron devices. A

continuous film composed of discrete grains is also suitable, and grains in polycrystalline Si

were utilized by Yano et al. in their demonstration of a single electron memory device [26].

Au and cadmium selenide (CdSe) colloidal clusters synthesized with wet chemistry were

employed by Klein et al. [27]. Sato and Ahmed investigated methods to deposit isolated

Au colloidal particles and one-dimensional chains of particles [28]. A technique to deposit

ordered two-dimensional arrays of Au particles was developed by Tsuitsui et al., who also

demonstrated the arrays’ mechanical stability [29]. Semiconductor particles have also been

employed, and Dutta et al. used a very-high-frequency plasma cell to produce Si nanocrys-

tals [30].

One of the challenges in working with islands of this type is the method used to provide

electrical contact to the islands. Ralph et al. measured current in the vertical direction

through a layer of islands [24]. The top contact was formed by a simple metal overlayer, but

the back contacts were made by etching a pit through the backside of the thin membrane on

which the islands were deposited. Klein et al. used electron beam lithography and multiple-

angle shadow evaporation to create electrodes separated by ∼50 nm [27]. Davidovic and

Tinkham probed islands located at the edges of a junction between two electrodes separated

by a surface oxide [31]. Electromigration was used to create a controlled break in a Au wire,

and CdSe nanocrystals were placed in the resulting 1 nm gap by Park et al. [32]. Morpurgo

et al. used electrical monitoring during electrodeposition to control the separation between

two closely separated electrodes [33]. The work in this thesis relied on the method of


Avouris et al., who developed a process to form a self-limiting local oxide across a conductive

wire [34].

1.5 Applications

A key goal of single electronics research has been the application of single electron devices to

digital logic. One approach has been to use the SET as a direct replacement for the Si metal-

oxide-semiconductor field-effect transistor (MOSFET), with logic values represented by line

voltages. Tucker [35] and Chen et al. [36] described a circuit similar to a CMOS inverter

using two SETs, with individual back-gates to put one SET in the Coulomb blockade regime,

blocking current, and to have the other SET passing current. This inverter was successfully

demonstrated in an aluminum/aluminum oxide (Al/AlOx) system by Heij et al. [37] and in

Si by Ono et al. [38].

The application of these devices to more complicated circuits may be limited, how-

ever. For the examples cited above, back-gates to individual islands were necessary to tune

each SET to cancel out the effect of random background charge. In addition, the gain of

the circuits, although greater than unity, was fairly low. In this configuration, the gain

is ∼Cgate/Cjunction, the ratio of two of the device capacitances. Since Cjunction may be

limited by the fabrication method, the only way to increase the gain is by increasing Cgate.

Unfortunately, this also has the effect of decreasing the maximum operating temperature.

Other schemes for digital logic with different architectures have also been investigated to

take advantage of the properties of SETs. Averin and Likharev have proposed single electron

logic (also called charge state logic), in which digital states are represented by the presence or

absence of a single electron on an island [39]. The potential for error is quite high, however,

as processes such as co-tunneling or thermally-activated tunneling could readily change the

number of electrons on an island even under Coulomb blockade conditions [40]. Nakajima

et al. pursued a logic system based on a binary decision diagram architecture, in which

an electron travels through a tree structure, with input values determining the particular

path and destination. They successfully fabricated an AND/NAND gate in GaAs grown

by selective-area metalorganic vapor-phase epitaxy [41]. Kiehl and Ohshima simulated the

storage of information in the phase of an AC voltage across a single electron tunneling

junction relative to a pump [42]. Another possibility is the quantum-dot cellular automata

system demonstrated by Snider et al., in which a binary state is represented by the positions


of two electrons in a cell made up of a 2 × 2 array of islands [43]. Logical functions are

created by different arrangements of cells, which directly pass their state on to adjacent

cells, eliminating the need for interconnects.

Perhaps the best potential for near-term future use of single electron devices is in mem-

ory. The ability to deal with small numbers of electrons is useful for both charge storage

and sensing. In addition, the small size of single electron devices should lead to high device

density. The general approach has been to store charge on a small island, and sense the

state of the stored charge with either an SET or an FET [44]. As noted previously, Yano

et al. used grains in polycrystalline Si for the storage island and the SET [26]. Guo et

al. embedded a lithographically-defined Si island inside an FET structure, with the island

serving as a floating gate for the channel beneath it [45]. An FET was used to control

multiple levels of charge on an island, and an SET was used to read the charge in work

performed by Nishiguchi et al. [46].

Research into single electron device fabrication and applications continues, especially

in Si [47]. Significant challenges remain however, to the reliable fabrication and operation

of single electron devices and circuits, and a key figure in the development of this field,

Likharev, has focused his attention on hybrid systems with CMOS in an architecture that

is tolerant to defects [48, 49].

Chapter 2

Single Electron Tunneling

The full theory of single electron tunneling requires a quantum mechanical approach. A

simpler classical approach, however, can impart an intuitive understanding of the concepts,

and this chapter describes a passive circuit approach for the derivation of the threshold

voltage for a single island SET. The theory behind the threshold voltage and transport for

one- and two-dimensional array structures is described, as well as simulation results showing

some of the effects of introducing disorder.

2.1 Single Tunnel Junction

The simplest Coulomb blockade system is the current-biased single tunnel junction, as

shown in Fig. 2.1. Like a classical capacitor, a tunnel junction has a charging energy given

by

Ec =Q2

2C(2.1)

where Q is the charge, and C is the capacitance of the junction. Current is composed

of discrete electrons, and only whole electrons tunnel across the junction. Current itself,

meanwhile, is continuous. In this simple circuit, the current will charge the junction, but

no electrons will tunnel across until the charging energy for a single electron, e2/2C, is

exceeded. The corresponding necessary junction voltage is V = e/2C.

A free energy argument can be made by looking at the change in junction energy when

an electron tunnels across. Consider first an electron tunneling forward across the junction,

from the grounded side (source) to the other side (drain). The free energy change is the

9

CHAPTER 2. SINGLE ELECTRON TUNNELING 10

I C

Figure 2.1: Schematic diagram of a current-biased single tunnel junction.

difference in the energy stored in the junction between the initial state with charge Q and

the final state with charge Q− e:

∆F+ =(Q− e)2

2C− Q2

2C

=e2

2C− eV (2.2)

where we have used the relation V = Q/C. Tunneling requires a negative change in free

energy. Applying the condition of ∆F < 0 to (2.2), we obtain the corresponding voltage

requirement:

V >e

2C. (2.3)

For tunneling in the reverse direction, we look at the difference in the junction energy

between the initial state with charge Q and the final state with charge Q+ e:

∆F+ =(Q+ e)2

2C− Q2

2C

=e2

2C+ eV. (2.4)

The requirement of a negative free energy change for tunneling results in:

V < − e

2C. (2.5)

Equations (2.3) and (2.5) indicate that in order to tunnel across the junction, the junc-

tion voltage must exceed a charging voltage determined by the junction capacitance. This

situation has been very difficult to observe experimentally because the junction capacitance

must be very small, and is usually dominated by parasitic capacitances.


2.2 Double Tunnel Junctions

We next consider the case of two tunnel junctions in series. The two junctions define

an island in between them containing an integral number of electrons. In the general

representation of Fig. 2.2, in addition to the two junction capacitances, we include a gate

capacitance to a third electrode, and a self capacitance to ground.

VG

VD

C1, G1

C2, G2

Cg

Cs

Figure 2.2: Schematic diagram of a voltage-biased double junction, or single island. In addition tothe two tunnel junctions, gate and self capacitances are included.

Conceptually, the movement of charge through two junctions is similar to the single

junction case. Again, we require minimum charging voltages across a junction to add or

remove an electron from the central island. For positive biases less than this threshold (or

negative biases greater than the corresponding threshold), no current flows.

The potential diagram in Fig. 2.3 is one way to represent the system. The potentials of

the drain and source leads are the solid black lines at the left and right, respectively. The

potential of the central island corresponding to the presence of N electrons on the island

is shown by the solid black line in the middle. The gray lines represent the potential of

the island for the cases of N + 1 and N − 1 electrons on the island. The junction voltages

required for adding or removing an electron are shown by the dashed lines.

In Fig. 2.4a, a bias has been applied between the drain and the source. In this case, the

capacitance of the first junction C1, is smaller than the capacitance of the second junction

C2, and more of the applied bias falls across the first junction than the second. The source-

island junction does not have sufficient voltage to allow tunneling onto the island, but the

drain-island junction does have sufficient voltage to allow an electron to tunnel from the

island onto the drain. The potential of the island then drops down to the N − 1 level. The


Figure 2.3: Voltage diagram of a single island. The gray lines represent the potential of the islandfor N + 1 and N −1 electrons on the island. The dashed lines reflect the junction voltages necessaryfor adding or subtracting an electron.

new island potential is low enough that an electron can tunnel onto the island from the

source. This returns the island to the N potential level, the situation repeats itself, and

source-drain current flows.

If we make C1 larger than C2, we see the situation in Fig. 2.4b when we apply a source-

drain bias. More voltage is dropped across the second junction, and we are able to add an

electron to the island from the source. The potential of the island jumps up to the N + 1

level, from which an electron can tunnel out onto the drain. The island returns to the N

level and the process repeats.

For the double junction, the relevant capacitance to determine the charging voltage is

the total capacitance seen by the island. Referring back to Fig. 2.2, the island sees four

capacitances in parallel. The total capacitance is

CΣ = C1 + C2 + Cg + Cs (2.6)

where C1 and C2 are the junction capacitances, and Cg and Cs are the gate and self

capacitances, respectively. The charging voltage is then given by

Vc =e

2CΣ. (2.7)

The threshold voltage for conduction is determined by whichever of the two junctions

first exceeds the charging voltage. The approach is to first determine the voltage across


(a) C1 < C2: an electron can beremoved from the island onto thedrain, and the island alternatesbetween the N and N − 1 levels.

(b) C1 > C2: An electron canbe added to the island from thesource, and the island alternatesbetween the N and N + 1 levels.

Figure 2.4: Depending on the junction capacitances, an electron can be added to, or removed from,the island as the source-drain voltage is increased beyond a threshold voltage.

each junction, and then compare those voltages with the island charging voltage. VD and

VG refer to the drain and gate voltages, and Vg and Vs refer to the voltages across the gate

and self capacitances. Qb is the background charge on the island.

V1 = VD − V2 (2.8)

Vg = VG − V2 (2.9)

Vs = V2 (2.10)

Qs +Q2 +Qb = Q1 +Qg (2.11)

Express the charge on each junction in terms of its capacitance and voltage:

CsVs + C2V2 +Qb = C1V1 + CgVg (2.12)

and solve for the voltage across one of the junctions:

V2 =C1VD + CgVG −QbC1 + C2 + Cg + Cs

. (2.13)


The other junction voltage can then also be solved for:

V1 =(C2 + Cg + Cs)VD − CgVG +Qb

C1 + C2 + Cg + Cs. (2.14)

The junction voltage requirement for tunneling across the first junction is then:

V1 >e

21CΣ

(2.15)

which leads to the drain voltage condition:

VD >e2 + CgVG −QbC2 + Cg + Cs

. (2.16)

For tunneling across junction two,

V2 >e

21CΣ

(2.17)

which leads to the alternative drain voltage condition:

VD >e2 − CgVG +Qb

C1. (2.18)

The threshold voltage for positive VD is thus

VT = min

[e2 + CgVG −QbC2 + Cg + Cs

,e2 − CgVG +Qb

C1

]. (2.19)

Similarly, for negative VD,

VT = max

[− e

2 + CgVG −QbC2 + Cg + Cs

,− e

2 − CgVG +QbC1

]. (2.20)

Assuming a simple case of no background charge and a negligible self-capacitance, plot-

ting the threshold voltage versus VD and VG produces a diamond-like shape, as seen in

Fig. 2.5. Inside the diamond is the Coulomb blockade region, where no current flows. In-

creasing VD past the threshold, or for a non-zero VD changing VG so that the threshold

condition is satisfied, results in a finite source-drain current. The upper right and lower

left walls of the diamond are determined by the sum of C2 and CG, and the upper left and

lower right walls are determined by C1, showing how the specific conditions will determine


whether junction 1 or 2 sets the threshold. Note, however, that changing VG simply alters

the potential of the island, and it is possible to leave the Coulomb blockade diamond cor-

responding to N electrons and enter the diamond corresponding to N + 1 electrons, where

again no current flows.

VG

VD

!

e

2 C2 + Cg( )

!

e

2C1

!

e

2Cg

VD

VG

!

e

2 C2 + Cg( )

!

e

2C1

!

e

2Cg

Figure 2.5: No current flows through the island in the Coulomb blockade region (central grey area)defined by the expressions for the threshold voltage.

A simple model of the drain current can be made by assuming that the tunneling cur-

rent through a junction may be described by a tunneling resistance. The current through

the device will be limited by the tunneling rate at one of the junctions. A plot made

in this way is shown in Fig. 2.6. For comparison, Fig. 2.7 shows the characteristics of

a device with identical parameters as simulated by MOSES 1.2, a Monte-Carlo Single-

Electronics Simulator [50]. MOSES possesses the important additional capability of mod-

eling the effects of temperature on the current. Thermal broadening leads to a rounding of

the current characteristic, until at high temperatures, the Coulomb blockade is lost entirely.

The results of the simple model, however, match the T = 0 K result from MOSES fairly

well.

Fig. 2.8, a MOSES simulation of a gate voltage sweep under the application of a small

drain bias, shows the characteristic Coulomb blockade oscillations in the drain current. The

drain current valleys occur when the device is biased in the Coulomb blockade regime, and

the peaks are when the threshold voltage condition at one of the junctions is satisfied. The


-40

-20

0

20

40

-10 -5 0 5 10

VD (mV)

I D (

pA

)

Figure 2.6: Simple calculation of a drain voltage sweep of a single island showing the low-conductanceCoulomb blockade region at low bias.

-40

-20

0

20

40

-10 -5 0 5 10

VD (mV)

I D (

pA

)

Figure 2.7: MOSES simulation of a drain voltage sweep of a single island at different temperatures:T = 0 K (black line), T = 10 K (medium grey line), and T = 20 K (light grey line).


peak spacing is determined by the gate capacitance, and the peak width corresponds to the

drain bias.

0

1

2

3

4

-200 -100 0 100 200

VG (mV)

I D (

pA

)

Figure 2.8: MOSES simulation of a gate voltage sweep of a single island showing Coulomb blockadeoscillations in the drain current. Simulated temperature T = 0 K.

2.3 Arrays

Single electron effects are also possible in one-dimensional (1D) linear series arrays and

two-dimensional (2D) planar arrays of islands. Devices formed from such arrays may be

desirable, as their high-resistance outer junctions can shield inner junctions from the en-

vironment [51]. Limitations in certain fabrication processes may also make it difficult to

produce a single, isolated island. The theory of charge transport through 1D and 2D ar-

rays is described below, followed by simulations of the current through a 2D disordered

array.

2.3.1 1D Arrays

Charge transport through uniform, 1D arrays of junctions has been described theoret-

ically as the movement of single electron solitons and anti-solitons [52]. A soliton is


the potential profile created around an island with an added charge due to the polar-

ization of charge in neighboring islands. The potential decays with a length λ, given

by

λ = cosh−1(

1 +Cs2C

)(2.21)

where Cs is the island self-capacitance and C is the junction capacitance. The soliton

travels unchanged through the array until it encounters another soliton or an array edge.

The threshold voltage to inject a soliton into an array and initiate current flow is given

by

VT =e

C(eλ − 1)(2.22)

independent of the length of the array, as long as the number of islands N > 2/λ. For

C Cs, λ ≈√Cs/C, and the use of a Taylor series expansion gives

VT =e√CCs

. (2.23)

At high voltages V VT , the current has a linear dependence on voltage:

I = GT (V − Voffset)/N (2.24)

where GT describes the total array tunneling conductance, and

Voffset = Ne

2C. (2.25)

Voffset then is directly proportional to the number of islands and the equivalent threshold

voltage of a single island.

2.3.2 2D Arrays

The soliton approach can be extended to the treatment of uniform 2D arrays, and predicts

a threshold voltage [53]

VT =e

2Cs×

(1− 2

π

)×√

CsC for Cs C

1 for Cs C(2.26)


to inject a soliton into a large array. Similarly, the offset voltage is given by [53, 54]

Voffset =e

C×

Ns4 −

14√

2for Cs C

(N − 1)C/Cs for Cs C(2.27)

where Ns is the number of islands in series, and the number of islands in parallel Np 1.

The understanding of experimentally realizable arrays, however, requires the inclusion

of nonuniformity resulting from random background charge and structural disorder. As

indicated by (2.19), background charge on an island modifies the potential of that island and

its neighbors, directly influencing the threshold voltage. As there is generally no practical

means to individually control the background charge on each island in an array, there is

likely to be a random distribution of charge between −e/2 and +e/2. Long-range structural

disorder, in the form of voids in the array, and short-range disorder, in the form of different

values of junction capacitances and conductances, also need to be considered in describing

the behavior of realistic arrays.

Middleton and Wingreen found similarities between charge transport behavior through

2D normal metal island arrays with random background charge and collective transport

through other systems with quenched disorder [55]. They identified three regimes of drain

current-drain voltage behavior, separated by a threshold voltage VT and another voltage

Vlinear [56]:V < VT sub-threshold regime,

VT < V < Vlinear scaling regime,

V > Vlinear linear regime.

In the sub-threshold regime, the voltage applied across the array is insufficient to over-

come the Coulomb blockade, and when T = 0 K, no current flows. For non-zero tem-

peratures, the sub-threshold current can be described by a conductance that follows an

Arrhenius law [57]

G ∝ exp(−Ea/kBT ), (2.28)

where the activation energy Ea decreases linearly with applied voltage [56]. In the absence

of charge disorder and for V → 0 V, Ea would correspond to the charging energy Ec of an

individual island.

As the applied voltage surpasses the threshold voltage, the array enters the scaling


regime, and current begins to flow through one or a small number of energetically favor-

able channels. As the applied voltage increases, additional channels become available for

conduction, and the current obeys the relation

I ∼ (V/VT − 1)ζ (2.29)

where the theory predicts ζ = 1 and 5/3 for 1D and 2D arrays, respectively [55]. In

their simulations of square 2D arrays of up to 4002 islands with junction capacitance much

smaller than the self-capacitance (C Cs), Middleton and Wingreen observed ζ = 2.0±0.2,

noting that larger arrays may be required to see the theoretical value of 5/3 [55]. Simulating

different conditions of initial background charge, they found an average VT = 0.676NEc/e,

with a distribution width δVT /VT ∼ N−2/3(lnN)1/2. Kaplan et al. simulated square arrays

of islands with C Cs, and obtained ζ = 1.7 for a 20 × 20 array [57]. They found

an average VT ≈ 0.3NEc/e, and a distribution width that changed very little with array

size.

The precise configuration of current paths is determined primarily by the charge dis-

order [58], and may be dependent on history. The presence of traps adjacent to the array

could alter the potential of nearby islands and affect conduction through them. The influ-

ence of a bi-level trap coupled to a single island has been described by Grupp et al. [59].

Hysteresis in the array current has been observed experimentally by Duruoz et al., but

was attributed to slow leakage of charge from a gate electrode [60]. For this mechanism,

the hysteresis is also observable for a single dot, and does not require multiple current

paths [61].

Simulations of arrays incorporating long-range structural disorder in the form of voids

were performed by Reichhardt and Reichhardt [62]. Although they found ζ = 1.9 in the

scaling regime for a 2D array without voids, the current through arrays with voids could

not be fit by a single value. Parthasarathy et al. performed experiments on arrays with

voids, and came to a similar conclusion [58]. They believed that the voids created bottle-

necks in the arrays which acted as 1D paths, connecting local 2D regions. As the voltage

across the array was increased above threshold, the bottlenecks would limit the current,

giving a particular value of ζ. However, once all of the bottleneck channels were in use,

the current would then be governed by the 2D regions, leading to a different value of

ζ.


Cordan et al. introduced short-range structural disorder into simulations of small 3× 2

and 3×3 arrays by using a distribution of island separation distances to set junction capac-

itances and conductances [63]. They found that for higher temperatures, the distribution

of tunneling conductances G, which are exponentially dependent on the island separation

distance, played an important role in determining the optimal current paths through the

array.

The final regime of current behavior, the linear regime, is entered when the current

flows through all possible paths. In the linear regime, ζ = 1 and current through the array

can be described by a single total array conductance. In their lithographically-defined

40 × 40 square metal and semiconductor arrays, Kurdak et al. found Vlinear corresponded

to a reduced voltage v = V/VT − 1 ≈ 5 [56]. On the other hand, Parthasarathy et al. did

not observe a linear region in measurements up to v = 10 of their 90× 270 deposited gold

nanocrystal arrays [58].

An entirely different approach to characterizing transport through arrays developed

from the application of arrays to primary thermometry [64]. While the use of SETs as

logic devices requires kBT Ec, it was found that uniform 1D arrays could be used for

thermometry even when kBT Ec [65]. At such temperatures, the “orthodox” equations

of Coulomb blockade [66] can be solved analytically to express the array conductance G

around V = 0 V in terms of the higher voltage linear tunneling conductance GT :

G

GT= 1− uNg(vN )− 1

4u2N [g′′(vN )h(vN ) + g′(vN )h′(vN )]

− 18u3N

[14g′′′′(vN )h(vN )2 +

13g′′(vN ) +

12g′′′(vN )h′(vN )h(vN )

]− · · · (2.30)

where

g(x) =x sinh(x)− 4 sinh2(x/2)

8 sinh4(x/2)(2.31)

h(x) = x coth(x/2) (2.32)

uN = 2N − 1N

EckBT

(2.33)

vN =eV

NkBT. (2.34)

For uN 1, the width V1/2 and depth ∆G of the dip in the conductance around V = 0 V

can be expressed entirely in terms of the single island charging energy Ec, the number of


islands N , and physical constants. When Ec and N are known, a conductance measurement

can be used to determine T :

∆GGT

=16uN =

13N − 1N

EckBT

(2.35)

and

eV1/2 = 5.439NkBT. (2.36)

At lower temperatures (kBT ≈ Ec), higher order terms must be included, giving [67]

eV1/2 = 5.439NkBT (1 + 0.3921∆G/GT ) (2.37)

∆GGT

=16uN −

160u2N +

1630

u3N . (2.38)

Although the above equations were derived assuming a uniform 1D model, the results

can be applied to nonuniform 2D arrays by substituting in an effective capacitance Ceff for

the 1D junction capacitance C in the calculation of Ec. Simulations of small 3 × 2 arrays

indicated Ceff ≈ 1.4C [64]. As for disorder, both theory and experiment have demon-

strated that V1/2 and ∆G are only weakly dependent on charge and structural disorder for

temperatures down to T ∼ Ec/kB [67].

For our purposes, we reversed the approach of Coulomb blockade thermometry. Rather

than extract a temperature from a characterized array, we attempted to extract the size

and charging energy from conductance measurements at a known temperature.

2.3.3 Simulations

As will be described in Chapter 5, the devices fabricated and tested in this thesis were

disordered 2D arrays. We performed MOSES simulations of arrays of nonuniform islands

with random charge to obtain a qualitative estimate of the behavior of the experimental

structures. MOSES limits the total number of junctions to 50, so a 4 × 5 island array

with 45 junctions was used, as shown in Fig. 2.9. A triangular array shape was chosen

so that at each interior junction, electrons would have a choice between two paths in the

direction of the drain. Random values were chosen in a normal distribution for junction

capacitances, junction conductances, gate capacitances, and self capacitances. The average


values were C = 3 aF, G = 1 × 10−6 Ω−1, Cg = 0.15 aF, and Cs = 0.03 aF, respec-

tively.

C20,21

C19,20

C18,19

C16,17

C15,16

C11,12

C12,13

C13,14

C9,10

C8,9

C6,7

C4,5

C5,6

8

9

10

11

12

13

14

15

16

17

1

4

5

6

7

2

21

20

19

18

C1,4

C1,5

C1,6

C1,7 C2,21

C2,20

C2,19

C2,18

C4,8

C5,8

C5,9

C6,9

C6,10

C8,11

C8,12

C9,12

C9,13

C10,13

C7,10C10,14

C11,15 C15,18

C15,19C12,15

C12,16 C16,19

C16,20

C17,20

C13,16

C13,17

C14,17 C17,21

Figure 2.9: Schematic diagram of 4 × 5 array used in MOSES simulation. Nodes 1 and 2 are thesource and drain leads; node 3 is the gate lead (not shown). Adjacent nodes are connected by aparallel capacitance (shown) and conductance (not shown).

The result of a MOSES simulation illustrating the distribution of current through the

array with a drain voltage just above threshold is shown in Fig. 2.10a. The current appears

to be in the early stages of the scaling regime, strongly favoring a single path through the

latter half of the array. In Fig. 2.10b, the drain voltage has been increased to the point

that nearly all horizontal paths are involved, and the current is no longer dominated by the

path that was energetically favorable earlier.

Fig. 2.11a is a plot of the current through the array at T = 0 K for several different

distributions of background charge. The threshold voltage can be seen to be different for

each distribution, with the largest VT for the case with all background charges uniformly set

to zero, when the initial potential differences between islands is minimized. When charge

disorder is introduced, the probability is increased for some junctions to start out favorably

biased towards overcoming the Coulomb blockade, thus reducing VT . The VT values range

from 5.3 to 25.6 mV. For comparison, (2.26) of the 2D soliton model gives VT = 43.4 mV,

using the array average values for C and Cg.

The current at higher drain biases through these same arrays is shown in Fig. 2.11b.


4

5

6

7

8

9

10

11

12

13

14 21

20

19

18

15

16

17

1 2

Vdrain = 17.4 mV

Vgate = 0 V

Idrain = 103 pA

T = 0K

0

83

0

17

24

0

16

0

3

56

0

8

33

0

12

3

0

2

42

53

0

1

0

0

4

1

0

0

95

0

1

0

0

4

1

0

2

93

0

1

0

5

1

94

0

(a) V ∼ VT . Current flows along essentially a single path.

4

5

6

7

8

9

10

11

12

13

14 21

20

19

18

15

16

17

1 2

Vdrain = 48.1 mV

Vgate = 0 V

Idrain = 9.26 nA

T = 0K

3

46

36

15

1

1

1

4

26

18

27

11

14

3

1

19

14

24

16

17

9

3

1

0

22

17

19

16

16

9

2

2

19

18

23

14

6

20

1

5

20

41

14

25

1

(b) V VT . Current flows along multiple paths.

Figure 2.10: MOSES simulations of a 4 × 5 disordered array at T = 0 K, showing the percentageof the total current passing through each branch. The increasing line thickness and darker shade ofgrey correspond to increasing percentage.


At these higher drain voltages, the differences between the currents becomes less apparent,

and the currents converge towards I = GT (V − Voffset). Fitting the current at even higher

biases than are shown in Fig. 2.11b, we find Voffset ≈ 52 mV. This is comparable to the

value of 57.3 mV calculated using (2.27) with Ns = 5.

The fit of the current to (2.29) of the Middleton-Wingreen model relies on the choice

of VT . For simulated T = 0 K, VT can simply be chosen as the lowest voltage at which

a non-zero current flows. For T > 0 K, where there may be a finite current for V < VT

in both simulation and experiment, a similar method would be to define an arbitrary low

current level as a threshold. Another possibility is to perform a fit with VT and ζ as fitting

parameters. Deviations from the ideal behavior at both low and high V [68], however,

require that only data from a certain range be fit, and the choice of which points to include

influences VT .

To overcome these limitations, Kurdak et al. developed a method for identifying VT after

noting that the current for V < VT is thermally activated, and that the current for V > VT

is relatively independent of temperature [56]. They plotted the current measured over a

range of temperatures for several voltages on an Arrhenius plot and extracted activation

energies Ea. Plotting Ea versus V , they defined VT as the voltage at which Ea vanished. In

the absence of charge disorder, Ea at V = 0 V corresponds to the charging energy Ec of an

individual island. Fig. 2.12 is an application of this technique to MOSES simulations of the

4 × 5 disordered array, with Ea values taken from positive drain voltages. Extrapolating

the fit line to the right gave VT = 27.7 mV, and to the left gave Ea0 = 4.3 meV. For an

individual island with six adjacent 3 aF tunnel junctions, the estimated charging energy

Ec = 4.5 meV. A fit performed with Ea derived from negative drain voltages, however,

produced an Ea0 = 2.5 meV.

Attempts to fit the simulation results to the Middleton-Wingreen model using different

values of VT for the same current are shown in Fig. 2.13a for T = 0 and 10 K. For the

simulated T = 0 K case, the two VT are determined using the method of Kurdak et al. and

by using the voltage at which the current first turns on. The Kurdak method resulted in

VT = 28 mV, for which the current at lower voltages strayed from the power law, and gave

ζ = 1.15. The other method gave VT = 16 mV, and lead to a better fit to the power law

and ζ = 1.62, which was closer to the theoretical value and those found in simulations and

experiment. The dashed grey line corresponds to ζ = 1, the slope that is expected in the

linear regime when the current flows through all channels. For neither choice of VT did the


0

1

2

3

4

5

0 10 20 30 40

Drain-Source Voltage (mV)

Dra

in-S

ourc

e C

urr

ent

(nA

)

(a) Different charge distributions influence VT .

0

10

20

30

40

0 20 40 60 80 100


Dra

in-S

ourc

e C

urr

ent

(nA

)

Voffset

(b) At higher drain voltages, the influence of different charge distri-butions decreases and the currents converge.

Figure 2.11: MOSES simulations of drain current though a 4 × 5 disordered array at T = 0 K, fordifferent random background charge distributions. The lightest grey line with the highest VT is forall background charges uniformly set to zero.


0

1

2

3

4

5

0 5 10 15 20

Voltage (mV)

Ea (

meV

)

VT = 27.7 mV

Ea0 = 4.3 meV

Figure 2.12: Application of the Kurdak method for determining the threshold voltage from MOSESsimulations of a 4 × 5 disordered array. Extrapolating in both directions gave Ea0 = 4.3 meV andVT = 27.7 mV.


current appear to enter the linear regime for the range of voltage simulated. This suggested

that the primary dependence on voltage arose from the addition or subtraction of current

paths. A path-by-path examination of the simulation results, however, indicated that in the

upper range of simulated voltages, essentially all paths were involved and the distribution

of current between them had reached a stable state.

Fits to the simulation at T = 10 K are shown in Fig. 2.13b. The Kurdak threshold

voltage is independent of temperature, so we used the same value as before. For comparison,

a fit with the T = 0 K turn-on VT used earlier was also included. The third VT was chosen

as the voltage at which the current surpassed the arbitrary threshold of 0.1 nA. As in the

T = 0 K case, the choice of VT had a substantial effect on the value of ζ extracted. The

Kurdak method gave ζ = 1.03 and the T = 0 K choice for VT lead to ζ = 1.37. The final

choice of VT resulted in ζ = 1.77. Similar to the lower temperature simulation, none of the

fits approached linear regime behavior.

We also analyzed the results of a MOSES simulation of a drain voltage sweep at T =

100 K with the techniques of Coulomb blockade thermometry. Fig. 2.14 shows the array

conductance versus voltage, and the measurements of the conductance dip ∆G and full

width at half minimum V1/2. This temperature required the use of the low-temperature

equations (2.37) and (2.38). The extracted values of Ec = 10.2 meV and N = 6.5 were

comparable to the average Ec = 4.5 meV and N = 5 estimated from the array parameters.

The black line in Fig. 2.14 is a plot of (2.30) using the extracted values for Ec and N .

The theory for the current through 2D arrays has focused primarily on describing the

influence of the drain voltage on drain current. As noted in Section 2.2, however, the gate

voltage can affect the drain current as well. Fig. 2.15 shows a MOSES simulation of the

drain current versus the drain voltage through a disordered 4× 5 array for several different

values of gate voltage. The capacitance between each island and the gate was slightly

different, so a change in the gate voltage shifted the potential of each island by a different

amount. These changes in the potential landscape played a similar role as charge disorder,

and influenced which current path was the most energetically favorable.

Fig. 2.16a is a plot of the drain current versus gate voltage for a fully uniform 4 × 5

array, over a single period of the gate voltage. Much like the single island (Fig. 2.8),

the gate voltage predictably controlled the drain current. In contrast, Fig. 2.16b was the

current through a disordered array. Although the pattern of peaks and valleys was irregular,

the gate voltage still demonstrated an ability to strongly influence the drain current. We


1E-10

1E-09

1E-08

1E-07

0.1 1 10

(V/VT)-1

Dra

in-S

ourc

e C

urr

ent

(A)

VT=16 mV (I>0)

!=1.62

VT=28 mV (Kurdak)

!=1.15

T=0 K

!=1

(a) Simulated temperature T = 0 K

1E-10

1E-09

1E-08

1E-07

0.1 1 10 100

(V/VT)-1

Dra

in-S

ourc

e C

urr

ent

(A) VT=28 mV (Kurdak)

!=1.03

VT=6 mV (I>0.1 nA)

!=1.77

VT=16 mV (T=0 K)

!=1.37

T=10K

!=1

(b) Simulated temperature T = 10 K

Figure 2.13: Application of the Middleton-Wingreen model to MOSES simulation results in thescaling regime. The dashed grey line corresponds to ζ = 1, the expected slope for the high voltagelinear regime.


0.6

0.7

0.8

0.9

1

-0.4 -0.2 0 0.2 0.4

Drain-Source Voltage (V)

G/G

T

!G

V1/2

Figure 2.14: Array parameters were extracted from the drain conductance (dI/dV ) of the MOSESsimulation of a 4 × 5 disordered array at T = 100 K. Using Coulomb blockade thermometrytechniques: Ec = 10.2 meV and N = 6.5, comparable to the estimated average Ec = 4.5 meV andN = 5. The black line is (2.30) plotted using the two extracted parameters.

-10

-5

0

5

10

-50 -25 0 25 50

VD (mV)

I D (

nA

)

Figure 2.15: MOSES simulations of drain current versus drain voltage, for several different gatevoltages, for a 4× 5 disordered array at T = 4 K.


consider this behavior, and the way the patterns evolve for different drain biases, to be

another signature of Coulomb blockade. Measurements of our completed devices, presented

in Chapter 5, demonstrated qualitatively similar behavior.


-3

-2

-1

0

1

2

3

0 0.2 0.4 0.6 0.8 1

Gate Voltage (V)

Dra

in C

urr

ent

(nA

)

(a) Uniform array

-3

-2

-1

0

1

2

3

0 0.2 0.4 0.6 0.8 1

Gate Voltage (V)

Dra

in C

urr

ent

(nA

)

(b) Disordered array

Figure 2.16: MOSES simulation of drain current versus gate voltage, for a range of positive andnegative drain voltages, for a 4× 5 array at T = 4 K, showing the effect of disorder.

Chapter 3

Atomic Force Microscope

Oxidation

This chapter describes our effort to use the atomic force microscope (AFM) to directly

pattern structures in semiconductor and metal films. The historical background for this

application of the AFM is covered, and the mechanism of the oxidation process is explained.

Our attempts to fabricate and characterize thin, lateral oxide structures in GaAs, nickel

aluminum (NiAl), and Ti is detailed.

3.1 History

The AFM [69] is one of several kinds of Scanning Probe Microscopes (SPMs), imaging

systems based on the interaction between a specialized probe and a surface. The AFM

measures surface topography with an atomically sharp tip mounted on the end of a can-

tilever. In a typical set-up, height information is provided by a laser reflected off of the

end of the cantilever, which measures the cantilever’s deflection as the tip is rastered across

the surface. AFMs can generally be operated in one of three modes: contact, intermittent-

contact, and non-contact. In contact mode, the tip physically rides over the surface. In

intermittent-contact mode, the tip vibrates, rapidly tapping the surface, and changes in the

amplitude of the vibration are translated into height information. In non-contact mode,

long-range forces act on the tip and cause the cantilever to deflect.

In any of its three imaging modes, the AFM ideally has little effect on the surface

being measured. Under certain conditions, however, the AFM is also capable of intentional

33

CHAPTER 3. ATOMIC FORCE MICROSCOPE OXIDATION 34

manipulation of the surface. A tip that is harder than the surface being scanned can modify

the surface with the application of sufficient force, and Kim and Lieber used the AFM in

this way to carve arbitrary patterns into a surface [70]. Vettiger et al. applied heat to AFM

tips to form indentations in polymer films [71].

AFM oxidation research developed from similar work with the scanning tunneling mi-

croscope (STM). Dagata et al. used the STM to selectively remove hydrogen (H) from a

H-passivated Si surface [72]. Subsequent exposure to ambient oxygen resulted in oxidation

of the newly unpassivated areas. The oxide could then be selectively etched away or used

as a mask for transfer of the pattern into the Si surface. Lyding et al. refined this technique

to produce lines as narrow as 1 nm [73].

In STMs, an electrical tunneling current between the sample surface and the tip hov-

ering above the surface is sensitive to both tip height and surface material, and a feedback

circuit typically maintains a constant current by varying the distance between the tip and

the sample surface. As noted before, in AFM operation, a feedback circuit uses a laser re-

flected off of the end of the cantilever to maintain a constant cantilever deflection, allowing

the current between a conductive tip and the sample surface to be controlled independently

of tip height. One of the first applications of the AFM to lithography was by Majumdar et

al., who used current from an AFM tip to expose PMMA resist [74]. Oxidation with the

AFM was first demonstrated by Day and Allee, who formed 85 nm wide oxide lines [75],

and Ejiri et al., who fabricated 40 nm wide oxide lines [76], on surfaces of natively ox-

idized Si. Snow and Campbell later generated 10 nm wide oxide lines on H-passivated

Si [77].

AFM oxidation was employed for electronic device fabrication by Minne et al., who

used AFM-oxidized amorphous Si as an etch mask in the formation of a MOSFET with a

0.1 µm gate length [78]. Similarly, using H-passivated Si as an etch mask, Campbell et al.

fabricated a side-gated FET with 35 nm gate length [79].

Building on previous STM work [80], Matsumoto et al. used the AFM to oxidize through

3 nm thick Ti films on SiO2 [81, 82, 83]. Instead of being used as a lithography step, the oxide

structures generated were directly used to form an SET. They drew broad oxide lines to

define a 30 nm Ti channel, and narrow oxide lines across the channel to isolate a 30×35 nm2

Ti island between two 27 nm wide TiOx tunnel barriers. With a bias applied through a

back gate, they observed electrical characteristics suggestive of a Coulomb staircase in the

drain current, evidence of Coulomb blockade, at room temperature.


They were later able to improve their device performance by incorporating several en-

hancements to their fabrication process. Performing AFM oxidation on Ti and niobium

films deposited on terraces of atomically-flat α-Al2O3 substrates, Matsumoto et al. were

able to improve the uniformity and reproducibility of their oxide tunnel barriers [84]. The

application of pulsed positive and negative voltages to the AFM tip enabled the fabrica-

tion of oxide lines with higher aspect ratios [85]. A thermal oxidation step following AFM

oxidation was used to shrink the tunnel junction area [86]. A purer Ti film was deposited

under high vacuum (2× 10−8 Torr), improving the stability of the devices during electrical

measurements [87]. Finally, they performed AFM oxidation with an AFM tip on which

they had grown a single-walled carbon nanotube, which allowed for reproducible oxide lines

as narrow as 6 nm [88]. The resulting side-gated SET demonstrated Coulomb diamonds in

electrical measurements at room temperature.

3.2 Oxidation

AFM oxidation of a metal or semiconductor film is initiated by applying a negative voltage

bias to a conductive AFM tip with the sample surface grounded, as shown in Fig. 3.1. The

process utilizes a thin layer of water adsorbed on both the tip and sample when in air [89]

and the meniscus that forms between them in contact mode AFM. The high electric field

(several volts across sub-nanometer scale distances) between the AFM tip and the sample

breaks down the water molecules into H+, OH− and O− ions. The applied electric field

also enhances the diffusion of the OH− and O− ions through the existing oxide down to the

film-oxide interface, where the ions react with the metal or semiconductor film and form

additional oxide.

AFM oxidation has been characterized as having rapid initial growth, followed by a grad-

ually slowing rate [90]. The decreasing rate has been attributed to the development of space

charge across the oxide, which opposes further diffusion of the reactive species. Matsumoto

et al. were able to attain high aspect ratio oxide features with the use of pulsed positive and

negative voltages because the positive voltage pulses cleared the oxide of charged species in

between the oxidizing negative voltage pulses [91].

During lithography, constant force between the tip and sample is maintained by the

AFM’s z-feedback circuit. The sample stage is mounted on a piezoelectric tube, which

automatically lowers or raises the stage to preserve a constant cantilever deflection.


Figure 3.1: Schematic of AFM oxidation process (not to scale). The metal film is locally oxidizedbelow the negatively-biased, moving probe tip.

Oxide structures with widths narrower than the 40 nm radius of a typical AFM tip are

possible due to the strong dependence of the oxidation on the electric field strength, which

is enhanced in the region directly below the tip [77]. The water meniscus between the tip

and film defocuses the electric field, however, placing a lower bound on the resolution which

is dependent on the ambient humidity [90, 92].

3.3 Oxidation of GaAs

The requirement of smooth, uniform starting surfaces suggested that epitaxial semiconduc-

tor films might be good candidates for AFM oxidation of lateral tunneling barriers. The

ability to pattern a 2DEG at a GaAs/AlGaAs interface buried some distance away from the

surface, and immune to surface degradation, was also attractive [93]. Ishii and Matsumoto

used AFM oxidation to deplete a 2DEG wire beneath 24 nm of undoped AlGaAs in a high

electron mobility transistor (HEMT) structure [94]. They were later able to deplete a 2DEG

wire beneath 28 nm of n-doped and undoped GaAs in an inverted HEMT by oxidizing the

GaAs and etching away the oxide [95].

Our initial work focused on minimizing the width of oxide lines on GaAs by investigating

the effects of tip translation speed, tip voltage, and local humidity. The experimental work

was performed on a Digital Instruments (now Veeco, Santa Barbara, Calif.) Multimode


AFM. Using NanoScope III control software [96] with the Nano-Lithography package,

arbitrary patterns were created with scripts which controlled the position, speed, and voltage

of the tip.

3.3.1 Procedure

The first attempts were conducted on GaAs films deposited by molecular beam epitaxy

(MBE). The surface was cleaned by soaks in acetone and isopropyl alcohol, followed by

a dip in 1:1:1 HCl:H2O2:H2O, and a DI water rinse. Samples approximately 1 cm2 were

mounted on slightly larger metal discs with silver paste. An additional drop of the paste at

the edge of the sample was used to electrically connect the sample surface to the metal disc.

The disc served both to secure magnetically the sample to the AFM stage and to complete

the electrical connection to the stage.

Conductive AFM tips were prepared by depositing approximately 30 nm of Ti in an

electron beam evaporator on standard silicon nitride (Si3N4) contact mode AFM tips from

Digital Instruments. The manufacturer specified that the tip of the pyramidal probe had a

radius of 40 nm.

Arrays of simple oxide shapes were drawn at various AFM tip voltages and tip translation

speeds. A lithography script was used to turn the tip voltage on, translate the tip to the

right by 2 µm at a given speed, turn the voltage off, move the tip down, turn the voltage

back on, and translate the tip to the left. The script then instructed the AFM to increase

the voltage and repeat the process. Next, the tip translation speed was increased, and a

similar range of writing voltages was attempted. Finally, the measurements were repeated

for similar writing voltages and speeds after a drop of warm water was applied to the

sample near the tip with a wooden toothpick to increase the local humidity, albeit by an

unmeasured amount.

3.3.2 Results

An AFM image of the oxide lines produced is shown in Fig. 3.2. Measurements of the oxide

line width and height were taken at three points along each line. Line widths of 34–122 nm

and heights of 0.3–6.1 nm were measured, and the results are shown in Fig. 3.3. The widths

and heights of oxide lines drawn while the humidity was increased are shown in Fig. 3.4.

Although considerable spread in the data can be observed, the trends in the data in-

dicated that low tip voltages, faster tip translation speeds, and low humidity all decreased


Figure 3.2: AFM image of oxide lines on GaAs, drawn by AFM oxidation. The tip translation speedwas held constant. Each pair of lines was formed with increasing tip bias, with the lines at the topof the image receiving the highest voltage.


0

20

40

60

80

100

120

140

5 10 15

Tip voltage (V)

Oxid

e li

ne

wid

th (

nm

)v=0.1 !m/sec

v=0.5 !m/sec

v=1.0 !m/sec

(a) Oxide line width.

0

1

2

3

4

5

6

7

5 10 15

Tip voltage (V)

Oxid

e li

ne

hei

ght

(nm

)

v=0.1 !m/sec

v=0.5 !m/sec

v=1.0 !m/sec

(b) Oxide line height.

Figure 3.3: Dimensions of oxide lines drawn at different AFM tip bias voltages and translationspeeds in GaAs. The solid line is a linear fit for a tip translation speed of 0.1 µm/sec, the dashedline for 0.5 µm/sec, and the dotted line for 1.0 µm/sec.


0

100

200

300

400

7 8 9 10 11 12 13 14

Tip voltage (V)

Oxid

e li

ne

wid

th (

nm

)v=0.1 !m/sec

v=0.5 !m/sec

v=1.0 !m/sec

v=5.0 !m/sec

(a) Oxide line width.

0

2

4

6

8

10

12

7 8 9 10 11 12 13 14

Tip voltage (V)

Oxid

e li

ne

hei

ght

(nm

)

v=0.1 !m/sec

v=0.5 !m/sec

v=1.0 !m/sec

v=5.0 !m/sec

(b) Oxide line height.

Figure 3.4: Dimensions of oxide lines drawn at different AFM tip bias voltages and translationspeeds in GaAs, with a drop of water placed on the sample. The solid line is a linear fit for a tiptranslation speed of 0.1 µm/sec, the dashed line for 0.5 µm/sec, the dotted line for 1.0 µm/sec, andthe dot-dash line for 5.0 µm/sec.


the width of the oxide lines. This behavior was consistent with that observed by others

in Si and Ti [76, 80]. Too low a voltage or too fast a tip speed, however, would result in

no oxidation, and we sought to determine the combination of lowest voltage and highest

translation speed that would result in the thinnest possible oxide line.

The humidity during oxidation was generally not under our control, but the room hu-

midity was monitored during the writing process. Oxidation often proved difficult, and

low humidity was suspected as a cause. Our attempt to use a humidifier to increase the

humidity, however, was aborted when condensation formed on the microscope, creating the

risk of an electrical short circuit.

Stievenard et al. [97] developed a model for the height of AFM oxide lines in Si as a

function of both tip voltage and tip speed. The model was based on the work of Cabrera

and Mott, which described the growth of very thin oxide films governed by field induced

oxidation [98]. In Stievenard’s model, the applied voltage adds to the potential difference

driving the diffusion of oxidizing species through the existing oxide. This results in the

oxide height following an inverse logarithmic law with time, with the relevant time being

determined by dividing the oxide line width by the tip translation speed.

1h

=1h1

log v +1h1

logh2L

h1uWox(3.1)

where

h1 = qa′(V0 + Vbias)/kT (3.2)

with a′ corresponding to half of the width of the potential barrier between two diffusion

sites, hL equal to the maximum oxide height beyond which the electric field no longer

enhances the oxidation rate, and

u = u0 exp(−W/kT ) (3.3)

with W being the activation energy for diffusion.

Stievenard et al. appeared to assume a constant line width independent of tip voltage

and translation speed. To account for the influence of these two factors on line width, we

employed an empirical model for the line width, with an inverse logarithmic dependence on


the tip speed and fitting parameters linearly dependent on voltage:

1Wox

= a(V ) + b(V ) log v (3.4)

Attempts to fit our data using the Stievenard model are shown in Fig. 3.5a. The wide

spread in our data makes it difficult to draw a clear conclusion, but the data is consistent

with the trends in both tip voltage and speed predicted by the Stievenard model. The

activation energy derived from this approach is 0.73 eV, and 0.65 eV when the water droplet

was added. The values of a′, however, of 5.1 and 11.8 pm appear to be too small to physically

correspond to half the distance between interstitial diffusion sites as described by Stievenard

et al.

3.3.3 Discussion

Inconsistent line widths, on time scales ranging from the drawing of a single line, to day-

to-day, continued to be a problem. For the shorter time scales, we believed that changes in

the shape of the AFM tip were the cause. A scanning electron microscope (SEM) image of

wear damage to an AFM tip is shown in Fig. 3.6a. Bloo et al. have observed damage to

Si3N4 AFM tips scanning Si surfaces in contact mode, and described the mechanism behind

the deformation and wear [99].

We investigated electron beam evaporated metal coatings of Ni and Cr, but found little

improvement over the original Ti. SEM images of the tips coated with other materials

indicated problems such as poor adhesion, as shown in Fig. 3.6b. Film stress leading to

bending of the cantilever was another problem. All of our coatings were deposited with an

electron beam evaporator, however, and Gordon et al. noted that sputtered metal films on

AFM tips may contain less stress than evaporated ones [100]. Ultralever conductive Si tips

from Park Scientific Instruments, notable for their conical shape and high aspect ratios, were

also used without improved consistency. The most consistent results were produced with

PtIr-coated tips from Digital Instruments intended for use with Magnetic Force Microscopy.

Even with these tips, however, line width variation was still evident. AFM imaging and

oxidation with carbon nanotube-based tips have been performed by Gotoh et al. with some

success [101].

For longer time-scale variations we suspected differences in surface conditions. The

samples were stored in plastic containers in air and were exposed to open air during imaging


0

1

2

3

4

5

6

5 10 15

Tip voltage (V)

Oxid

e li

ne

hei

ght

(nm

) v=0.1 !m/sec

v=0.5 !m/secv=1.0 !m/sec

(a) Oxide line heights.

0

2

4

6

8

10

7 8 9 10 11 12 13 14

Tip voltage (V)

Oxid

e li

ne

hei

ght

(nm

)

v=0.1 !m/sec

v=0.5 !m/sec

v=1.0 !m/secv=5.0 !m/sec

(b) Oxide line heights with humidity increased.

Figure 3.5: Height of oxide lines drawn at different AFM tip bias voltages and translation speeds inGaAs, compared to the Stievenard model.


(a) Wear on Ni coated AFM tip.

(b) Cr coating peeling from AFM tip.

Figure 3.6: SEM images of contact mode AFM tips used for lithography, with different metalcoatings.


and oxidation. Imaging of the surface often indicated the presence of contamination on the

surface. As a general rule, the area to be oxidized was imaged prior to oxidation for

placement surfaces. This also served a cleaning purpose, using the AFM tip to physically

scrape the surface clean, and we observed accumulations of debris at the edges of the initial

scan.

We attempted a number of different solvent cleaning solutions, including ultrasonic

baths of acetone, methanol, and isopropyl alcohol; boiling acetone; and cotton swab scrubs

under acetone. Solvent cleans of the sample immediately prior to each run proved difficult,

however, due to the silver paste used to secure the samples to the metal disc sample holders.

Although the paste would dissolve under the various solvents, other particles from the paste

would often adhere to the surface, leaving it dirtier than before. A mechanical mount that

provided electrical contact between the surface and the sample holder may have allowed for

more frequent cleaning, but may also have been unable to provide the sub-nanometer level

of sample stability required.

Yoshitaka Okada, a visiting professor who worked with us while at Stanford, continued

to work on GaAs oxidation with the AFM on his return to Japan. He and his collaborators

used AFM-generated oxide lines to define a 30 × 30 nm2 island in a 2DEG, and observed

single electron effects at a measurement temperature of 15 K [102]. They also improved the

oxide aspect ratio through the use of pulsed voltages. Unlike Matsumoto et al. [85], who

modulated the applied voltage between positive and negative values, Okada et al. modulated

the applied voltage between negative voltages and zero [103].

A challenge inherent to working with GaAs is that As oxide is water soluble. Further-

more, in comparison to metals, the lower electron density means that quantum confinement

effects become a factor at larger device dimensions and complicate transport. For these

reasons, we turned our focus to AFM oxidation of metal films.

3.4 Oxidation of NiAl

Our research group possessed the capability to grow epitaxial NiAl lattice-matched to GaAs

by MBE, so we attempted to oxidize thin NiAl films on a semi-insulating GaAs substrate.

Crystalline NiAl had the potential for several advantages over the polycrystalline Ti used in

previous work by others, with an atomically smooth surface and a possible Al oxide with a

higher barrier height than TiOx. Following a procedure very similar to that used for GaAs,


we succeeded in generating structures which we believed resulted from the oxidizing of NiAl

to Al oxide.

After successful AFM oxidation of uniform NiAl films, we used optical lithography with a

contact mask, and wet etching to produce patterned films on which electrical measurements

could be performed. The structures consisted of 2 µm-wide strips 10 µm long, with wide

contact pads at both ends. One contact pad of each device was connected to a grid that

spanned the sample. Silver paint was again used to link the grid to the sample holder.

Calibration of the preferred tip voltage and speed for oxidation were performed in the

contact pad regions prior to oxidizing the central strips.

We aligned the AFM to a specific location along a NiAl strip by first using the AFM’s

optical microscope to visually place the tip. An initial 10 µm AFM scan would be performed

to determine the actual location of the tip, followed by successively smaller scans to refine

the placement. Following oxidation of the desired structures, we isolated the device from

the grid by using the AFM to draw oxide lines across the bridge between the contact pad

and the grid.

Multiple oxide lines were drawn across the strips, forming metal-insulator-metal (MIM)

junctions. Fig. 3.7 is an AFM image of an MIM structure. Electrical measurements of these

junctions, however, revealed a high leakage current. The fate of the remaining Ni atoms

after oxidation was unclear, suggesting their possible contribution to the leakage current.

In addition, the NiAl was grown on a GaAs buffer, whose resistance was potentially much

lower than the semi-insulating GaAs substrate. Simple measurements of the temperature

dependence of the current through the MIM junction were compared with the current

between two contacts to the buffer. The similarity of their behavior suggested that the

leakage current passed through the buffer layer.

The leakage current problems, as well as continued difficulties with reproducibility, led

us to abandon NiAl and focus our investigation on Ti, which had been used successfully by

others [83, 104].

3.5 Oxidation of Ti

Ti oxidized at a lower applied tip voltage, and somewhat more consistently, than NiAl. The

electrical barrier height of the Ti oxide fabricated by AFM oxidation was determined. The

high resistivity observed in our thin Ti films was investigated, and the dependence on film


Figure 3.7: AFM image of AFM-oxidized barrier across NiAl wire. Both the NiAl film and the GaAssubstrate appear to have been oxidized.

thickness and temperature suggested that the thinner films were electrically discontinuous.

Finally, SET device structures were fabricated and tested, but single electron behavior was

not observed at room temperature.

3.5.1 Ti Oxide Barrier Height Characterization

The Ti/TiOx electrical barrier height was determined by looking at the thermionic emission

current through a Ti wire with a barrier. Similar measurements of a Ti wire without a

barrier showed a linear I-V characteristic, but also demonstrated a negative temperature

coefficient of resistance, possibly indicating a discontinuous film.

Procedure

Ti films 3–5 nm thick were deposited with an electron beam evaporator onto 100 nm of

thermally-grown SiO2 on a Si substrate. Film thicknesses were measured during deposition

with a quartz crystal monitor. Typical deposition pressures were in the high 10−8 to low

10−7 Torr range. The Ti films were patterned into wires, 2 µm wide and 10 µm long, with


optical lithography using contact masks, and wet etching with dilute hydrofluoric acid (HF).

Ti/Au contacts were deposited using optical lithography, electron beam evaporation, and

lift-off in acetone.

We successfully used the AFM to fabricate oxide structures more complicated than we

had previously achieved in GaAs or NiAl. These structures used slower tip translation

speeds during oxidation to produce thick side regions defining a narrow channel 0.5 µm

long and roughly 200 nm wide. Finer oxide barriers were drawn across the channel with a

newer and sharper tip moving at higher speeds. Fig. 3.8 shows an MIM junction fabricated

in this manner. Wire-bonded contacts to the thin Ti film proved unreliable, however, and

only a small number of devices were able to be tested electrically.

Electrical characterization was performed in a liquid nitrogen cryostat with an HP4145

semiconductor parameter analyzer. I-V measurements were made of Ti channels both with

and without oxide barriers.

Figure 3.8: AFM image of Ti MIM junction fabricated by AFM oxidation. AFM oxidation was usedto both define the channel and form the thin barrier.


Results and Discussion

Fig. 3.9 shows the nonlinear current through the MIM junction at measurement temper-

atures T=200–280 K. The temperature and field dependence of the thermionic emission

current over a MIM barrier is described by the expression

J ∼ T 2 exp[− q

kT(φB −∆φ)

](3.5)

where

∆φ =

√qE

4πε(3.6)

arises from image force lowering [105]. Voltage-dependent barrier heights are obtained from

the slopes of ln(J/T 2) plotted versus 1/T for a range of applied voltages. Plotting the bar-

rier heights versus the square root of the voltage, and extrapolating to V = 0 V gives the

zero-bias barrier height. The result shown in Fig. 3.10 for one sample indicated a zero-bias

barrier height of 0.30 eV, which is consistent with the value obtained by Matsumoto [83].

Measurements of MIM junctions from different depositions, however, showed barrier heights

as low as 0.11 eV.

-600

-400

-200

0

200

400

600

-5 -4 -3 -2 -1 0 1 2 3 4 5

Voltage (V)

Curr

ent

(pA

)

T=280 K

T=200 K

Figure 3.9: I-V measurements through an AFM-oxidized MIM junction, at temperatures T=200–280 K.


0

0.05

0.1

0.15

0.2

0.25

0.4 0.6 0.8 1

Voltage1/2

(V1/2

)

Bar

rier

Hei

ght

(eV

)

!B0=0.30 eV

Figure 3.10: Barrier height determination of AFM-oxidized MIM junction.

The current through a channel without an oxide barrier is shown in Fig. 3.11. Two key

features were apparent: a Ti resistivity much higher than the bulk value, and a negative

temperature coefficient of resistance (TCR). The high resistivity can be explained by in-

creased electron scattering by film surfaces, grain boundaries, and impurities. The negative

TCR was likely the result of a discontinuous film.

Fuchs and Sondheimer described how the resistivity of a thin, metallic film increases

with decreasing film thickness by noting the growing role played by surface scattering when

the film thickness becomes comparable to the electron mean free path [106, 107]. Mayadas

and Shatzkes accounted for a similar contribution from grain boundary scattering in a

polycrystalline film when the grain size was comparable to the electron mean free path [108].

This effect was verified experimentally in thin Ti films by Igasaki and Mitsuhashi [109]. An

additional role played by film thickness was noted by Day et al., who found that the Ti

grain size decreased with decreasing film thickness [110].

Due to the high reactivity of Ti, thin films of Ti may incorporate high levels of oxy-

gen. Singh and Surplice found it necessary to include scattering from residual gases to

account for the resistivity values they measured in Ti films [111]. Day et al. described

fast diffusion of oxygen atoms along Ti grain boundaries as contributing to increased grain

boundary scattering [110]. Higher oxygen content was found by Hofmann et al. to lead to


-2

-1

0

1

2

-5 -4 -3 -2 -1 0 1 2 3 4 5

Voltage (V)

Curr

ent

(nA

)

T=200 K

T=290 K

Figure 3.11: I-V measurements through Ti channel defined by AFM oxidation, at temperaturesT=200–290 K. The solid lines are experimental data, and the dashed lines are a fit to VRH.

smaller grains with more random orientation, also leading to more grain boundary scatter-

ing [16].

Typical deposition pressures in our electron beam evaporator were in the high 10−8 to

low 10−7 Torr range. This corresponded to oxygen impinging on the surface at a rate of

approximately 0.05 nm/sec [112], while Ti deposition rates were as low as 0.1 nm/sec. If

the oxygen sticking coefficient was close to unity, the oxygen levels in the Ti film were near

the 34 atomic % solid solubility limit [113].

Negative TCR in thin metal films has been explained as resulting from the film actually

being discontinuous [9, 10, 114]. The initial stages of deposition may involve Ti atoms

forming separate clusters which would then coalesce at larger thicknesses. Conversely, Syl-

westrowicz observed that an already deposited continuous film may be rendered electrically

discontinuous by oxidation along grain boundaries [115]. The latter description is the more

likely one for our case, as AFM imaging of the Ti films showed physically continuous films

with surface roughness less than 1 nm.

Electron transport through a discontinuous film can be described by Mott’s variable

range hopping (VRH) conduction [116]. Localized electrons hop from site to site with a

probability determined by the separation in both energy and distance. This leads to a


conductivity with a temperature dependence given by:

σ = σ0 exp[−(T0/T )

14

]. (3.7)

The dashed lines in Fig. 3.11 are derived from a fit of the measured data to the VRH

equation. The fit to T−1/4 was slightly better than the fit to T−1, but both were adequate

fits over the limited temperature range of the measurement. The standard VRH model did

not, however, account for the slight field dependence in the measured data.

3.5.2 Ti Film Characterization

To further investigate the nature of thin Ti, films were deposited with different thicknesses

and their resistivities were measured. Additional evidence was obtained that our thin Ti

films were electrically discontinuous.

Procedure

Ti films with thicknesses in the range 2–26 nm were deposited and patterned in a manner

identical to that described in the previous section. The film resistance was measured using

a 50 µm wide Ti strip with Ti/Au contacts placed with varying separations along the strip.

Room temperature I-V measurements were performed in a probe station with an HP4155

semiconductor parameter analyzer. The measured resistance was plotted versus the distance

between the contacts being probed. The film resistivity was derived from the slope of the

line fitting the resistance values.


Fig. 3.12 shows the Ti film resistivity for the different film thicknesses. Not shown in the

figure is the resistivity of the 2 nm thick film, which was measured as 7.9×105 µΩ-cm. The

resistivity increased rapidly as the thickness dropped below 12 nm, but appeared to saturate

around 120 µΩ-cm at thicknesses greater than 12 nm. The value for the thicker films was

approximately three times greater than the resistivity of bulk Ti, 42 µΩ-cm [117]. For an

estimate of oxygen content, Ottaviani et al. correlated a Ti film resistivity of 112 µΩ-cm with

an oxygen concentration of 20% [113]. Additional analysis of the thin Ti film composition

is described in the next chapter.


0

100

200

300

400

0 10 20 30

Thickness (nm)

Res

isti

vit

y (!!

-cm

)

Figure 3.12: Ti film resistivity increased as deposited film thickness decreased. Resistivity of 2 nmthick film (7.9× 105 µΩ-cm) not shown.

Singh and Surplice described their thin Ti film resistivity using the following equation:

ln d = − 4l03σ0

σ

d+ (0.4228 + ln l0) (3.8)

where d is the film thickness (in Angstroms), σ is the film conductivity (in Ω-cm), and l0

and σ0 are the bulk mean free path and conductivity [111]. Rearranging the equation to

plot σ/d versus ln(d) resulted in the plot shown in Fig. 3.13. The bulk mean free path

derived from the x-intercept was 32.2 nm, consistent with the values found by Singh and

Surplice. The bulk conductivity extracted was 47.4 µΩ-cm. Singh and Surplice described

the point where the slope changes from positive to negative as the thickness where the film

goes from discontinuous to continuous. Their value of 7 ± 2 nm is similar to the 11.5 nm

value derived from Fig. 3.13. The Ti film measured in the previous section, and many of the

Ti films used in the next chapter, were thinner than 11.5 nm, and thus likely discontinuous.

In an effort to directly measure the grain structure and size in our Ti films, we performed

transmission electron microscopy (TEM). Difficulties with conventional sample preparation

led to the use of Si3N4 membranes from SPI Supplies (West Chester, Pa.). 4 nm and 25 nm

thick Ti films were evaporated onto 100 nm thick Si3N4 “windows,” and plan view TEM


0

200

400

600

800

0.5 1.5 2.5 3.5

ln(Thickness)

Cond

uct

ivit

y/T

hic

knes

s ( !

cm

nm

)-1

Figure 3.13: Nossek plot indicated that Ti film was discontinuous for thicknesses below 11.5 nm.

was conducted with minimal additional sample preparation. We were unable to clearly

distinguish Ti features in the thinner film samples. In the 25 nm thick film, individual

grains less than 10 nm in diameter were observed, as shown in Fig. 3.14. A continuous

grain structure was not seen, however.

3.5.3 Ti SET Fabrication and Measurement

Three-terminal device structures designed to demonstrate single-electron effects were fabri-

cated and tested. Only a small number of devices were fabricated, and none showed clear

evidence of Coulomb blockade at room temperature.

Procedure

Ti films were deposited and patterned as described previously. The structures were similar

to those of Matsumoto [83], with two continuous thick oxide barriers, drawn in a raster

pattern, defining the gate width, two more thick oxide barriers setting the channel width

and the separation of the gate from the channel, and a third set of thin oxide lines acting

as tunnel junctions. Room temperature I-V measurements were made on a probe station

with an HP4145 semiconductor parameter analyzer.


Figure 3.14: Plan view TEM image of 25 nm thick polycrystalline Ti film, showing Ti grains withdiameters less than 10 nm.


Fig. 3.15 is an AFM image of a three-terminal device structure created with AFM oxidation.

Barriers as thin as 20 nm were fabricated, and defined single and multiple islands as small

as 30 × 70 nm2 in the central channel, as shown in Fig. 3.16. The device capacitances

were estimated using the device geometry as measured by AFM, and the simple parallel

plate capacitor formula. (Knoll et al. have developed a more accurate, but much more

complicated, method for numerically calculating the capacitance between thin, coplanar

electrodes [118].) The parallel plate model gave a junction capacitance Cj = 5.36 aF,

gate capacitance Cg = 0.02 aF, and self capacitance Cs = 0.73 aF. These capacitances

corresponded to an island charging energy of 13.1 meV, or an equivalent temperature of

152 K. For Coulomb blockade effects to be clearly observed, measurements would likely

have to be made below 76 K.

A room temperature I-V characteristic through a structure with four barriers is shown

in Fig. 3.17. The nonlinear current had a higher resistance region at low bias, similar to

Coulomb blockade. The dashed line in Fig. 3.17 is a fit to thermionic emission behavior,


Figure 3.15: AFM image of three terminal structure. T-junction patterned with optical lithographyand etching, central channel and side gate defined by AFM oxidation.

however, and describes the I-V characteristic fairly well. We concluded that Coulomb

blockade was not occurring at room temperature.

Additional measurements at lower temperatures, where the lower thermal energy would

have made Coulomb blockade more energetically probable, may have demonstrated Coulomb

blockade behavior. Practical limitations prevented these measurements, however. We were

only able to fabricate a small number of devices with AFM oxidation. Wire bonded contacts

were necessary for low temperature measurements, and due to the wire bonding difficulties

mentioned earlier, we were unable to successfully wire bond a device for low temperature

testing.

Two key challenges that we were unable to overcome were thinner barriers and consistent

oxidation. We were unable to achieve barriers in the 10–20 nm thickness range necessary

for the tunneling currents required for SET device operation. Our efforts were further

complicated by our continued inability to obtain the level of reproducible AFM oxidation

results that would allow us to optimize oxidation conditions. Since we had demonstrated an

ability to define the narrow channels required for SET devices, we sought another method for


Figure 3.16: AFM image of central channel, showing Ti MIM junctions fabricated by AFM oxidation.Barriers were as thin as 20 nm, and islands had areas ∼30× 70 nm2.

creating the oxide tunneling barriers, that of current induced oxidation, which is described

in the next chapter.


-150

-100

-50

0

50

100

150

-1 -0.5 0 0.5 1

Voltage (V)

Curr

ent

(pA

)

Figure 3.17: Room temperature I-V measurement of single electron device structure. The dashedline is a fit to thermionic emission behavior.

Chapter 4

Current Induced Local Oxidation

4.1 Introduction

Current-induced local oxidation (CILO) was introduced by Avouris et al. [34, 119, 120],

of IBM Research Division in 1998. CILO uses high current densities to enhance local

oxidation rates in thin metal films, generating lateral tunneling barriers. The self-limiting

nature of the process offered the promise of improved reproducibility over AFM oxidation,

and Avouris et al. successfully fabricated oxide barriers as thin as 10 nm.

We incorporated CILO into our SET fabrication by combining it with our existing AFM

oxidation capabilities. We developed a novel process whereby we used AFM oxidation to

define the overall shape of the SET, CILO to create the source and drain tunneling barriers,

and then AFM oxidation again to define a lateral gate. Unfortunately, we later learned that

Avouris et al. had the identical idea, which they used to fabricate an SET that exhibited a

Coulomb staircase [120].

To further investigate the CILO process, we elected to use electron beam lithography,

instead of AFM oxidation, to define the structures needed for CILO. We hoped that this

would allow us to more quickly and reproducibly create arrays of structures with different

shapes and dimensions with which we could study the influence of the current density and

its local variation on CILO. Although that did not turn out to be the case, we were able

to investigate other aspects of the process.

This chapter first describes the work performed by Avouris et al. and the theoretical

framework behind CILO that they established. The results of our own experiments char-

acterizing the barrier height of the CILO oxide, determining the minimum current density

59

CHAPTER 4. CURRENT INDUCED LOCAL OXIDATION 60

required for CILO, investigating the role of heating in the CILO process, and analyzing

the composition of thin metal oxides are presented next. Finally, enhancements to the

resistance model developed by Avouris et al. are discussed.

4.2 Background

The CILO process generates local oxide barriers at constrictions in thin, metal conductors.

Avouris et al. first deposited 4 nm thick Ti films by evaporation, and used optical lithography

to pattern 1–2 µm wide wires. They then used AFM oxidation to oxidize wedge-shaped

regions of the wires, leaving a 100–200 nm wide conducting channel, as shown in Fig. 4.1.

The application of a stress voltage to the leads produced a current with a high current

density at the constriction. Electrical and AFM measurements verified that an oxide barrier

was created in the channel.

Figure 4.1: Avouris et al. used AFM oxidation to define a 100–200 nm wide channel in a Ti wire.Passing a current through the wire locally oxidizes the Ti in the channel [34].

Avouris et al. attributed the enhanced local oxidation rate primarily to electromigration.

The current density in the channel was approximately 107 A/cm2, which is consistent with

the early stages of electromigration. The electron wind force pushes a small number of Ti

atoms from their lattice sites. The resulting vacancies travel in a direction opposite to the

electron current, and gather around grain boundaries. Nanocracks then develop around

the grain boundaries, allowing greater movement of oxidants (O2 and H2O) from the film

surface into the bulk, as shown in Fig. 4.2.


Figure 4.2: Electromigration causes vacancies to accumulate at grain boundaries. The resultingnanocracks enhance the movement of oxidants into the metal film. (After Martel et al. [120])

Avouris et al. also noted that the high current density causes Joule heating, which they

estimated could raise the temperature in the channel as high as 1000 K. Such heating

would increase the oxidation rate by enhancing the diffusion of oxidants and increasing

the chemical reaction rate. They also noted a possible role played by a local heating phe-

nomenon due to vibrational excitation that occurs at high current densities. This concept

developed out of their previous work on atomic manipulation with the scanning tunneling

microscope [121].

The progress of the oxidation was measured by monitoring the CILO current under

the application of a constant stress voltage. They assumed a total ohmic resistance which

could be divided into a lead resistance Rlead and a channel resistance Rchannel, as shown in

Fig. 4.3. Rchannel is ohmic, and given by:

Rchannel =ρl

tw(4.1)

where ρ and t are the Ti film resistivity and thickness, and l and w are the channel length

and width. Rlead remains constant, and the change in Rchannel is due to the decrease in the

cross-sectional area as the oxide grows down from the surface. As can be seen in Fig. 4.4,

data from our own work, the current initially changes very little, and then makes a steep


drop at the end of the process. In resistance terms, the total resistance is initially dominated

by Rlead. It is only when the area in the channel has been reduced by ∼95% that Rchannelbegins to take over and the current falls sharply. Avouris et al. found an empirical fit to

the CILO current with the expression:

dS

dt∝ −j4 (4.2)

where S = tw is the cross-sectional area and j is the current density in the constriction.

This high sensitivity to the current density helps to explain why the oxidation is limited

spatially to the area in the constriction, and why further oxidation does not occur once

the current drops to the lower value. The self-limiting nature of the CILO process holds

particular promise in nanofabrication, as tight control of the oxidation time is not required.

Figure 4.3: The total resistance consisted of the constant lead resistance and the variable channelresistance.

Avouris et al. also observed quantized conductance through their barriers as the oxida-

tion neared completion. Conduction through the almost complete barriers was attributed

to atomic-scale channels, each with a conductance given by:

G =2e2

h(4.3)

where e is the electron charge, and h is the Planck constant. As the number of channels

decreased one by one, discrete downward steps were observed in the current.

Fig. 4.5 shows the current measured through one of our devices before and after the

CILO process. The resulting MIM junction produced a nonlinear I-V characteristic and a

much lower current than that measured prior to CILO.


0

0.05

0.1

0.15

0.2

0 20 40 60 80

Time (sec)

Curr

ent

(mA

)

Figure 4.4: Current through the channel during the CILO process.

1E-12

1E-10

1E-08

1E-06

1E-04

0 0.2 0.4 0.6 0.8 1

Voltage (V)

Curr

ent

(A)

After CILO

Before CILO

Figure 4.5: Current through a device before and after the CILO process.


In our attempts to duplicate the work of Avouris et al., we observed some differences,

and conducted our own experiments to determine the cause.

4.3 Barrier Height Determination

We measured the electrical barrier height of an oxide barrier created with CILO, and com-

pared the value with that from our AFM oxidation and those reported by others.

4.3.1 Procedure

The patterned Ti wire structures employed for this experiment were from the same samples

used for the characterization of AFM oxide barriers. Channels were defined in Ti wires with

AFM oxidation, with 0.5 µm thick oxide barriers drawn in a raster fashion from the edges,

and the central constriction formed by two triangular extensions, as shown in Fig. 4.6.

Using an HP4145 semiconductor parameter analyzer, stress voltages were applied until an

abrupt drop in the current was observed, indicating the formation of an oxide barrier. The

current through the device was measured both before and after CILO. The devices were

wire-bonded, and measured in a cryostat at the same time as the AFM oxide barriers in

the previous chapter. Using the same procedure as described for the AFM oxide barriers,

the zero-bias barrier height was calculated.

4.3.2 Results

Fig. 4.7 shows the measured barrier height from one CILO MIM device measured at temper-

atures T=200–290 K. The data points extrapolated to a zero-bias barrier height of 0.14 eV.

Barrier heights in two other similarly prepared and measured MIM junctions were 0.06 and

0.12 eV. These values lie on the lower end of the 0.1–0.3 eV range of reported values for Ti

oxide barriers fabricated with AFM or CILO [83, 120, 122]. Avouris et al. noted that the

0.24 eV barrier height they measured for their CILO oxide was at the high end of the range,

and suggested that the heat generated by the high current density annealed the oxide. If

this was the case, we did not generate as much heat with our currents, or our oxides formed

differently.


Figure 4.6: AFM image of CILO barrier formed in a channel defined by AFM oxidation.

0.09

0.1

0.11

0.12

0.13

0.4 0.6 0.8 1

Voltage1/2

(V1/2

)

Bar

rier

hei

ght

(eV

)

!B0=0.14 eV

Figure 4.7: Barrier height determination of MIM junction fabricated by CILO.


4.3.3 Discussion

The current we observed during CILO behaved somewhat similarly to that reported by

Avouris et al. The current steps attributed to quantum conductance were not observed,

however. Although this may have been partly due to the larger time steps that we used

in our CILO current measurements, our currents continued to slowly decline following the

abrupt current drop, while theirs appeared to fall to a constant value. The final resistance

of our MIM devices was similar to those measured by Avouris et al.

4.4 Minimum Current Density for CILO

Avouris et al. noted that lower applied stress voltages resulted in thinner oxide barriers, so

we attempted to determine the minimum current, or current density, required for CILO in

our structures in order to obtain the thinnest possible tunneling barriers.

4.4.1 Procedure

Ti wires with central constrictions were prepared using electron beam lithography and lift-

off. Electron beam lithography was conducted with a Hitachi HL-700 F system, with ZEP

520 positive e-beam resist, and CAPROX [123] proximity correction. The Ti films were

deposited with a thickness of ∼8.5 nm as measured by the crystal oscillator, and ∼10 nm

as later measured by AFM. The substrate was a Si wafer, with a top layer of 100 nm of

thermally grown SiO2. Lift-off was performed in acetone, in a beaker resting in an ultrasonic

bath. AFM was used to measure the width of the constrictions.

Electrical measurements were performed on a probe station, with an HP4156 semicon-

ductor parameter analyzer. An arbitrary constant low voltage was applied across two outer

leads, and the HP4156’s two VMU leads were used to monitor the voltage between two

inner leads connected 2 µm from the channel. If no appreciable change in the current was

observed within five minutes, the process was repeated with an increased voltage. If the

current displayed a clear downward trend, but did not complete an abrupt drop during the

five minute span, the same voltage was applied for another five minutes. This process was

repeated until the abrupt drop characteristic of CILO was observed.


4.4.2 Results

The current densities required to initiate CILO in devices with a range of constriction widths

are shown in Fig. 4.8. The average value of j = 2 × 107 A/cm2 was consistent with the

value of j ∼= 107 A/cm2 reported by Avouris et al. [34]. Our electron beam lithographically

defined constrictions had widths from 335 nm up to 590 nm, whereas the constrictions of

Avouris et al. were defined with AFM oxidation, with widths in the 100 nm range. The Ti

film used in this experiment was also almost three times as thick as the 4 nm films of Avouris

et al. Thus, although the current densities were similar, the current in our experiments was

as much as an order of magnitude larger.

0E+00

1E+07

2E+07

3E+07

300 400 500 600

Channel width (nm)

Init

ial

CIL

O c

urr

ent

den

sity

(A

/cm

2)

Figure 4.8: Minimum current to initiate CILO in channels defined by e-beam lithography.

4.4.3 Discussion

Another difference between our work and that of Avouris et al. was the precise location of the

oxide barrier relative to the constriction. The barriers of Avouris et al. naturally developed

precisely at the narrowest point of the constriction, where the current density was highest.

Our oxide barriers, however, generally formed slightly in the downwind direction of the

electron flow. This was observed both for channels we defined with AFM oxidation and


with electron beam lithography. We believed that heat generated by the current in the

constriction was carried downwind by the electrons, where the heat continued to affect the

film.

This idea was partially supported by the observations of well-defined halos that some-

times occurred further downwind on some of our earlier channels defined by AFM oxidation,

an example of which is shown in Fig. 4.9. The shape of the halo roughly correlated with con-

tours of constant current density from simulations. This kind of structure was not reported

by Avouris et al.

Figure 4.9: AFM image of CILO barrier and halo formed slightly downwind of a channel defined byAFM oxidation.

Another key difference was the form of the damage that occurred when the CILO process

failed. Avouris et al. observed damage that they attributed to electromigration when they

applied current densities on the order of j = 108 A/cm2. This damage took the form of

accumulation of material upwind of the constriction, and the formation of voids in the

downwind direction, consistent with the type of damage expected from large amounts of

electromigration. We observed a different kind of damage, as seen in Fig. 4.10. In addition

to appearing when excessive current was applied, this form of damage also occurred in


certain samples even when the CILO current was minimized. We believed that this damage

was due not to electromigration, but to heat being carried downwind by the electrons.

Figure 4.10: AFM image of CILO damage located downwind of a channel defined by electron beamlithography.

To avoid this damage on certain susceptible samples, we developed a process of multiple,

partial oxidations. We found that if we interrupted the process immediately after the

conductance had dropped by ∼10 µS, the damage would not occur. By repeatedly restarting

the CILO, each time with a lower applied voltage, we were able to create a complete oxide

barrier and avoid the damage. A plot of the CILO current from this process is shown in

Fig. 4.11. The plot also shows the channel conductance, which was determined by dividing

the current by the voltage measured by the inner voltage probes.

4.5 Heating and XPS Characterization of Ti Films

Avouris et al. identified electromigration and heating as the two driving forces behind CILO.

In our experiments, however, the downwind location of the oxide barrier, the downwind

appearance of a halo, and the form of the damage appeared to point to heating as the

primary force. As noted earlier, Avouris et al. estimated that the temperature in the


0

0.2

0.4

0.6

0.8

0 500 1000 1500

Time (sec)

Curr

ent

(mA

)

0

100

200

300

Conduct

ance

(!

mho)

24 V

16 V

13 V

10 V

Figure 4.11: CILO current and channel conductance during multiple, partial oxidations. The appliedstress voltages are noted in the plot.

channel may rise as high as 1000 K [119]. We conducted two experiments to investigate

the role of heating in the CILO process, and determine the dependence of the oxidation

rate on temperature. In both experiments, we baked thin Ti film samples on a hotplate in

air, then made electrical and spectroscopic measurements to determine how the film had

changed.

4.5.1 Procedure

In the first experiment, six samples, approximately 1 cm2, were cleaved from the same wafer.

Each sample contained a 1 µm wide Ti wire. The thickness of the Ti film on each sample was

measured with the AFM, using the NanoScope “Bearing” analysis [96]. The thickness was

determined by measuring the distance between the two peaks of the “Bearing” histogram,

which represented the average vertical locations of the substrate and film surfaces. The wire

resistance was measured with an HP4156 semiconductor parameter analyzer in a 4-probe

arrangement.

Each sample was baked for 2 minutes on a hotplate in air, at temperatures from 150 to

275 C. The samples were cooled to room temperature, and the thickness and resistance


were remeasured. This process was repeated four more times, so that the samples were

baked for a total of 10 minutes.

The second experiment used unpatterned samples with 4 and 6 nm thick Ti films, each

baked for a given temperature and time. The focus was on lower temperatures and shorter

times than the previous experiment, and the samples were baked at 175 and 200 C, for

times up to 4 minutes. The resistivity of the films was measured on a 4-probe van der

Pauw [124] system before and after the hotplate bake.

XPS is a surface-sensitive method for determining material composition. The sample

is bombarded with x-rays that excite core electrons, which are emitted from the sample

with characteristic kinetic energies. In addition, these energies are sensitive to chemical

bonds, enabling the identification of different chemical species. The instrument used for

this work was an SSI S-Probe Monochromatized XPS Spectrometer with Al Kα probe.

Low resolution scans from 0 to 1 keV were taken, and the relative amounts of the key

elements present were determined by measuring the area of the C 1s, N 1s, O 1s, Ti 2p,

and Si 2p peaks. Higher resolution scans of the O and Ti peaks were then used to determine

the relative amounts of different species.

In addition to surface characterization, information about the depth and thickness of

shallow buried layers can be provided by two techniques, angle resolved XPS (ARXPS)

and ion etch depth profiling. ARXPS takes advantage of the short electron escape depth

by collecting data from two different angles to extract layer composition, position, and

thickness information [125]. In ion etch depth profiling, argon ions are used to sputter

surface material in between XPS scans. We used both techniques to analyze our Ti films

before and after heating.

4.5.2 Results

The results of the AFM film thickness measurements are shown in Fig. 4.12. A discontinuity

between the thicknesses measured at 4 and 6 minutes is evident. After an initial AFM

measurement of the 6 minute samples produced very poor images, the samples underwent

a solvent clean. Following the cleaning, the images were clearer, but the measured film

thicknesses of several samples had decreased from the 4 minute measurement. The increase

of the film thickness with temperature and time, which we attributed to oxide growth, was

still clear, however.


8

9

10

11

12

13

0 2 4 6 8 10

Time (minutes)

Thic

knes

s (n

m)

150 °C

200 °C225 °C250 °C

T=275 °C

175 °C

Figure 4.12: Effects of hotplate bake temperature and time on the thickness of a Ti film measuredby AFM. A solvent clean was conducted prior to the measurement of the 6 minute bake samples.

Although the discontinuity rendered the data somewhat suspect quantitatively, we ap-

plied a linear fit to estimate the oxidation rate. An initial rapid, linear rate has been

observed for a number of metal films, before the rate turns to logarithmic behavior at later

times and larger thicknesses [126]. The linear rate corresponds to an oxidation process

that is limited by the reaction rate at the metal-oxide interface, while the logarithmic rate

describes a process limited by the diffusion of oxygen through the existing oxide. Fig. 4.13

is an Arrhenius plot of the rates, from which an activation energy Ea = 0.28 eV was de-

rived. This was markedly smaller than the value of Ea = 2.0 eV reported by Salomonsen

et al. [126], whose work involved thicker Ti films and higher temperatures.

Fig. 4.14 shows the effects of baking temperature and time on the normalized conduc-

tance of the Ti wires. After 10 minutes at 275 C, the conductivity dropped to a little

over 30% of its original value, demonstrating that heating strongly affected the conduction

through the wires, even with temperatures well below the 1000 K predicted by Avouris et al.

The normalized conductance, measured on a 4-probe Van der Pauw system, of two 4 nm

thick Ti film samples used in the second measurement is shown in Fig. 4.15. The hotplate

temperature was only 175 C, but a substantial change in the conductance, due to the thin

initial Ti film thickness, was evident.


-7.5

-7

-6.5

-6

-5.5

-5

1.8 1.9 2 2.1 2.2 2.3 2.4

1000/Temperature (1/K)

ln(O

xid

atio

n r

ate

(nm

/sec

)) Ea=0.28 eV

Figure 4.13: Estimate of activation energy Ea of Ti oxidation, from linear fits to AFM thicknessdata.

0

0.2

0.4

0.6

0.8

1

1.2

0 2 4 6 8 10

Time (min)

Norm

aliz

ed c

onduct

ance

T=150 °C

175 °C

200 °C

225 °C

250 °C

275 °C

Figure 4.14: Effects of hotplate bake temperature and time on the normalized conductance of a Tiwire 1 µm wide and 10 nm thick.


0

0.2

0.4

0.6

0.8

1

1.2

0 100 200 300 400 500

Time (sec)

Norm

aliz

ed c

onduct

ance

Figure 4.15: Effects of hotplate bake time on the normalized conductance of two 4 nm thick Ti films,as measured on a 4-probe Van der Pauw system. Hotplate temperature was 175 C.

We attributed the change in the conduction of both the wire and film samples to growth

of the insulating surface oxide, which thinned the remaining conductive Ti film. We initially

believed that the Ti films had the simple layer structure shown in Fig. 4.16. A native oxide

of stoichiometric TiO2 would form the top 1 nm, with a pure Ti layer beneath it. We

sought to use XPS analysis of the films before and after baking to measure the growth of

the oxide layer. The results, however, indicated that instead of well-defined metal and oxide

layers, the structure likely consisted of an O-rich Ti film covered by a gradual transition to

TiO2.

The first method used to determine the layer structure was ARXPS. The reduced area

fraction of each relevant element was measured with the detector at 30 and 90 from

the sample surface. The key values were the ratio R of the reduced area fractions at the

two detector angles, and the sum S of all reduced area fractions of elements in the same

layer. The data from a 6 nm thick Ti film sample prior to baking is shown in Table 4.1,

along with reference binding energies [127, 128]. The large reduced area fraction of C is

common, and represents surface contamination. The N may have been incorporated during

Ti film deposition. Two Ti species were clearly identified: Ti and TiO2. A third Ti peak


Figure 4.16: Schematic of expected layer structure for a nominally 6 nm thick film deposited onSiO2.

was suggested by curve fitting, and was located between the binding energies for TiO and

Ti2O3. The two O peaks have been associated with TiO2 and O bonded with C [128].

Table 4.1: ARXPS data from 6 nm Ti film prior to baking.

Element Binding Binding Reduced Area 30/90

Peak Energy Energy Fraction (atomic %) RatioMeas. (eV) Ref. (eV) 30 90

C 1s 284.6 285.0 40.58 26.34 1.54N 1s 396.4 398.4 3.30 5.07 0.65

Ti 2p3 454.4 453.9 1.01 2.48 0.41Ti 2p3 (TixOy) 456.7 n/a 1.27 2.79 0.46Ti 2p3 (TiO2) 458.9 458.7 7.54 8.77 0.86O 1s (TiO2) 530.5 530.3 27.03 34.54 0.78

O 1s (C) 531.9 532.3 19.27 20.02 0.96

A possible layer structure was developed from the assumption that elements with similar

R were likely to occupy the same layer. The first estimate of the layer structure consisted of

a top layer of C/O contamination, followed by a TiOx layer containing all of the measured

O 1s (TiO2), and then a combined Ti/TixOy/N layer. An average R and total S were

determined for each layer, and the results are shown in Fig. 4.17 as black circles. The

graphical analysis produced an estimated starting depth, thickness, and composition for

each layer. The amount of O 1s (TiO2) in the oxide layer is four times the amount of Ti


2p3 (TiO2), suggesting an oxide with a stoichiometry close to TiO4. An alternative was to

assume that the oxide layer contained only enough O to form TiO2, and that the rest of

the O was contained in a lower Ti/TixOy/N/O layer. The grey triangles in Fig. 4.17 show

the result.

0

1

2

0 20 40 60 80 100

S (atomic %)

R

thickness (nm)

depth (nm)

5.0

0.2

3.0

C/O layer

0.5

1.0

1.52.0

3.0

2.0

1.5

1.0

0.5

TiOx layerTiO2 layer

Ti/TixOy/N/O layerTi/TixOy/N layer

Figure 4.17: Graphical analysis of ARXPS data from 6 nm Ti film prior to baking. Black circlesassume all O in TiOx layer, leading to x ∼ 4. Grey triangles assume enough O to form TiO2, andthe rest of the O is incorporated in the lower Ti/TixOy/N/O layer.

Both analyses suggested structures different from the pure, abrupt layers of Fig. 4.16,

with substantial amounts of O likely present throughout the structure, and the presence of

multiple forms of Ti oxide. The layer structures derived from Fig. 4.17, however, were not

self-consistent, as there was a good deal of overlap between adjacent layers. The ARXPS

technique works best for well-defined layers, which likely does not describe our layer struc-

ture. Further difficulties resulted from uncertainty in the curve fitting of the relatively

small signals of Ti 2p3 and Ti 2p3 (TixOy). We were thus unable to use ARXPS to clearly

quantify changes in the structure from oxidation.

The second attempt to use XPS to characterize the layer structure and its changes

utilized ion etch depth profiling. Fig. 4.18 shows two high resolution scans of the Ti 2p1


and 2p3 peaks from two different etch steps. The black trace is from early in the process,

and is dominated by oxidized Ti, while the grey trace is from a later etch step, and shows

a mix of metallic and oxidized Ti species.

0

1000

2000

3000

4000

5000

6000

450455460465470

Binding Energy (eV)

Counts

Ti 2p3Ti 2p1

Ti (TiO2) 2p3

Ti (TiO2) 2p1

Figure 4.18: High resolution XPS scans of Ti 2p peaks measured close to the initial surface (black)and after etching (grey).

Compiling elemental data after multiple etch steps resulted in the XPS depth pro-

files shown in Fig. 4.19 of a control sample and a sample that had been baked at 200 C

for two minutes. For comparison, Fig. 4.20 is a simulation of the XPS depth profile

data for the ideal layer structure shown in Fig. 4.16. Both measured profiles are quite

different from the simulated ideal structure. Most importantly, the clear transition be-

tween the oxide and metal seen in the simulation was not observed in the measured pro-

files.

We had hoped to be able to observe the movement of the oxide-metal interface into the

metal film as a result of heating, but the absence of a clear, abrupt interface made this

impossible. The depth profiling did confirm, however, the strong presence of O throughout

the Ti film as suggested by the earlier angle resolved XPS measurements. The control

sample indicated that the “metal” layer initially consisted of as much as 40% TiO2. As

noted earlier in Section 3.5.1, large quantities of oxygen may have been incorporated during


deposition. In addition, we observed a small increase in the ratio of oxidized Ti to metallic

Ti in the metal film region as a result of hotplate baking.

Similar to the ARXPS results, the XPS ion etch depth profiling suggested the presence

of other stoichiometries of Ti oxide. For oxidation of Ti at higher temperatures, Ti2O3

and TiO have been found beneath the TiO2 layer [129]. Both Ti2O3 and TiO have XPS

peaks that lie between the much stronger metallic Ti and TiO2 peaks, however, and as with

the ARXPS results, uncertainties in the peak fitting process made it difficult to accurately

characterize the smaller curves.

In addition, the depth resolution of the XPS measurement suffered due to roughening

of the surface caused by uneven sputtering rates across the surface. AFM measurements of

the film surface prior to XPS showed an rms roughness of 0.3 nm, while measurements of

etched areas following XPS showed an increased rms roughness of 0.7 nm.

4.5.3 Discussion

An explanation of the mechanism behind CILO must describe how the oxidation rate in-

creases despite the presence of the Ti native oxide. The 1–2 nm thick Ti native oxide forms

quickly upon the Ti film’s first exposure to air. Diffusion of oxygen through the oxide to

the oxide-metal interface is the rate-limiting step, and the oxide continues to grow until

its thickness reduces the oxidation rate to nominally zero. As described earlier, Avouris

et al. claimed that electromigration opens up cracks along grain boundaries in the Ti film,

enhancing the diffusion of oxygen through the Ti. Yet the rate-limiting step should be

diffusion of oxygen through the oxide layer, not the metal film. Thus, local temperature

change caused by Joule heating appears to be the best explanation for the enhanced diffu-

sion of oxygen through the oxide, and hence, for CILO. The changes in conductance and

composition observed in the Ti films in our hotplate heating in air experiments point to the

strong role played by heating in the CILO process.

To estimate the amount of heating created by the CILO current, we employed the

simplified 2-dimensional Bilotti’s equation [130]:

∆T =I2ρtox

koxwh(w + 0.88tox)(4.4)

which predicts the temperature change for a given current I, in a wire with resistivity ρ,

width w, and height h, on an oxide layer with thickness tox and thermal conductivity kox.


0

10

20

30

40

50

60

0 5 10 15

Etch Step

Ato

mic

per

cent

Ti

Ti (TiO2)

O (TiO2)

O (SiO2)

(a) Control sample: no baking (Si not scanned for).

0

10

20

30

40

50

60

0 5 10 15 20

Etch Step

Ato

mic

per

cent

TiTi (TiO2)

O (TiO2)

O (SiO2)

Si

(b) Baked at 200 C for 2 minutes.

Figure 4.19: XPS ion etching depth profiles of a Ti film baked on a hotplate, and a control sample.


0

20

40

60

80

100

0 1 2 3 4 5 6

Depth (nm)

Ato

mic

per

cent

Ti

O (SiO2)

SiO (TiO2)

Ti (TiO2)

Figure 4.20: Simulation of the XPS depth profile data for a structure consisting of 1 nm of TiO2,5 nm of Ti, and a SiO2 substrate.

Using the appropriate values for our Ti film, SiO2 layer and CILO current, however, (4.4)

predicts ∆T ∼ 3 K, which is considerably smaller than the approximately 700 K increase

predicted by Avouris et al.

The sensitivity of the Ti films to the effects of heating also placed limits on the processing

conditions. Our fabrication process routinely employed a singe at 150 C prior to the

deposition of resist, exposing the Ti film to elevated temperatures twice. This extra heating

and oxidation likely increased the thickness of the oxide layer beyond what we expected for

the native oxide thickness, and reduced the thickness of the metallic Ti layer.

4.6 Improved Device Resistance Model

Attempts to correlate the AFM-measured oxide height above the film surface with the

change in electrical resistance during CILO resulted in a marked discrepancy. We attempted

to improve the correlation by including a more accurate value for the native oxide thickness,

the possible presence of multiple stoichiometries of Ti oxide, and the effects of surface

scattering.


4.6.1 Procedure

CILO was performed on two sets of samples, both defined with electron beam lithography,

and with Ti film thicknesses of 6.5 and 10 nm. The applied voltage and resulting current, as

well as the voltage between two inner probes, were monitored with an HP4156 semiconductor

parameter analyzer. The conductance between the inner probes was displayed in real-time.

CILO was automatically halted after drops of 15–250 µS in the conductance were observed.

The height of the oxide barrier was measured with AFM, from surface profiles taken across

the center of the barrier.

4.6.2 Results

Fig. 4.21a shows an AFM image of a device with a partial oxide barrier. The dotted

line indicates the position of the surface profile of Fig. 4.21b. The barrier height of this

particular sample was 1.8 nm. The height of the oxide barrier was not always uniform

across its length, but the height was measured at the center of the barrier for consistency

between devices.

The change in the resistance measured between the beginning and end of the partial

CILO process was used to estimate the height of the oxide barrier above the surface. As

described previously in (4.1), the change in resistance was assumed to be due entirely to a

decrease in the thickness of metallic Ti as the oxide grew down into the film. The initial

metallic Ti thickness was determined by subtracting an assumed 1 nm native oxide from

the AFM-measured film thickness. Together with the initial resistance and AFM-measured

dimensions, a resistivity was calculated. The final metallic Ti thickness was then determined

from the final measured resistance. The density of TiO2 is approximately double that of Ti,

so the final oxide barrier height was estimated by assuming it to be equal to the thickness

of the consumed Ti. A comparison of the heights measured by AFM with the heights

calculated from the change in resistance is shown in Fig. 4.22.

4.6.3 Discussion

The poor correlation between the AFM-measured oxide barrier heights and the calculated

heights indicated that improvements to the model were necessary. Correlation was improved

by using different values for the native oxide thickness and Ti oxide density, and the inclusion

of a film thickness-dependent resistivity.


(a) AFM image of partially oxidized CILO barrier. Dottedline shows the location of the surface profile measurement.

6

6.5

7

7.5

8

8.5

0 100 200 300 400

Position (nm)

Hei

ght

(nm

)

(b) Surface profile measurement of CILO barrier, indicating height ofapproximately 1.8 nm.

Figure 4.21: AFM measurement of partial CILO oxide barrier.


0

2

4

6

8

10

0 1 2 3 4 5

Oxide Height Measured by AFM (nm)

Oxid

e H

eight

Cal

cula

ted f

rom

Ele

ctri

cal

Res

ista

nce

(nm

)

Figure 4.22: Initial attempt to correlate oxide barrier height measured by AFM with height estimatedfrom the change in resistance. The line corresponds to the desired 1:1 ratio.

As we were unable to directly measure the thickness of the native oxide layer of our Ti

films, we initially assumed a value of 1 nm as suggested by Matsumoto [83]. The work of

Lehoczky et al. [131], however, lead us to adopt a value of 2.6 nm. The larger value may

have better described our samples due to their long exposure to air and the incorporation

of a high concentration of oxygen during film deposition.

A given volume of Ti almost doubles in size on becoming TiO2, so we assumed that the

depth of the oxide below the film surface was roughly equal to the measured height of the

oxide above the surface. As noted earlier, Evans [129] found the presence of both TiO and

Ti2O3 on Ti films. The molecular weights and densities of the different oxide stoichiometries

is shown in Table 4.2 [132]. The last column shows the ratios of the calculated unit cell

volumes of the Ti oxides to bulk Ti. Due to our inability to measure the precise composition

of the native oxide, we were unable to determine a specific volume ratio. Comparison of

our own data with that of Lehoczky et al. [131] however, resulted in a choice of 1.6. This

value suggested that the native oxide was a combination of multiple oxide stoichiometries

weighted towards TiO.

The final improvement to the modeling came from the inclusion of surface scattering

in determining the film resistance. When the film thickness becomes comparable to the


Table 4.2: Ti and Ti oxide volumes

Material Mol. wt. Density Unit cell vol. Ratio with Ti(g/cm3) (10−29m3)

Ti 47.867 4.506 1.76 1.0TiO 63.866 4.95 2.14 1.2Ti2O3 143.732 4.486 5.32 3.0TiO2 (rutile) 79.866 4.26 3.11 1.8TiO2 (anatase) 79.866 3.84 3.45 2.0TiO2 (brookite) 79.866 4.17 3.18 1.8

electron mean free path, the scattering of electrons from surfaces and interfaces becomes

comparable to the bulk scattering. The Fuchs-Sondheimer equation describes the increasing

role of surface scattering as film thickness decreases:

ρfilmρbulk

=φp(γ)γ

(4.5)

where1

φp(γ)=

1γ− 3(1− p)

2γ2

∫ ∞1

(1a3− 1a5

)1− exp(−γa)

1− p exp(−2γa)da (4.6)

and γ = t/λ, t is the film thickness, λ is the mean free path, and p is a value from 0 to

1 that describes the specularity of the reflection. A numerical solution to the equation is

plotted in Fig. 4.23. For the specularity parameter, a value of p = 0.2 was used, following

the results of Lehoczky et al. [131].

The electron mean free path in our film was not measured, and the value of λ = 12.6

found by Lehoczky et al. [131] for similar films was used. This value is in the neighborhood of

the values determined by Day et al. (15–18 nm) [110] and Singh and Surplice (28 nm) [111].

The comparatively low value of Lehoczky et al. may be attributable to a higher oxygen

content, as their Ti films were deposited at both a lower rate and a higher background

pressure than those of Day et al. and Singh and Surplice. Our deposition rates and pressures

were similar to those of Lehoczky et al.

As noted in Chapter 3, Mayadas and Shatzkes described the contribution of grain bound-

ary scattering to the resistance [108]. Day et al. noted that rapid oxidation along grain

boundaries during the native oxidation of thin films lead to a saturation of grain boundary

scattering [110]. We therefore assumed that grain boundary scattering would contribute a


1

2

3

4

0 0.5 1 1.5 2 2.5

! (t/")

#fi

lm/ #

bulk

Figure 4.23: Fuchs-Sondheimer equation describes how the thin film resistivity increases as the filmthickness decreases to a value comparable to the electron mean free path.

constant amount that would not change as the film continued to oxidize and its dimensions

were reduced.

The Fuchs-Sondheimer contribution to the thin film resistivity was incorporated into the

CILO current model. From the resistance value at the beginning of the CILO process, we

used the Lehoczky value of native oxide thickness with the AFM-measured film thickness

and constriction dimensions to determine a film resistivity. Equation (4.5) was used to find

a value for the bulk resistivity. The bulk resistivity was then used to iteratively calculate

a new film resistivity and thickness from the measured resistance at the end of the CILO

process. Finally, the new oxide volume ratio was used to calculate the expected oxide barrier

height. The result was an improved correlation between the measured oxide barrier height

and the calculated value, as shown in Fig. 4.24.

Although questions remained about the precise physical mechanisms driving CILO,

we felt that we had achieved sufficient control and understanding to employ CILO for the

fabrication of SETs. I describe our device fabrication and testing efforts in the next chapter.


0

1

2

3

4

5

0 1 2 3 4 5

Oxide Height Measured by AFM (nm)

Oxid

e H

eight

Cal

cula

ted f

rom

Ele

ctri

cal

Res

ista

nce

(nm

)

Figure 4.24: Improved correlation between oxide barrier height measured by AFM with heightestimated from the change in resistance. The line corresponds to the desired 1:1 ratio.

Chapter 5

SET Fabrication and Measurement

This chapter describes our single electron tunneling device and its fabrication. The novel

fabrication method we developed takes advantage of aspects of self-assembly, self-alignment,

and self-limitation to achieve nanometer-scale features through the use of relatively simple

processes. Low temperature measurements of the device conducted in a cryostat probe

station and a liquid helium (He) dewar demonstrated behavior consistent with Coulomb

blockade.

5.1 Introduction

Although the CILO oxides demonstrated improved reproducibility over the AFM oxides,

we were still unable to fabricate barriers thin enough for SETs. By combining CILO with

self-assembled Au islands, however, we found a way to achieve sufficiently small device

dimensions without adding undue complexity to the fabrication.

Vullers et al. [133] suffered similar difficulties to ours in their work using the AFM to

fabricate thin, lateral oxide barriers. To get around this limitation, they used the AFM to

locally oxidize a thin Ti film surrounding a self-assembled Au island. Rather than defining

a conductive Ti island with several oxide barriers, they used the Au island as the heart

of their SET. In so doing, the limiting oxide barrier thickness was reduced from the total

barrier thickness to the distance between the island and the edge of the barrier, as shown in

Fig. 5.1. The AFM oxide thickness d1 simply determines the separation between the source

and drain leads, and d2 may be thin enough to allow tunneling between the island and the

leads.

87

CHAPTER 5. SET FABRICATION AND MEASUREMENT 88

Figure 5.1: The use of Au islands reduced the tunneling distance through the oxide barrier from d1

to d2, relaxing the fabrication requirements.

We adapted this idea into our CILO-based process, taking advantage of the self-aligned

way that the CILO oxide naturally formed in the pre-patterned constriction in the Ti wire.

By using self-assembled Au islands, we mostly avoided the use of high-resolution lithography

for our key features. The self-limiting nature of CILO eliminated the need for tight control

over the oxide barrier fabrication parameters. With this process, we successfully fabricated

disordered arrays of self-assembled Au islands that demonstrated behavior consistent with

Coulomb blockade in low temperature measurements. We have thus established key steps

towards developing a simple, economical fabrication process for SETs.

5.2 Fabrication

An overview of the fabrication process is shown in Fig. 5.2. Electron beam lithography

was employed to define 1 µm wide lines with a single, central constriction approximately

100 nm wide. In an electron beam evaporator, deposition of islands of Au was followed

immediately by deposition of a continuous layer of Ti. Metal liftoff then produced the basic

device structure. Contact pads were defined using a standard process involving optical

lithography, electron beam evaporation, and liftoff. Finally, CILO was used to create an

oxide barrier in the central constriction region.

5.2.1 Electron Beam Lithography

The electron beam lithography masks were designed using L-Edit [134]. The initial lithog-

raphy work was conducted on a Hitachi H-700F electron beam lithography system, using

positive resists ZEP520 and poly(methyl methacrylate) (PMMA). With this system, we


Figure 5.2: Overview of the SET fabrication process.

were unable to consistently achieve a sufficient level of control over a key device dimension,

the width of the central constriction. The primary challenge appeared to be proximity ef-

fects, where electrons from exposed areas scattered into adjacent regions. The edges of the

constriction were defined by pixels that needed to remain unexposed, but received doses

from the exposed pixels that surrounded them on multiple sides. Several different prox-

imity correction schemes [135, 136] were attempted with CAPROX proximity correction

software [123]. In addition, diagonal mask features were replaced by horizontal and vertical

approximations to simplify the structure. Although improvements were observed, they did

not provide sufficient control and reproducibility.

Successful electron beam lithography was ultimately completed through a collabora-

tion with the Inter-University Semiconductor Research Center of Seoul National University.

This placed limits, however, on the number of available samples and the ability to make

modifications to the mask design.


5.2.2 Au Island Deposition

The Au islands were deposited with an Innotec ES26C electron-beam evaporation system.

Typical chamber pressures prior to deposition were in the low 10−7 Torr range, and deposi-

tion rates were ∼0.01 nm/sec, the lower limit of the rate display. Less than 1 nm of Au was

deposited, as measured by the crystal film thickness monitor. The Au films appeared to

follow the Volmer-Weber growth mode, in which the bonds between Au atoms are stronger

than the bonds between Au and the SiO2 substrate, leading to the formation of islands [137].

The reproducibility of the amount of Au deposited was limited by the response time and

speed of the shutter over the source, which was opened and closed manually. We did not at-

tempt to optimize the deposition conditions for island size or density, but similar processes

have been studied by Boero et al. [138].

Fig. 5.3 is an AFM image of Au islands on SiO2 with a deposited thickness of 0.4 nm

as measured by the crystal film thickness monitor. Analysis of the image with Image

SXM [139] resulted in a count of 336 islands, a figure which was verified by a manual count

of 346 islands. Fig. 5.4 is a histogram of island diameters, showing a broad distribution of

island sizes below 12 nm. The actual island size may be underestimated in this histogram,

as the automated counting process required setting a minimum elevation in order to clearly

separate distinct islands. For reliable device production, much tighter control of the island

size will be required.

The wide distribution of island sizes made it difficult to accurately estimate the single

electron charging energy. Using the known deposited volume, and a 7 nm average diameter,

the average island height was found to be ∼2 nm, assuming a pillbox shape. The edge-to-

edge separation between islands was calculated to be 7 nm. An estimate of the capacitance

between islands, and the capacitance between an island and the back gate, was made using

the approximations of Wasshuber [140] for the capacitance between two spheres and the

capacitance between a sphere and a plane, respectively. A rough correction was imposed

by reducing the capacitances by the ratio of the surface areas of the island’s pillbox shape

to a sphere.

With these approximations, the island-island junction capacitance was estimated as

Cj = 0.37 aF, and the island-gate capacitance Cg = 1.2 aF. To estimate the charging energy

and maximum operating temperature, we assumed that the islands took on a hexagonal

close-packed array structure, with each island having six nearest neighbors. The 2D array

theory of Bakhvalov et al. estimates that for Cg/Cj = 3, an island in the interior of a


Figure 5.3: AFM image of Au islands evaporated on SiO2.

0 5 10 15 20Diameter (nm)

0

10

20

30

40

Cou

nt

Figure 5.4: Histogram of diameters of Au islands evaporated on SiO2.


rectangular array with four nearest neighbors has a capacitance CΣ,4 = 5.3Cj [53]. Analysis

of the 4 × 5 triangular array described in Chapter 2, however, indicated that islands with

six nearest neighbors and Cg/Cj = 3 would have a slightly larger capacitance CΣ,6 = 7.9Cj .

This expression leads to CΣ,6 = 2.92 aF for our Au islands, which corresponds to a charging

energy Ec = 27.4 meV. An operating temperature of T = 159 K would lead to a thermal

energy of half that value, and provide a safety margin for operation. Measurements of the

devices, however, required a much lower temperature for Coulomb blockade effects to be

apparent, indicating that the device capacitances were larger than the above figures.

5.2.3 Ti Film Deposition

Ti was deposited at vacuum pressures in the high 10−8 to low 10−7 Torr range at a rate

of 0.1–0.2 nm/sec. It may have been possible to lower the impurity concentration by using

higher deposition rates. However, we were concerned that increasing the electron beam

power would increase the chamber and sample temperatures, and more impurities might be

introduced by outgassing from heated chamber surfaces.

A simple trick was employed in order to reduce the starting chamber pressure. The

samples were initially loaded in the chamber such that the crystal monitor support column

stood between the samples and the Ti source. The Ti source was brought up to deposition

temperature in the normal way, with the shutter closed. Upon reaching the desired power,

the shutter was opened, and Ti was deposited on the chamber walls as the chamber pressure

and deposition rate were measured. After ∼30 seconds, the planetary rotation of the sample

holders was started, bringing the sample out from the “shadow” of the support column. This

enabled us to reduce the chamber pressure by about a factor of two prior to deposition.

5.2.4 Liftoff and Cleaning

The first step in the liftoff of the Au islands and Ti film was an overnight soak in acetone or

Shipley 1165 photoresist remover. The Shipley resist stripper appeared to be more effective

at removing photoresist, but also tended to leave a residue behind. A 5 minute soak in

a beaker of acetone, in an ultrasonic bath, followed by rinses in methanol and isopropyl

alcohol, were generally sufficient to complete the liftoff.

Subsequent AFM imaging occasionally showed residue on the sample surface. In these

cases, or for particularly stubborn liftoff, we used a stronger cleaning process. The first step


was a gentle scrub with a cotton swab while the sample was immersed in acetone. This was

followed by 5 minutes in boiling acetone, and then 5 minutes each in acetone, methanol,

and isopropyl alcohol in a heated ultrasonic bath.

5.2.5 Contact Pads

The 150 × 150 µm2 contact pads were defined with optical lithography on a Karl Suss

MA-6 contact aligner. The large feature sizes allowed us to use inexpensive transparency

masks printed at 3600 dpi on mylar sheets by MediaMorphosis (Mountain View, Calif.),

and standard recipe photolithography with Shipley 3612 photoresist. In the Innotec electron

beam evaporator, we deposited ∼10 nm of Ti and ∼100 nm of Au. Liftoff was performed

in acetone, in an ultrasonic bath, followed by rinses in methanol and isopropyl alcohol.

Finally, a backside Ti/Au contact was deposited onto the entire back surface of the sample

with the Innotec evaporator.

5.2.6 CILO

CILO was conducted as described in Chapter 4, and Fig. 5.5 is an AFM image of the central

area of a completed device. Although covered by the Ti film, the shape of the Au islands

remained apparent, and it was clear that there were many islands contained in the Ti oxide

barrier.

5.3 Low Temperature Probe Station Measurement

Electrical measurements of the devices were made at low temperature, where Coulomb

blockade effects are more readily apparent. The goals were to observe evidence of Coulomb

blockade, demonstrate the role of the Au islands, and estimate key parameters.

5.3.1 Procedure

Four devices with different characteristics were fabricated: two had Au islands, two did

not; two had thicker barriers and higher resistance, two had thinner barriers and lower

resistance. The CILO for all four devices was performed in multiple steps, reducing the

conductance by 20 × 10−6 Ω−1 each time. The high-resistance devices with and without


Figure 5.5: AFM image of central area of completed device. A CILO-generated TiOx barrier isolatesAu islands from adjacent Ti leads.

Au islands had room temperature resistances of 525 kΩ and 884 kΩ, respectively, and the

low-resistance devices measured 34 kΩ and 12 kΩ, respectively.

The measurements were performed in a He-cooled probe station. The sample was

mounted to a stage with silver paint, and the stage was secured with screws in the cryostat

chamber. Following evacuation of the chamber, gaseous He was introduced to cool the sam-

ple. The use of gaseous He under pressure made chamber temperatures below 4.2 K possible.

A schematic of the two-terminal measurement system is shown in Fig. 5.6. The drain-

source bias was provided by a DC voltage source and an AC lock-in. The drain-source

current passed through an Ithaco I/V amplifier, whose output voltage was fed into the AC

lock-in. The amplitude of the measured AC signal at the lock-in frequency was output

as a DC voltage, read by a Keithley digital multimeter. A MATLAB [141] script running

on a personal computer controlled the DC voltage source and read the output from the

multimeter. The DC drain-source bias magnitude ranged from 10 mV to 0.5 V. The lock-in

provided a small-signal AC bias of 2.5 mV at a frequency of 145 Hz. The back gate and

sample stage were grounded.


Figure 5.6: Schematic diagram of low temperature probe station measurement apparatus.

5.3.2 Results and Discussion

The differential drain-source conductances as a function of drain-source voltage were mea-

sured for each device over a range of temperatures, and are shown in Figs. 5.7–5.10. For the

devices containing Au islands, the high resistance device was measured at T = 1, 2, 2.5, 3,

3.5, 5, 7.5, 10, 17, 30, and 70 K, and the low resistance device was measured at T = 1, 15,

30, 50, and 70 K. For the devices without Au islands, the high resistance device was mea-

sured at T = 10, 15, and 30 K, and the low resistance device was measured at T = 1, 5, 10,

30, and 70 K. Devices both with and without Au islands demonstrated a low drain-source

conductance region at low drain-source bias, consistent with Coulomb blockade, indicating

that the Au islands did not play a key role.

Direct analysis of the conductance of the low resistance device without Au islands at

T = 70 K was possible with Coulomb blockade thermometry, which requires relatively high

temperatures and a broad voltage sweep. Fig. 5.11 shows the measurement of the depth and

full width at half minimum of the conductance dip, which lead to estimates of the charging

energy Ec = 4.8 meV, and number of islands in the current path N = 4.6. The black line

in Fig. 5.11 used these values for Ec and N in (2.30), the analytical expression for the array

conductance, and demonstrates the accuracy of the fit. The derived Ec was about six times

smaller and N about 1.5 times smaller than predicted from the earlier AFM measurements

of the Au island size.

Further analysis of the current behavior required integration of the measured differential

conductance. The minimum measured conductance varied between devices, with one device

even demonstrating negative conductance at low bias. This suggested that the accuracy of


0

2

4

6

8

10

-150 -100 -50 0 50 100 150


Dra

in-S

ourc

e dI/dV

(1/G!

)

T=70 K

T=1-17 K

T=30 K

Figure 5.7: Differential conductance through a high-resistance device with Au islands measured atT = 1, 2, 2.5, 3, 3.5, 5, 7.5, 10, 17, 30, and 70 K.

0

2

4

6

8

10

-0.6 -0.4 -0.2 0 0.2 0.4 0.6


Dra

in-S

ourc

e dI/dV

(1/M!

)

T=1 K

T=70 K

T=30 K

T=15 K

T=50 K

Figure 5.8: Differential conductance through a low-resistance device with Au islands measured atT = 1, 15, 30, 50, and 70 K.


-20

0

20

40

60

80

-1 -0.5 0 0.5 1


Dra

in-S

ourc

e dI/dV

(1/G!

)

T=10 K

T=30 K

T=15 K

Figure 5.9: Differential conductance through a high-resistance device without Au islands measuredat T = 10, 15, and 30 K.

0

1

2

3

4

-0.15 -0.1 -0.05 0 0.05 0.1 0.15


Dra

in-S

ourc

e dI/dV

(1/G!

)

T=1, 5, 10 K

T=70 K

T=30 K

Figure 5.10: Differential conductance through a low-resistance device without Au islands measuredat T = 1, 5, 10, 30, and 70 K.


0.7

0.8

0.9

1

-150 -100 -50 0 50 100 150


G/G

T

!G

V1/2

Figure 5.11: Coulomb blockade thermometry analysis of a low-resistance device without Au islands.The measured ∆G and V1/2 lead to Ec = 4.8 meV and N = 4.6. The black line uses the twoparameters to fit to an analytical expression for the current at T = 70 K.

the measurements may have been limited by leakage current. The integrated differential

conductance of the high-resistance device with Au islands is shown in Fig. 5.12. The slope

in the central area and smooth turn-on behavior may be due to leakage current providing

an offset in the small-signal conductance. In order to apply much of the Coulomb blockade

array theory described in Chapter 2, it was necessary to identify a threshold voltage for the

drain-source current. Even at low temperatures, however, the apparent smooth turn-on of

the current made it difficult to identify a clear threshold voltage.

We explored the possibility that the mechanism governing the current was something

other than Coulomb blockade. Four other explanations exist for nonlinear current through

insulators: Schottky emission, Frenkel-Poole emission, Fowler-Nordheim tunneling, and

space-charge-limited current [105].

In Schottky emission, electrons with sufficient thermal energy can overcome an insulating

barrier whose height is lowered by the application of an electric field. The voltage and

temperature dependence of Schottky emission current are given by [105]:

I ∼ T 2 exp

[a

√V

T− qφB

kT

](5.1)


-0.3

-0.2

-0.1

0

0.1

0.2

0.3

-150 -100 -50 0 50 100 150


Dra

in-S

ourc

e C

urr

ent

(nA

)

T=1 K

T=70 K

Figure 5.12: Current through a high-resistance device with Au islands from integrated differentialconductance. T = 1, 2, 2.5, 3, 3.5, 5, 7.5, 10, 17, 30, and 70 K.

Fig. 5.13 attempts to fit the currents from Fig. 5.12 to Schottky emission behavior by

plotting ln(IDS/T 2) versus 1/T for several values of VDS . Schottky emission should produce

straight lines with negative slopes, which does not describe the behavior of the experimental

data.

Frenkel-Poole emission involves the capture and emission of trapped charge within the

insulator as the mechanism governing the current. The voltage and temperature depen-

dences of Frenkel-Poole emission are given by [105]:

I ∼ V exp

[2a√V

T− qφB

kT

](5.2)

Fig. 5.14 shows a plot of ln(IDS/VDS) versus 1/T . Frenkel-Poole emission should produce

straight lines with negative slopes, which is not the case here. The plot does show, however,

that IDS/VDS is relatively constant below T = 10 K, even for low VDS . In Chapter 2, it was

noted that below threshold, the current through an island array is thermally activated. The

current for VDS = 20 mV was initially believed to be below threshold, which is inconsistent

with the temperature-independence we observed.


-34

-32

-30

-28

-26

-24

-22

-20

0 0.2 0.4 0.6 0.8 1

1/Temperature (1/K)

ln(I

DS/T

2)

VDS=10 mV

VDS=120 mV

Figure 5.13: Current through high-resistance device with Au islands from integrated differentialconductance does not conform to Schottky emission behavior, which should appear as straight lineswith negative slopes. VDS = 10, 20, 50, 80, 120 mV.

We noted that the thermocouple used to measure the temperature contacted the sample

stage, and not the sample itself. Thus, the thermocouple may not have reflected the actual

temperature of the device, and the device itself may not have been cooled below T = 10 K.

The cryostat incorporated a window to facilitate manipulation of its probes on the sample.

Although an opaque cover blocked light during measurement, blackbody radiation from the

room temperature cover may have provided a source of heat to the sample.

Space-charge limits the current when a carrier density gradient increases to the point

that an electric field develops that opposes the direction of the current. The current is

proportional to V 2, and the curvature of the lines in Fig. 5.15 demonstrates that this does

not describe the behavior of the measured data.

Although we expected electrons to tunnel between our conductive islands, tunneling

current should not be the limiting factor. Fig. 5.14 showed that the current below T =

10 K was relatively independent of temperature, which is consistent with tunneling current.

Simmons derived a formula for the tunneling current at low voltages [142]:

I = Θ(V + γV 3) (5.3)


-22

-21

-20

-19

-18

-17

0 0.2 0.4 0.6 0.8 1

1/Temperature (1/K)

ln(I

DS/V

DS)

VDS=20 mV

VDS=120 mV

Figure 5.14: Current through high-resistance device with Au islands from integrated differentialconductance does not conform to Frenkel-Poole emission behavior. VDS = 20, 50, 80, 120 mV.

0

0.1

0.2

0.3

0.4

0.5

0.6

0 0.005 0.01 0.015 0.02

VDS2 (V

2)

Dra

in-S

ourc

e C

urr

ent

(A)

T=2 K

T=70 K

Figure 5.15: Current through high-resistance device with Au islands from integrated differentialconductance does not conform to space-charge limited current behavior. T = 2, 5, 10, 30, 70 K.


A fit of the differential conductance at T = 2 and 10 K to the derivative of the Simmons

formula is shown in Fig. 5.16, where different fit values were used for positive and negative

drain-source voltage. The fit was not particularly close, and the fitting parameters for

currents at T = 2 and 10 K differed by as much as 50%.

0

1

2

3

-100 -50 0 50 100


dI

DS/dV

DS (

1/ !

)

T=10 K

T=2 K

Figure 5.16: Differential conductance through high-resistance device with Au islands shows poor fitto low voltage tunneling behavior. T=2 and 10 K.

For applied voltages greater than the barrier height, the Fowler-Nordheim expression

accounts for the increasingly thin triangular shape of the barrier as the voltage is in-

creased [105]:

I ∼ V 2 exp(−a/V ) (5.4)

A fit of the experimental data to Fowler-Nordheim tunneling is shown in Fig. 5.17 for

voltages greater than the 0.1 V oxide barrier height measured in Chapter 4. The behavior

of the experimental current appeared to be somewhat consistent with Fowler-Nordheim

behavior. However, we would expect currents above the array threshold voltage to be

governed by tunneling, and it was possible that the array threshold voltage was less than

0.1 V.

We have demonstrated that the nonlinear behavior of the drain-source current through


-18.4

-18.2

-18

-17.8

7.5 8 8.5 9 9.5 10

1/VDS (1/V)

ln(I

DS/V

DS

2)

T=10 K

T=5 K

T=2 K

Figure 5.17: Current through high-resistance device with Au islands from integrated differentialconductance appears similar to Fowler-Nordheim tunneling current. T = 2, 5, 10 K.

the arrays was consistent with Coulomb blockade, and was not consistent with other expla-

nations for the current. The analysis was complicated, however, by a possible offset in the

minimum differential conductance, which influenced the current obtained from integrating

the conductance. The key result, however, was that the Au islands did not appear to have

played the desired role, as Coulomb blockade features were observed in devices without Au

islands.

One possible explanation for the existence of Coulomb blockade without Au islands is

that crystals of Ti remained unoxidized within the CILO oxide barrier, and oxidized grain

boundaries served as tunneling barriers between grains. Tan et al. demonstrated Coulomb

blockade using nanocrystalline grains of Si in this way [143]. They oxidized and annealed

a nanocrystalline Si film containing grains about 8 nm across. Oxidation occurred along

grain boundaries, and the oxidized grain boundaries acted as tunneling barriers. With these

devices, they demonstrated Coulomb blockade oscillations at room temperature.

It is possible that CILO oxidized the Ti films preferentially along Ti grain boundaries,

isolating Ti crystal grains inside Ti oxide. Fig. 3.14 showed that the deposited Ti grains

were smaller than 10 nm across, making them similar in size to the Au islands.


5.4 Liquid Helium Dewar Measurement

Measurements were made inside a liquid He dewar with different equipment to address

some of the limitations of the previous experiment. Immersion in liquid He ensured that

the device was cooled below T=10 K. Direct measurement of the drain-source current

allowed for Coulomb blockade array analysis. Modulation of the drain-source current by

the gate voltage provided further evidence of Coulomb blockade.

5.4.1 Procedure

Similar to the previous experiment, four devices were fabricated: two with Au islands

and two without. Oxide barriers in all four devices were created with multiple, partial

CILO steps. All four devices were measured to have room temperature resistances ∼1 MΩ

immediately after CILO, but the resistances of three devices dropped sharply following wire-

bonding. The samples were wire-bonded to 32-pin, non-magnetic, leadless chip carriers, with

one pin bonded to the backside contact. Due to the devices’ expected sensitivity to higher

temperatures, the conductive epoxy securing the sample to the carrier was baked at a lower

temperature and for a longer time than the standard recipe. Nonetheless, the wire-bonding

appeared to have affected three of the devices, whose room temperature resistance fell to

as low as 26 kΩ.

To insert the devices inside a liquid He dewar, we constructed a dunk stick from a thick-

walled stainless steel tube. A terminal box at the top contained four triaxial connections

for use with the HP4155 SMU cables and four coaxial connections for the VMU cables. The

outer shields of the triaxial and coaxial cables were grounded to the terminal box. The inner

shield of the triaxial cable was left unconnected at the terminal box. 30 awg magnet wire

ran down the length of the tube, connecting the terminal box to the socket at the bottom

of the dunk stick. The chip carriers were secured face-down in a spring-loaded Plastronics

plastic socket.

For the first set of runs, the backside gate was grounded, and two devices could be

measured without rewiring. For later measurements, the backside gate was connected to

one of the SMU terminals and only one device could be measured at a time.

Drain voltage sweeps were performed as double sweeps up to a set drain-source bias and

then back down, followed by a similar double sweep to and from a set negative voltage.

Initially, we conducted four-probe measurements, with the SMUs sourcing drain-source


voltage, and the VMUs measuring voltage in differential mode from contacts closer to the

center of the device. We soon noticed, however, that the measured currents appeared to

be offset by ∼50 pA. The input resistance of the HP4155 VMU probes is rated as greater

than 1 GΩ. Although this was acceptable for room temperature measurements, the low

temperature resistance of the devices was ∼1011 Ω. Further measurements were made with

only two SMUs and the VMUs were disconnected.

We also performed gate voltage sweeps while measuring the drain-source current. Seek-

ing to observe gate modulation of the drain-source current, the drain-source biases were kept

small in order to remain below the array threshold voltage. The resulting currents, however,

were on the order of nanoamps, with features on the order of picoamps. To minimize the

effect of noise, it was necessary to average multiple sweeps. HP VEE software [144] was used

to control the HP4155 and automate the measurement. Multiple gate voltage sweeps with

100 mV steps were made at a set drain voltage. The drain voltage was then incremented

by 1–2 mV, and after a 30 second pause, another set of gate voltage sweeps was conducted.

5.4.2 Results and Discussion

The results of the drain voltage sweep measurements are shown in Figs. 5.18–5.21. Much

like the earlier measurements made in the cryostat probe station, high-resistance regions

at low bias were observed for all four devices. A small (< 0.2 pA) offset was observed

at zero bias, with a slightly greater value for sweeps made in the negative direction. In

our analysis, we accounted for this offset by subtracting from the current the average of

a few points around zero bias. Within a certain voltage range around VDS = 0 V, the

current could be fit by a line with a slope corresponding to a resistance of order 1011 Ω.

The measured currents in this region were very near the HP4155’s minimum resolution of

10 fA.

We attempted to fit the measured currents to low and high-voltage tunneling behavior,

as was done for the previous measurements. Using 0.1 V as the divider between the low

and high voltage regions, the low voltage behavior was a poor fit, but the high voltage

behavior was reasonably consistent with tunneling. Reducing the division point to 60 mV

improved the low voltage tunneling fit slightly, but made the high voltage fit worse. Hence,

we concluded that the behavior of the current could not be explained by tunneling alone.

As measurements inside the liquid He dewar were only conducted at a single temperature,

we were unable to use temperature dependence to rule out other possible mechanisms.


-6

-4

-2

0

2

4

6

-0.3 -0.2 -0.1 0 0.1 0.2 0.3


Dra

in-S

ourc

e C

urr

ent

(nA

)

Figure 5.18: Current through a high-resistance device with Au islands, measured inside a liquidhelium dewar. T = 4.2 K.

-4

-2

0

2

4

-0.2 -0.1 0 0.1 0.2


Dra

in-S

ourc

e C

urr

ent

(nA

)

Figure 5.19: Current through a low-resistance device with Au islands, measured inside a liquidhelium dewar. T = 4.2 K.


-0.6

-0.4

-0.2

0

0.2

0.4

0.6

-0.3 -0.2 -0.1 0 0.1 0.2 0.3


Dra

in-S

ourc

e C

urr

ent

(nA

)

Figure 5.20: Current through a high-resistance device without Au islands, measured inside a liquidhelium dewar. T = 4.2 K.

-8

-6

-4

-2

0

2

4

6

8

-0.2 -0.1 0 0.1 0.2


Dra

in-S

ourc

e C

urr

ent

(nA

)

Figure 5.21: Current through a low-resistance device without Au islands, measured inside a liquidhelium dewar. T = 4.2 K.


We analyzed the drain-source current using the methods of Middleton and Wingreen,

as described in Chapter 2. We chose an arbitrary value of 0.1 pA as the minimum current

to determine the threshold voltage VT . VT selected in this way ranged from 19.5 to 61 mV.

Devices with higher room temperature resistance generally had higher VT , but this was not

always the case. At higher voltages, the current through all devices could be fit to the

Middleton-Wingreen power law, with ζ ranging from 3.3 to 4.0. As noted in Chapter 2,

the Middleton-Wingreen theory predicts ζ = 5/3 for 2D arrays, and most reported values

have been ζ = 2 or less. Lebreton et al. have suggested that higher values of ζ indicate

higher dimensional transport, and observed ζ = 3.6 in their 3D arrays [145]. Our measured

values of ζ were consistent with 3D transport, but the physical structure suggested that

transport should be 2D: the Au islands appeared to be deposited in a single layer, and the

Ti crystals, if they were indeed governing the current, were likely to be columnar at this

film thickness [146]. We also noted that ζ = 1 was not observed at the highest measured

drain-source biases, suggesting that the arrays were still operating in the scaling regime.

1E-13

1E-12

1E-11

1E-10

1E-09

1E-08

0.1 1 10

(V/VT)-1

Dra

in-S

ourc

e C

urr

ent

(A) VT=30 mV

!=3.32

Figure 5.22: Middleton-Wingreen plot of the current through a high-resistance device with Auislands, measured inside a liquid helium dewar. T = 4.2 K. VT = 30 mV, ζ = 3.32.

Gate sweep measurements provided additional evidence of Coulomb blockade in the

high-resistance device with Au islands. Quantitative analysis, however, was complicated by


1E-13

1E-12

1E-11

1E-10

1E-09

1E-08

0.1 1 10

(V/VT)-1

Dra

in-S

ourc

e C

urr

ent

(A)

VT=19.5 mV

!=4.01

Figure 5.23: Middleton-Wingreen plot of the current through a low-resistance device with Au islands,measured inside a liquid helium dewar. T = 4.2 K. VT = 20 mV, ζ = 4.01.

1E-13

1E-12

1E-11

1E-10

1E-09

0.1 1 10

(V/VT)-1

Dra

in-S

ourc

e C

urr

ent

(A) VT=61 mV

!=3.46

Figure 5.24: Middleton-Wingreen plot of the current through a high-resistance device without Auislands, measured inside a liquid helium dewar. T = 4.2 K. VT = 61 mV, ζ = 3.46.


1E-13

1E-12

1E-11

1E-10

1E-09

1E-08

0.1 1 10

(V/VT)-1

Dra

in-S

ourc

e C

urr

ent

(A)

VT=20 mV

!=3.87

Figure 5.25: Middleton-Wingreen plot of the current through a low-resistance device without Auislands, measured inside a liquid helium dewar. T = 4.2 K. VT = 20 mV, ζ = 3.87.

excessive noise in the measurement and the complicated behavior of the gate current at low

temperatures.

Fig. 5.26 shows the drain and gate currents through a high-resistance device with Au

islands at T = 4.2 K, as the gate-source voltage VGS was swept from 0 to 20 V and back

while the drain-source voltage VDS was held at 0 V. The gate contact was fully insulated

from the drain and source leads by 100 nm of SiO2, so the substantial drain and gate currents

and hysteresis appeared to be caused by capacitance in the circuit, as opposed to leakage.

Our proposed explanation for the behavior of the gate current is detailed in the Appendix.

In an attempt to remove the influence of the gate current from the drain current, we

subtracted the VDS = 0 V drain current from the drain currents measured at other values

of VDS . An example of this is shown in Fig. 5.27 for VDS = 44 mV, where the thin, grey

lines are the raw data from four separate measurements of the gate sweep in the positive

direction, and the thick black line is the average. Subtracting the VDS = 0 V drain current

from the average produces the thick grey line, which we call the “corrected” current. The

compiled currents derived in this way for gate sweeps in the positive direction for VDS from

10 to 44 mV are shown in Fig. 5.28.


-8

-4

0

4

8

0 5 10 15 20

Gate-Source Voltage (V)

Curr

ent

(pA

)

Gate Current

Drain Current

VDS=0 V

T=4.2 K

Figure 5.26: Drain (black line) and gate (grey line) currents as VGS is swept from 0 to 20 V andback, for VDS = 0 V. The measurement was performed at T = 4.2 K. The arrows indicate thedirection of the gate voltage sweep.

-4

-3

-2

-1

0

1

2

3

0 5 10 15 20


Dra

in C

urr

ent

(pA

)

Corrected current

Individual runs

and average

VDS=44 mV

T=4.2 K

Figure 5.27: Measured drain currents (thin, grey lines), average current (thick, black line), andcurrent corrected by subtraction of VDS = 0 V drain current (thick, grey line), for VDS = 44 Vinside liquid He dewar, T = 4.2 K.


Peaks in the drain current with behavior consistent with the MOSES simulations pre-

sented earlier were observed, and displayed some reproducibility between different drain

biases. It was also evident, however, that noise in the measurement was of similar mag-

nitude to some of the peaks, and it was not possible to unambiguously identify the peak

locations. For clarity, Fig. 5.29 presents the same data after smoothing and with each trace

offset by 0.1 pA. Although small peaks at VGS=10, 13, and 17 V are evident, the clearest

feature appears to be the strong decrease in the drain current as VGS approaches 20 V. This

modulation of the drain current by VGS is consistent with Coulomb blockade, and difficult

to explain by other means.

-0.5

0

0.5

1

1.5

2

2.5

0 5 10 15 20


Dra

in-S

ourc

e C

urr

ent

(pA

)

VG=0 to 20 V

VD=10 to 44 mV

T=4.2 K

Figure 5.28: Drain currents v. gate-source voltage sweep from 0 to 20 V inside a liquid He dewar,T = 4.2 K. VDS = 10, 20 mV and 25–44 mV in 1 mV increments.

The current from gate sweeps in the negative direction was not identical, but similar,

and is shown in Fig. 5.30. The strong increase in the current as VGS decreases from 20 V

is evident. The drain currents measured for negative drain biases are shown in Fig. 5.31.

The simulation results presented in Chapter 2 showed that the drain current behavior for

positive and negative drain biases may be different. Although smaller features were not as

apparent in this measurement, the strong decrease in the drain current was again observed

as VGS approached 20 V. A measurement performed several days later with a smaller VGS


0

1

2

3

4

0 5 10 15 20


Dra

in C

urr

ent

(pA

)

Figure 5.29: Drain currents v. gate-source voltage sweep from 0 to 20 V, smoothed and with 0.1 pAoffset, inside liquid He dewar, T = 4.2 K.

step size is shown in Fig. 5.32. The smaller step size resulted in a slower sweep speed, and

reduced the capacitive current. Once again, as VGS approached 20 V, the measured drain

current decreased.

Further measurements of this device with VGS > 20 V may have been useful, especially if

the drain current were observed to modulate with a consistent period. Concerns of possible

damage to the device, however, lead us to limit VGS to 20 V. A Fast Fourier Transform

analysis of the data was attempted to identify current features with a shorter period, but

the results were inconclusive.

Measurements of a high-resistance device without Au islands did not demonstrate mod-

ulation of IDS by VGS , suggesting that the Au islands played an important role. However,

later measurements of the device with Au islands also displayed no features, so it is possible

that the devices were damaged in a way that destroyed that aspect of their behavior. The

low conductance region around VDS = 0 V continued to be observed in drain voltage sweeps

of both devices.

We concluded that our single electron tunneling devices, fabricated by a novel method,

demonstrated behavior consistent with Coulomb blockade, with low conductance regions

at low drain-source bias, and modulation of the drain-source current by the gate voltage.


0

1

2

3

0 5 10 15 20


Dra

in C

urr

ent

(pA

)

VGS=20 to 0 V

VDS=10 to 44 mV

T=4.2 K

Figure 5.30: Drain currents v. gate-source voltage sweep from 20 to 0 V inside liquid He dewar,T = 4.2 K.

-3

-2

-1

0

0 5 10 15 20


Dra

in C

urr

ent

(pA

)

T=4.2 K

VGS=0 to 20 V

VDS=-10 to -42 mV

Figure 5.31: Drain currents v. gate-source voltage sweep from 0 to 20 V, with negative drain bias,inside liquid He dewar, T = 4.2 K. VDS = −10,−20 mV and −24 to −42 mV in -2 mV steps.


0

1

2

3

4

5

0 5 10 15 20


Dra

in C

urr

ent

(pA

)

VGS=0 to 20 V

VDS=10 to 45 mV

T=4.2 K

Figure 5.32: Drain currents v. gate-source voltage sweep from 0 to 20 V, with smaller gate voltageincrement, inside liquid He dewar, T = 4.2 K. VDS = 10 mV and 20–45 mV in 5 mV increments.

The islands in the array that governed the current appeared to be larger than indicated by

AFM measurements, with larger capacitances and smaller charging energies than predicted.

Whether these islands were formed by the deposited Au or Ti nanocrystals or a combination

of both was unclear.

Chapter 6

Conclusions

6.1 Summary

SETs, electronic devices sensitive to a single electron, have the potential to play an im-

portant role in the extension of Moore’s Law into the future. Operation of SETs at room

temperature, however, requires device dimensions in the nanometer range, and suitable fab-

rication processes are generally either prohibitively complicated or expensive. We developed

a relatively simple and economic fabrication process, based on Au islands and CILO, that

took advantage of aspects of self-assembly, self-alignment, and self-limitation.

The operation of SETs was described by Coulomb blockade theory. A passive circuit

approach was presented to derive the threshold voltage for conduction through a single

island, double junction device. Next, the theory behind charge transport through uniform

1D and 2D arrays was explained, and the effects of the introduction of disorder were shown.

Simulations of the current through a disordered array were used to illustrate the principles

and predict the behavior of the fabricated device.

The use of an AFM to create oxide lines in films of GaAs, NiAl, and Ti was demonstrated.

In GaAs, the dependences of the oxide thickness on AFM tip voltage and translation speed

were fit to a physical model. MIM barriers were fabricated across NiAl wires, but leakage

currents were found to be too high. The electrical barrier height of an oxide line drawn

in Ti was characterized, and closer examination of the thin Ti film indicated that it was

electrically discontinuous. A three-terminal SET structure was fabricated, but room tem-

perature electrical measurements suggested I-V behavior more consistent with thermionic

emission than Coulomb blockade.

116

CHAPTER 6. CONCLUSIONS 117

The self-limiting CILO process was used to fabricate oxide barriers in Ti wires, in con-

strictions defined by both AFM oxidation and electron beam lithography. The Ti oxide

barrier height was characterized and compared to the AFM oxide barrier. The minimum

current density for initiation of CILO was determined. The role of heating in the CILO

process was investigated by examining the effect of heating on the resistance of Ti films.

XPS of the Ti films before and after heating showed their high oxygen content. The cor-

relation between the CILO current behavior and the oxide thickness measured with AFM

was improved by accounting for the presence of multiple Ti oxide stoichiometries, and the

role of surface scattering in increasing local resistivity. A multiple, partial CILO process

was developed to form oxide barriers in films which would otherwise have been damaged by

a single, complete CILO step.

A SET fabrication process utilizing self-assembled Au islands inside CILO-generated

Ti oxide barriers was developed, and used to create devices consisting of a disordered 2D

array between two closely spaced leads. The devices were measured at low temperatures in

two different measurement systems. Differential conductance measurements over a range of

temperatures demonstrated low conductance regions at low bias, consistent with Coulomb

blockade, in devices with and without Au islands. I-V measurements at T = 4.2 K showed

gate modulation of the drain current in a device with Au islands, another characteristic of

Coulomb blockade.

The Coulomb blockade features were only observed at low temperatures, however, in-

dicating that the islands were too large for room temperature operation. The fact that

the low conductance region at low bias was observed in devices both with and without Au

islands suggested the possibility that nanocrystalline grains of Ti, with grain boundaries

oxidized by CILO, may have played a role.

6.2 Future Work

The low temperature measurements suggested that Coulomb blockade was achieved in our

devices. Much of the work in this thesis was exploratory, however, and plenty of room

remains for refinement of both the devices and their measurement to prove their viability

and improve their performance.

First, the noise in the measurements must be reduced. Although the use of an AC

lock-in amplifier complicated the analysis of the first drain current versus drain voltage


measurement due to an apparent offset, such an offset would have less of an impact on

measurements of the drain current versus gate voltage. In this measurement, the focus

would be on identifying the locations of peaks in the drain-source conductance. The signal-

to-noise ratio could also be improved by reducing the distance between islands, which would

increase the tunneling current.

The measurements could also be improved by more accurate monitoring of the device

temperature. An integrated temperature sensor very near the device could accomplish this.

Such a sensor might also allow for measurement of the device temperature during the CILO

process. A primitive sensor was attempted in one version of our device, but was insufficiently

sensitive.

There are undoubtedly many ways to improve the device design. Our need to have

the electron beam lithography performed elsewhere placed limits on the fabrication pro-

cess. Additional lithography and deposition steps would allow for a thicker Ti film in the

leads and contacts, improving device yield when wire bonding, and limiting the electrically

discontinuous Ti film to the central wire and constriction. Access to an evaporator with

a load lock would allow for Ti film depositions at lower pressure, reducing the amount of

oxygen incorporated in the film. Another improvement to the device design would be to

incorporate a patterned side or top gate which might provide better control of the island

potential than the backside contact.

We were unable to thoroughly investigate different geometries for the central constriction

and their effect on CILO. The current density is likely to be more uniform in a constriction

formed by a very gradual transition from the wire width to the constriction width, which

may improve the uniformity of the oxide barrier. Conversely, in a constriction with a

very abrupt transition, the current density is expected to be much higher at the edges.

If oxidation occurs more rapidly at the edges of the constriction, it may be possible to

effectively narrow the constriction beyond the lithography limit.

The most important point to clarify, however, is whether it is the Au islands acting as

the conductive islands for Coulomb blockade, or if it is nanocrystalline grains of Ti. If it is

the Au islands, improvements to the device can be made by optimizing the Au deposition

for island size, uniformity, and density. This would enable the fabrication of the ideal device:

a single island isolated inside an oxide barrier.

Successful fabrication of such an ideal device, however, would rely on the probability of

an island being present in the constriction region. In addition, the exact position of the


island within the constriction would influence the junction characteristics, and the junctions

to source and drain would likely be asymmetric. The different junction capacitance and

conductance values would make it difficult to accurately predict and control the threshold

voltage. Even if multiple islands are allowed, other problems remain. For devices com-

posed of multiple islands, the ideal separation between islands is quite small. Muller et

al. have noted that since the margin of error to keep the islands from shorting together is

similarly small, it may be difficult to reliably achieve acceptable yields, even for research

purposes [147].

If grains of Ti prove to be responsible for Coulomb blockade, a similar calibration of

deposition conditions would be needed to establish control over grain size and uniformity.

Independent control of grain density would likely not be possible in a physically continuous

film. However, it may be possible to use partial CILO to control the oxidation of the grain

boundaries and tune the size of the remaining metallic grain. This would be a very exciting

extension of the CILO technique.

The future success of SETs may depend on whether they can be reliably fabricated

at the small sizes required. Approaches based on self-assembly have demonstrated the

ability to create structures with nanometer scale dimensions, but generally suffer from poor

control over uniformity, density, and placement. The use of CILO to isolate Au islands

is a partial solution to the placement problem. The other problems remain, however, and

the ultimate feasibility of this approach, as well as others based on self-assembly, may rest

on the development of a defect-tolerant circuit architecture that allows for non-uniformity

between devices.

Appendix A

Low Temperature Gate Current

A large gate current with hysteresis was observed for the low temperature gate sweep

measurements conducted with a dunkstick inside a liquid helium dewar. We attributed this

current to capacitance, and believed that the step in the gate current was due to a change

in the gate capacitance resulting from field-induced ionization of holes.

A.1 Characterization and Simple Modeling

To characterize the apparatus, gate voltage sweeps were conducted with and without a

mounted device, at room temperature with the dunkstick outside the dewar, and at T =

4.2 K with the dunkstick inside the dewar. The results of the measurement are shown

in Fig. A.1. The gate current at T = 4.2 K with a mounted device showed complicated

behavior, but the other three gate currents could be modeled as a series resistor-capacitor

circuit. For a ramped gate voltage given by VGS = γt, where γ is the ramp rate and t is

time, the gate current can be generally expressed as:

i(t) = γC

[1− exp

(− t

RC

)](A.1)

Fitting this equation to the gate currents without a mounted device, we determined that

the unshielded wires in the dunkstick contributed ∼50 pF when the dunkstick was outside

the dewar. This was reduced to ∼20 pF when the dunkstick was inserted into the dewar.

A separate measurement showed that the shielded triaxial cables from the HP4155 to the

dunkstick contributed virtually no capacitance.

120

APPENDIX A. LOW TEMPERATURE GATE CURRENT 121

-4

-2

0

2

4

6

8

0 5 10 15 20

Gate Voltage (V)

Gat

e C

urr

ent

(pA

)

Chip in Socket

No Chip

4.2K

Room Temp.

Figure A.1: Characterization of measurement apparatus capacitance, with a loaded device at roomtemperature (thick, grey line), a loaded device at T = 4.2 K (thick, black line), no device at roomtemperature (thin, grey line), and no device at T = 4.2 K (thin, black line).

The device gate capacitance was modeled as being in parallel with the wire capacitance.

From the gate current measured at room temperature with the dunkstick outside the dewar,

the device gate capacitance was calculated to be ∼180 pF. We estimated the device oxide

capacitance to be 23 pF, assuming a parallel plate capacitor with the combined source and

drain contacts as the plate area.

The series resistances in the current fits ranged from 2.5×1012 to 1.5×1013 Ω. This large

resistance may correspond to the HP4155 SMU input resistance, which is rated as ≥ 1013 Ω.

Such a resistance, however, would be expected to be in parallel with the capacitance, instead

of in series.

As shown in Fig. A.1, the gate current behavior at T = 4.2 K with a mounted device

rose sharply around 9 V, then flattened out. Similar behavior was observed during the gate

voltage sweep in the negative direction. The general shape of the current behavior could

be modeled by the introduction of a larger capacitance value in the series resistor-capacitor

circuit at the transition voltage. Fig. A.2 shows a simple simulation result, where the thick,

grey line is the simulation, and the thin, black line is experimental data. The current at low

gate voltage was governed by the cable capacitance (C = 20 pF), and the current at higher


gate voltages was described by C = 54 pF, which was determined by fitting the current.

The capacitance was changed at VGS = 10 V when the gate voltage was swept in the

positive direction, and 11 V in the negative direction. These voltages were chosen to fit the

experimental data. While the simulation for positive sweep direction fit the experimental

data fairly well, the simulated current in the negative sweep direction decayed more slowly

than the experiment.

-4

-2

0

2

4

0 5 10 15 20


Gat

e C

urr

ent

(pA

)

experiment

simulation

Figure A.2: Simple simulation (thick, grey line) of the gate current versus a gate voltage sweep,and experimental data (thin, black line). The gate and measurement apparatus are modeled as aseries RC circuit, where C changes at 10 V when sweeping in the positive direction, and 11 V inthe negative direction.

The change in capacitance can be understood by considering how the gate contact

structure changes as a function of voltage. At room temperature, the gate consists of a

reverse-biased Schottky diode at the back contact and an oxide capacitance on the other

side of the substrate. The large area and reverse leakage current of the Schottky diode allow

additional reverse bias to be dropped primarily across the oxide, and the oxide capacitance

dominates.

At T = 4.2 K, however, the situation is quite different. For Si at T<∼30 K, there

is insufficient thermal energy to ionize dopants, the Fermi level lies midway between the

dopant energy level and the band edge, and virtually all the carriers are frozen out. The


gate capacitance is then dominated by the capacitance formed by the entire substrate. Upon

application of a critical value of gate voltage, however, carriers may be generated by electric

field ionization, and a depletion region could form at the back contact [148]. The structure

would be similar to that at room temperature, and the oxide capacitance would dominate

over the wide-area back depletion capacitance.

This may explain why features observed in the drain current were strongest for gate

voltages larger than the 10 V threshold. For lower VGS and prior to carrier generation, the

voltage applied to the gate had little effect on the island potential. Only for VGS > 10 V,

and after carriers were generated, could the gate strongly control the island potential.

A.2 Physical Explanation

A mechanism for this process has been proposed by Foty, who described how Poole-Frenkel

field-assisted thermal ionization and field-induced tunneling reduce the dwell time of a hole

on an acceptor [149]. An applied electric field lowers and thins the barrier on one side of the

potential well surrounding each dopant, increasing the probability of ionization. Fig. A.3

shows the calculated hole dwell time on an acceptor at T = 4.2 K, where the black line

demonstrates the influence of the electric field on thermal ionization, and the grey line is

for tunneling. The plot indicates that electric fields of ∼1.5×105 V/m would be required to

reduce the hole dwell time to the order of seconds. A gate voltage of 10 V across a 500 µm

thick substrate only produces an electric field of 2×104 V/m.

Foty, however, assumed a hole capture cross-section that is independent of temperature,

and used the room temperature value, σp = 10−15 cm2. Abakumov et al. noted that the

capture cross-section at T = 4.2 K may be as much as four orders of magnitude larger [150].

If this is the case, the gate voltages applied in our measurement are sufficient to reduce the

hole dwell time to seconds or less. The applied electric field is also similar to that required

for impact ionization at low temperatures [151]. Once freed, the holes may contribute to

the ionization of additional carriers.

As can be seen in Fig. A.2, a small bump in the gate current was observed for both

the positive sweep of VGS , where it occurs for VGS just before the transition, and the

downsweep, where bumps were noted both before and after the transition. Foty [149] and

Saks and Nordbryhn [151] noted transient peaks in the substrate current when they applied

a step voltage to a MOS capacitor at T < 15 K. They attributed the location of the peak


1E-20

1E-10

1E+00

1E+10

1E+20

1E+30

0E+00 1E+05 2E+05 3E+05

Electric Field (V/m)

Dw

ell

Tim

e (s

ec)

Thermal

Ionization

Tunneling

T=4.2 K

Figure A.3: The effect of electric field on calculated hole dwell time on acceptor at T = 4.2 K, afterFoty [149].

in time to the highest rate of hole ionization during the formation of the depletion layer.

This ionization current may explain the bump in the gate upsweep current and the small

increase in the gate downsweep current just before the gate capacitance begins to change.

The additional bump in the gate downsweep current after the gate capacitance changes,

however, is not explained by this mechanism.

A.3 Simulations

Simulations were attempted with DESSIS/SDEVICE [152] to verify and quantify the change

in the gate capacitance, but were ultimately unsuccessful. 1D and 2D simulations of both

full-size and reduced-size devices were attempted. Convergence problems at T = 4.2 K,

however, forced us to mainly conduct simulations at higher temperatures and extrapolate

downwards. We used the simulators’ Poole-Frenkel field-enhanced ionization model for

traps to simulate the effect of the gate voltage on acceptor ionization. Although this model

did cause the applied gate voltage to affect carrier ionization, the simulations indicated a

different mechanism, Schenk field-assisted generation, was ultimately responsible for the

increase in carriers.


Schenk modified Shockley-Hall-Read generation to describe how the effective energy

barrier for generation could be lowered by including a field-dependent lateral tunneling com-

ponent [153]. DESSIS/SDEVICE simulations indicated that this mechanism, particularly

under the contact edges where the electric field was highest, could lead to the generation of

carriers. Although there were convergence problems at T = 4.2 K, simulations at slightly

higher temperatures showed promising results.

Unfortunately, a deeper investigation into these results indicated that they were simply

a mathematical artifact. DESSIS/SDEVICE stores a lower limit of 10−100 for its variables,

and the intrinsic carrier concentration ni falls below this value for T < 25 K. At these

low temperatures, ni bottoms out, the numerator of the SHR equation changes sign, and

high-field regions appear to begin generating large numbers of carriers. This was verified

by manual calculations using DESSIS/SDEVICE models, which indicated that the carrier

concentrations should be such that recombination continued as the temperature decreased

below 25 K.

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FABRICATION OF LATERAL OXIDE BARRIERS FOR METAL SINGLE