Fabrication and Fabrication and characterization of characterization of highhigh--performance performance polymer thinpolymer thin--film transistorsfilm transistors

Alberto SalleoPalo Alto Research Center3333 Coyote Hill RoadPalo Alto, CA

Vg=-20V

Vg=-10V

Vg=-5V

Vg=-15V

Source: Apple

Source: Gyricon Media

Source: dpiX

LargeLarge--area electronicsarea electronics

Low-T Flexible substrates!

Screen Printingweb or sheet fed

simplephotolithography

Microcontact Printingsmall features

rapid patterning

Jet-Printingdigital imaging

flexible substratesdirect-write of materials

Challenges: materials compatibility, feature sizes, registration, process development

Alternatives to PhotolithographyAlternatives to Photolithography

(Princeton, UCSC, UCLA)

(PARC, Plastic Logic)

(Harvard, Bell Labs, IBM)

IBM

Rogers, et. al. PNAS 2002

AIP printhead - PARC

OutlineOutline

� Organic semiconductors

� Polymer thin-film transistors

� Patterning techniques

� Non-ideal behavior in polymer TFTs:– Contact resistance– Bias stress– Limits of polymer TFTs?

Organic semiconductors come in 2 “flavors”Organic semiconductors come in 2 “flavors”

1988 19961992 2000 2004 20081984

a-Si:H

Si wafers

Poly-Si

E-paper

Display

Smart cards/ RFID tags

Low-costICs

Today’s PcProcessors

a-Si

1992

102

a-Si:H

Si wafers

Poly-Si

E-paper

Display

Smart cards/ RFID tags

Low-costICs

Processors

E-paper

Display

Smart cards/ RFID tags

Low-costICs

Processors

Oligothiophenes

a-Si

Polythiophenes

Pentacene

Mobility

cm2/V.s

101

1

10-1

10-2

10-3

10-4

10-5

Today’s PCProcessors

PentacenePentacene is the best performing is the best performing small molecule organic semiconductorsmall molecule organic semiconductor

2.5µm

AFM

Low mobility high mobility

10-14

10-12

10-10

10-8

10-6

10-4

-40 -30 -20 -10 0 10 20 30

L=100µmL/W=1/5

µsat

=0.43cm2/Vs

VD=-30V

VD= -1.0V

gate voltage [V]

drai

n cu

rren

t [A

]

Polymeric Organic Semiconductors offer Polymeric Organic Semiconductors offer processing advantagesprocessing advantages

•deposited from solution•amorphous or semicrystalline films•good mechanical properties for flexible substrates

XPT: regio-regular poly(thiophene)

F8T2: poly(9,9-dioctylfluorene-co-bithiophene)

Dow Chemical

Xerox Research Centre Canada

mobility ~ 10-3 to 10-2 cm2 V-1 s-1

mobility ~ 10-2 to 10-1 cm2 V-1 s-1

Carefully designed polymers form ordered filmsCarefully designed polymers form ordered films

anneal

H. Sirringhaus et al., APL 77(3), 406 (2000)

XPT F8T2

OutlineOutline

� Organic semiconductors

� Polymer thin-film transistors

� Patterning techniques

� Non-ideal behavior in polymer TFTs:– Device structure and contact resistance– Bias stress– Limits of polymer TFTs?

ThinThin--film transistorfilm transistor

What is important?A. Conduction at the

semiconductor-dielectric interface

B. Contacts - injection of holes, (and blocking of electrons)

C. Electronic stabilityD. Ambient stabilityE. Fabrication technology

Typical dimensionsDielectric 100-500 nmSemiconductor 20-50 nmChannel “height” <1 nmChannel length 2-100 µmChannel width 10-500 µm

ID/VD = (W/L)CG µF (VG-VT)Conduction = geometry . mobility . voltage

(design material application)

- VG

gate

source drain

VD

+ + + + + +

C

B B

A

D

Disorder and TFT characteristicsDisorder and TFT characteristics

(HOMO)

Valence band

mobile holes

trapped holes

Increasing disorder

Lo

g d

ensi

ty o

f st

ates

Energy Gate voltage

Lo

g c

urr

ent

ideal

real

subt

hres

hold

leakage

Band states

shallow traps

deep traps

Chemically functionalized dielectric surface Chemically functionalized dielectric surface greatly enhances mobilitygreatly enhances mobility

-30 -20 -10 0 10 2010-13

10-12

10-11

10-10

10-9

10-8

Dra

in c

urre

nt (

A)

Gate voltage (V)

µ~10-2 cm2/V.s

µ~10-4 cm2/V.s

No SAM

SAMsource drain

VD

+ + + + + + +

SAM(~ 20 Å thick)

A. Salleo, M. L. Chabinyc, M. S. Yang,R. A. StreetAPL 81(23), 4383 (2002)

SiCl317

Mobility enhancement controlled by Mobility enhancement controlled by molecular ordering at the interfacemolecular ordering at the interface

2850 2900 2950 3000

Abs

orba

nce

(a.u

.)

Wavenumber (cm-1)

0.00001

0.0001

0.001

0.01

0.1

1

Untreatedoxide

Vapordeposited SAM

Solutiondeposited SAM

mo

bili

ty (

cm2 /V

s)

Linear

Saturation

RAIR

2850 2900 2950 3000

Abs

orba

nce

(a.u

.)

Wavenumber (cm-1)

HighHigh--performance performance poly(thiophenepoly(thiophene) transistor ) transistor

Turn-on voltage

-15-14-13-12-11-10

-9-8-7-6-5

-30 -20 -10 0 10 20

Gate Voltage (V)

log

[Dra

in C

urr

ent (

A)]

On

/Off ratio

Sub

-thresh

old

slope

Carrier mobility-10

-8

-6

-4

-2

00 10 20 30 40

Source-Drain Voltage (V)

Dra

in C

urr

ent (

µA

)

Vg =-30 V

Vg =-20 V

Vg =-10 V

saturation regime

linea

r reg

ime

µ~0.1 cm2/V.sIon/Ioff up to 109

Environmental stabilityEnvironmental stability

-30 -20 -10 0 10 2010-13

10-12

10-11

10-10

10-9

10-8

10-7

Dra

in c

urre

nt (

A)

Gate voltage (V)

Encaspulateddevice

in air

Unencaspulateddevice in air

on/off ratio decreases

sub-threshold slope increases

Where are we at this point?Where are we at this point?

-20 -10 0 10 2010-13

10-12

10-11

10-10

10-9

10-8

10-7

10-6

10-5

Gate voltage (V)

XPT a-Si:H

Dra

in c

urre

nt (

A)

- Gate voltage (-V)

OutlineOutline

� Organic semiconductors

� Polymer thin-film transistors

� Patterning techniques

� Non-ideal behavior in polymer TFTs:– Device structure and contact resistance– Bias stress– Limits of polymer TFTs?

DepositionDepositionStructure

� Channel definition

� Device isolation

� Array design

� Carrier mobility

� On/Off ratio

� Stress

patternpattern properties

spin coatingspin coatingdip coatingdip coating

jettingjetting

?

Patterning and propertiesPatterning and properties

Patterning at “intermediate” scales enables use of Patterning at “intermediate” scales enables use of nonnon--conventional techniquesconventional techniques

0.13-0.15 µm features

100-500 µm features

CMOS Processing

Printed Circuit Board

Source: IBM

5-20 µm features

Target

Increasing feature size

Increasing cost

20 µm

InkInk--jet printing of wax is used jet printing of wax is used to define the device structureto define the device structure

Direct Write Etch MaskDeposit film

Etch film strip wax

Print wax mask

Au/Ti contacts

SiO2

doped Si wafer

semiconducting polymer

SAM

wax

source drain

gate

a) substrate with contacts

b) print wax

c) deposit SAM; remove wax

d) dipcoat polymericsemiconductor

Layer registration

TFTsTFTs are completed by taking advantage of are completed by taking advantage of patterned patterned dewettingdewetting

M. L. Chabinyc, W. S. Wong, A. Salleo, K. E. Paul, R. A. StreetAPL 81(23), 4383 (2002)

solution containingpolymeric semiconductor

substrate with patterned surface energy

OTS/SiO2

F8T2

SiO2

200 µm

sourcesemiconducting polymer

drain

gate

SiCl317

JetJet--printed Organic Semiconductorsprinted Organic Semiconductors

� Additive process� Digital mask� Alignment better than 5

microns� Variety of substrates,

dielectrics, surface treatments possible

� Top or bottom contacts possible

Direct deposition of active material

Acoustic inkjet printing (AIP)

InkInk--jet printing requires optimizationjet printing requires optimization

150 µm

Optimize• Temperature of solution and substrate• Concentration of solution• Drop-to-drop overlap• Print speed

Semiconductor not dissolved Semiconductor dewetting

All printAll print--patterned TFTpatterned TFT

100 µm

S

DG

glass

S D

Semiconductor (XPT)

dielectric(Low T SiO2 )

SAM

gate (Cr)

Lo

g[D

rain

Cu

rren

t (A

)]Vsd=-1V

Vsd=-5V

Vsd=-50V

Gate Voltage (V)

Linear Mobility ~0.07 cm2/VsOn/Off ratio ~106

Sub-threshold slope ~1.4 V/decadeVT~ -6V

OutlineOutline

� Organic semiconductors

� Polymer thin-film transistors

� Patterning techniques

� Non-ideal behavior in polymer TFTs:– Device structure and contact resistance– Bias stress– Limits of polymer TFTs?

Staggered TFT performs better than coplanar TFTStaggered TFT performs better than coplanar TFT

+ + + + + +

VDVD

+ + + + + + + +

1.E-09

1.E-08

1.E-07

1.E-06

1.E-05

0.1 1 10 100

Drain Voltage (-V)

Dra

in C

urr

ent

(A)

24201612

8VG

staggered

5020

5µm

coplanar

VG=20VStandard FET model

R. A. Street, A. SalleoAPL 81(5), 2887 (2002)

Threshold voltage shift during operation Threshold voltage shift during operation reduces output currentreduces output current

0.01

0.1

1

0 100 200 300 400Time (sec)

Dra

in c

urr

ent

(A.U

.)

PTRR

F8T2

XPT

F8T2

VG

IDS

t

Characteristic recovery time is strongly Characteristic recovery time is strongly materialmaterial--dependentdependent

-60 -50 -40 -30 -20 -10 0 10

10-11

10-10

10-9

10-8

VT

VT

Von

Von

First measurement

Second measurement

Drain current (A)

Gate voltage (V)

F8T2

Bias stress is due to gate potential shielding by trapped charge (=C0∆VT)

-20 -15 -10 -5 0 5 11E-12

1E-11

1E-10

1E-9

1E-8

1E-7

First measurement Second measurement

Dra

in c

urre

nt (

A)

Gate voltage (V)

XPT∆VT

Bias stress occurs in pulsed operationBias stress occurs in pulsed operation

-14 -12 -10 -8 -6 -4 -2

0

1x10-9

2x10-9

3x10-9

4x10-9

5x10-9

First measurement

Second measurement

Dra

in c

urr

en

t (A

)

Gate voltage (V)

F8T2

150,000 pulses (τ= 20 µs )Duty cycle: 0.2 %

Where is the charge trapped?Where is the charge trapped?

Semiconductor

++

+ Mobile ions

trapping in the polymertrapping at the interface

trapping in the dielectric

+

struct. transf. in polymer

Dielectric

+

VD

Trapping depends on effective stress Trapping depends on effective stress not on dielectric or dielectric/semiconductor not on dielectric or dielectric/semiconductor interfinterf..

0.0 4.0x1012

8.0x1012

1.2x1013

1.6x1013

2.0x1013

1010

1011

1012

1013

|C

0

. ∆V T

| (

cm

-2)

C 0

(VGmax

-VT

0) (cm-2)

PECVD SiO2: µ=1.5×10 -2cm 2/V.s

Parylene: µ=1.2×10 -3cm 2/V.s

Thermal SiO2: µ=7×10 -4cm 2/V.s

OTS: µ=1.5×10 -2cm 2/V.s

VTS: µ=7×10 -4cm 2/V.s

CTS: µ=3×10 -4cm 2/V.s

BTS: µ=5×10 -3cm 2/V.s

Cambridge

Infineon

A. Salleo and R. A. Street, accepted in JAP

Recovery rate scales with absorption of Recovery rate scales with absorption of bandgapbandgap radiation in the polymerradiation in the polymer

0 1x1013

2x1013

3x1013

0.0

2.0x109

4.0x109

6.0x109

8.0x109

1.0x1010

1.2x1010

Ch

arg

e r

ele

ase

ra

te (

cm

-2.s

-1)

Absorbed photon flux (cm -2

.s -1

)

OTS; λ=607 nm

OTS; λ=557 nm

OTS; λ=507 nm

Bare; λ=557 nm

Bare; λ=507 nm

PECVD; λ=557 nm

PECVD; λ=507 nm

Charge trapping occurs within the polymerCharge trapping occurs within the polymer

Semiconductor

++

+Mobile

ions

trapping in the polymertrapping at the interface

trapping in the dielectric

+

struct. transf. in polymer

Dielectric

+

Recovery under illumination

Bias stress independentof type of dielectric

Bias stress independentof SAM at interface

Recovery under illumination

Trapping kinetic in both polymers is “bimolecular”Trapping kinetic in both polymers is “bimolecular”

-7

-6

-5

-4

-3

-2

-1

0

0 0.1 0.2 0.3 0.4 0.5 0.6

N2 (cm-6 x1038)d

N/d

t (c

m-3

sec

-1 x1

019

)

PTRR

dN/dT measured at fixed time

k=1.3 x10-18cm2/sec

h + h BP

2h

h kNdt

dN −∝

-45

-40

-35

-30

-25

-20

-15

-10

-5

0

0 0.5 1 1.5 2 2.5

N2 (cm-6 x 1038)

dN

/dt

(cm

-3se

c-1

x 10

19) F8T2

dN/dt measured at 15 msecVary VG; 15-35V

k = 1.9 x 10-18 cm2/sec

µWV

LdIN

DS

Dh=

XPT

R. A. Street, A. Salleo, M. L. Chabinyc, submitted to Phys. Rev. B

Bias stress may dictate Bias stress may dictate design requirements for design requirements for TFTsTFTs

0.0 4.0x1012

8.0x1012

1.2x1013

1.6x1013

2.0x1013

1010

1011

1012

1013

|C0

. ∆V T

| (cm

-2)

C 0

(VGmax

-VT

0) (cm-2)

4010)(

212

≈××−

=µTG VV

I

L

WVG~ -20VVDS~ -20VI~ 1 µAµ~ 0.015 cm2/V.s

ConclusionsConclusions

� Organic electronics may enable new applications.

� Solution processing enables low-cost patterning techniques such as jet-printing.

� Polymer TFTs are approaching the properties necessary for large-area electronics.

� Control over dielectric/semiconductor interface is necessary for optimal device performance.

� Non-ideal behaviors of the material need to be understood for real applications.

ChallengesChallenges

� Organic dielectric (capacitance, compatibility, process).

� Encapsulation and via holes.

� Reliability, reproducibility and electrical stability.

Michael ChabinycKateri Paul

William WongSteve Ready

Raj ApteRobert StreetJengPing Lu

Dietmar Knipp

Beng OngPing LiuYiliang Wu

Dan Gamota

Paul TownsendDave BrennanMitch Dibbs

NIST ATP GRANT: 70NANB0H3033