FABRICATING AND ALIGNING SILICON NANOWIRES TO INVESTIGATE SIZE

DEPENDENCE FOR QUANTUM CONFINEMENT AND ELECTRONIC TRANSPORT ANALYSIS

SECTION A: PROJECT ABSTRACT

The fabrication and understanding of the fundamental properties of well-defined

one-dimensional structures are critical towards the development of nanostructures, nanomaterials, and developing nanotechnology. One-dimensional nanostructures can address basic issues about size and dimensionality in applications such as photonics [1,2], nanoelectronics [3,4], nanostructured materials [5,6], and material composites [7,8]. In addition, these structures can efficiently transport electrons and excitons, making them ideal for molecular-scale electronic architectures.

Silicon devices have become essential in many current technology devices. As the miniaturization of transistors and circuits continue to progress, the need to wire and connect electronic components become crucial in order for microelectronics to scale down to nanoelectronics. Although nanoscale silicon devices [9,10] as well as wires to connect [11-13] and array [14-16] them have been in development, many obstacles still await. Devices need to be connected to one another; wires, looped and tangled, need to be straightened for circuitry, arrayed wires lack uniform spacing and sometimes the ability to be connected to macro-scale devices.

We attempt to address some of the fundamental problems in nanoscale electronics. Specifically, we propose a strategy to fabricate and align silicon nanowires – to directly specify nanoscale wire diameter (as low as 5 nm), align them, and measure the associated electronic characteristics. The strategy has two unique characteristics. First, the nanowires are perfectly aligned during fabrication. Second, the strategy will enable a simple, rapid, and direct manner to explore nanoscale electronic properties of the nanowires. The method will combine “top down” approaches, such as electron beam (e-beam) lithography and plasma-assisted dry etching, with a “bottom-up” approach, such as molecular beam epitaxy (MBE), to fabricate, align, and array nanowires.

E-beam lithography and plasma etching will pattern and etch nanometer-sized channels, as small as 5 nm wide, in a thin film, providing a fast and simple technique to create nanometer-sized dimensions on a substrate. MBE will then grow single crystal nanowires in each channel. Since MBE uses a variety of materials for epitaxial growth, metallic and semiconducting nanowires can be deposited onto the substrate. All nanowires will be extensively characterized and analyzed for purity using techniques such as high-resolution transmission electron microscopy (HR-TEM), X-Ray diffraction (XRD), field emission scanning electron microscopy (FE-SEM), and energy dispersive X-Ray spectroscopy (EDX). Then, etching and evaporating electrodes at the ends of each nanowire will individually address each nanowire wire. Electrical properties on the nanoscale (10 nm) regime can then be investigated. By combining these two design paradigms, this proposed strategy will provide controlled wire growth on the atomic scale. The fabricated nanowires will be used to investigate the role of dimensionality and size for electron transport and quantum confinement in nanostructures to further understanding of nanoscale phenomena.

1

SECTION B: BACKGROUND AND SIGNIFICANCE

Nanotechnology is moving at a rapid pace, and improved understanding of nanoscale phenomena is critical for advancement in applications in materials science and computer technology. Since their discovery in 1991 [17], carbon nanotubes (CNTs) have been the basis for various nanoscale devices such as field effect transistors [18-21], heterojunctions [22,23], and nanocomputing applications [24,25]. Nanotubes are interesting one-dimensional structures in that they can efficiently transport electrons and optical excitations. However, there are some limitations in creating CNTs. First, controlling the diameter and chirality in nanotubes is difficult. Current fabrication methods yield nanotubes with a range of diameters (~20 nm to 300 nm) and different rolling orientations, resulting in the unpredictability of producing metallic or semiconducting nanotubes [26]. These techniques are problematic since electrical properties of one-dimensional semiconducting structures are controlled by their diameter [27]. Second, controlled and long-term stable doping of CNTs is also very challenging. Nanowires have been gaining a lot of attention as alternatives to CNTs because their growth is easier to control and have been relatively easier to dope with suitable impurities.

Several techniques have been employed for nanowire synthesis. One technique, vapor-liquid-solid growth (VLS), has been used to form single crystal wire structures [28,29]. VLS uses a liquid metal cluster or catalyst that acts as an energetically favored site for absorption of gas phase reactants. A one-dimensional structure grows from the cluster as the reactants supersaturate. The diameter of the structures is limited by the diameter of the liquid metal cluster that can be grown under equilibrium conditions [30]. Another VLS method uses Au to confine silicon nanowire growth. The diameters of these nanowires were still relatively large and had a large size distribution – 20 nm to 100 nm. Sorting nanowires with a large size range and analyzing their respective electronic properties is difficult to accomplish.

Laser-assisted catalytic growth (LCG) has been used to grow a range of multi-component semiconducting nanowires. LCG exploits laser ablation to generate nanometer-size clusters that define the size and direct the growth of crystalline nanowires in combination with a vapor-liquid-solid (VLS) process, as previously described. This growth mechanism uses binary and pseudobinary phase diagrams to choose a specific catalyst:nanowire material composition and growth temperature such that a liquid alloy and solid nanowire material coexists. The cluster has a preferential site where the reactant absorbs, and when supersaturated, the nucleation for crystallization and 1D growth occurs. LCG has been used to grow elemental Si and Ge nanowires [31]. Semiconducting GaAs and GaN nanowires were grown as well, although predicting the catalyst:nanowire material was more difficult due to the complexity or unavailability of information in the ternary phase diagrams [32,33].

Templates have also been utilized to direct nanowire growth [34-38]. Nanometer-sized pores in membranes and zeolites have been used to confine the growth of wires [34,38], and carbon nanotubes have been converted to carbide and nitride nanowires [35-37]. Although template-based methods are straightforward to implement, template-based growth typically produces polycrystalline materials with diameters too large to observe the effects of quantum confinement.

2

Molecular beam epitaxy has also been used to grow and align GaAs nanowires on nanochannel alumina (NCA) templates [39]. Gold was deposited onto the substrate using e-beam evaporation. GaAs wires were then grown using MBE using the deposited gold as a catalyst. Wires were grown perpendicular to the substrate, but no electronic characterizations were performed.

Although nanowire fabrication techniques have been extensively studied, measuring their electron transport properties is still problematic because the wires need to be connected to electrodes. Nanowires are usually fabricated in large, tangled clumps, and finding a technique to straighten and position each wire between two electrodes for electrical analysis has not been straightforward. Even wires that are relatively straight still need to be removed from their substrate in order to be connected to electrodes. Aligning nanowires is not straightforward although several techniques exist tried to address the problem.

Electron transport properties are usually measured by randomly dispersing nanowires on a TEM grid and fabricating electrodes around isolated wires [40]. Since nanowires are often looped or somewhat straight, but with no directional control, this process is cumbersome in that the grid needs to be scanned in order to find a relatively straight wire that is somewhat isolated in order to fabricate electrodes. Nanowires have also been prepared for analysis by using ultrasonic dispersion to distribute nanowires across a TEM grid for analysis [41].

Aligning nanowires is not only critical for measuring transport properties, but also for creating networks and arrays for nanoelectronics applications. One technique combines fluidic alignment with surface patterning techniques [42]. A surface was lithographically defined into channels and chemically modified. The nanowires were aligned in a microfluidics chamber. Although wires were aligned into networks, the spacing between each wire was not consistently uniform, and using microfluidics to array nanowires is laborious compared to directly depositing wires into an arrayed format.

Nanowires have also been deposited and aligned using electric field-assisted assembly [43,44]. Nanowires were positioned between two lithographically defined electrodes on a SiO2 substrate. The nanowires were assembled due to polarization from applying an alternating electric field. Although this technique assembled nanowires for electrical characterization, the nanowires used were quite large (70 nm to 100 nm), which would not exhibit any of the quantum effects that would be used for nanoscale electronics. Although electric fields can control assembly, this method can be limited in the packing density it can achieve because of the electrostatic interference between electrodes.

Crossbar arrays [14] have also been fabricated by creating a “stamp” for nanowire patterning. Thin film metallic nanowires were grown by electron beam metal evaporation and then were physically transferred onto a silicon wafer. Transport properties were measured by sectioning the wires by ion etching and fabricating electrodes by e-beam lithography. Although this technique has been the most promising in that it produced wires that were straight for long distances and could be arrayed into interesting crossbar array patterns, this technique was limited in that it could not produce single crystal wires or semiconducting wires. In addition, since this technique placed the substrate at an angle to the evaporants during evaporation, there may be a shadowing

3

effect onto the nanowires, resulting non-uniform thickness across the diameter of the wire.

Proposed Approach for Nanowire Fabrication and Alignment

Nanowires have the potential to answer fundamental questions about one-

dimensional structures and are expected to play a central role in nanoelectronics applications. To explore these questions, varying nanowire diameter and chemical composition will be required. Here, we propose an approach to create silicon nanowires, using a template fabricated from a combination of well-established techniques used in microelectronics manufacturing such as silicon-on-insulator technology (SOI), electron beam lithography, plasma-assisted dry etching, and molecular beam epitaxy. The process involves using a single crystal substrate and creating an insulating layer through SOI techniques, patterning a nanowire template with electron beam lithography, etching the template with a plasma dry etch, followed by nanowire deposition using molecular beam epitaxy. The physical template will produce aligned, straight wires for long distances that will make analyzing and arraying nanowires and connecting them to electrodes for analysis more straightforward. By fabricating electrodes around the wires, a direct measure of the electron transport characteristics is possible.

Oxygen implantation is a technique used in microelectronics fabrication in order to create an oxide layer at the surface or buried within a silicon substrate. Typically, the silicon dioxide insulator is sandwiched between the silicon substrate and another thin layer of silicon, referred to as silicon on insulator (SOI). This technology is significant in that transistors are insolated from each other and the substrate material. Without an oxide layer, fabricating multiple transistors on a substrate connects each to its neighbor and substrate electrically.

Epitaxial SiO2 has been grown and analyzed by several laboratories [45-47], but ion implantation of oxygen at high enough doses to produce SiO2 has been reported since the mid 1960s [48,49]. For typical IC dimensions, roughly 1015 ions per cm2 are used to create an oxide layer. The quality and structure of the oxide layer depends on the dose and energy of the implanting oxygen as well as the temperature of the wafer during implantation. As the dose increases, oxygen builds to the solubility limit, and further increases in the dose would form SiO2 islands.

Conventional ion implantation breaks the crystal lattice, and a dose of 1015 ions per cm2 can create an amorphous structure. A process called solid-phase epitaxy is used where the crystalline structure is re-created by annealing the wafer at high temperatures (900oC to 1100oC) [50]. This process is driven by the lower free energy of the crystalline state, compared to an amorphous structure, and depends on the presence of the crystalline substrate (the crystalline silicon wafer) in intimate contact with the amorphous surface layer.

To create crystalline oxide layers within a silicon substrate, a technique called SIMOX (Separation by Implantation of Oxygen) can be used. A crystalline oxide layer contains 4.4 x 1022 oxygen atoms/cm3. From experiments it has been shown that a standard oxygen ion implantation dose of 1.8x1018 per cm2 is used to create a continuous crystalline layer of oxide [51]. The temperature at which the implantation occurs is also important to the quality of the oxide layer and substrate. When implantation is carried

4

out at high temperatures (typically between 600oC and 650oC), the damage to the lattice can be annealed out during implantation, sometimes referred to as a “self anneal”. After oxygen implantation, another thermal annealing step is necessary to create a device-worthy SIMOX structure. As a general rule, the higher the annealing temperature, the better the quality of the oxide layer. Ideally, annealing the substrate a few degrees below the melting point of silicon (1415oC) produces high quality crystalline oxide layers. Annealing substrates at 1405oC using a lamp system has been used create crystalline oxide SIMOX layers [52]. After annealing, the oxide layer and the silicon layers exhibit crystallinity [45-47,53,54].

Resolution in e-beam lithography is not limited by diffraction because the quantum mechanical wavelength is exceedingly small. Although other nanolithography techniques, such as probe lithography, can also create nanometer-sized features, they involve considerable more time than e-beam lithography, which usually requires approximately 1 hour to 1.5 hours per substrate. The energy and dose of electron beams can be precisely controlled, and the deflection and modulation can be controlled by electrostatic or magnetic fields with speed and precision. E-beam lithography can directly write on a resist-coated substrate or can use electrons to create a mask whose pattern can be subsequently transferred to a substrate. E-beam lithography can accurately register over small areas of a substrate or directly write on a surface, eliminating the need for a mask, since it has a large depth of focus [55].

Numerous e-beam resists are used for fabricating masks and for direct write applications. Resists can have a positive or negative tone [56]. For positive resists, the e-beam weakens the polymer by rupture or scission of the main and side polymer chains. The exposed resist becomes more soluble in developing solutions. For a negative resist, the reaction strengthens the polymer by cross-linking main chains or pendant side chains of the polymer, making the resist less soluble to developing solutions.

Almost any material can function as a resist, although one must consider sensitivity, resolution, tone, and etching resistance for a particular application. Poly(methylmethacrylate) is an example of an inexpensive, positive resist with high-resolution capability. A co-polymer of glycidyl methacrylate ethyl acrylate is an example of a negative resist used to fabricate masks. E-beam lithography can create line-widths as small as 5 nm with a pitch as small as 30 nm [57,58].

To etch through patterned oxide layers, a plasma-assisted dry etch can be used. In one type of plasma dry etch technique, a substrate is etched by a combination a physical and chemical etching process, where the surface is bombarded with ions causing a reaction at the substrate surface. For an anisotropic etch profile, vertical sidewalls can be created by first bombarding the surface with high-energy ions (< 1000 eV), creating dangling bonds and dislocations. The substrate becomes more reactive towards the etchant species as a result [55]. A reactive neutral species, such as fluorine atoms, then diffuse to the substrate where they form volatile products with the layer to be removed. The plasma supplies the gaseous, reactive etchant species. Vacuum pumping removes the volatile reaction products. This technique is called chemically assisted ion-beam etching (CAIBE). The etch rates can vary between 100 Å/min to 2000 Å/min. Chemically assisted ion etching can accurately transfer a mask pattern to the substrate and can selectively etch different materials. An anisotropic etch can be further refined by using helium cooling (to temperatures as low as –120oC).

5

A fabricated template from e-beam lithography and a plasma dry etch can then be used in combination with MBE to create single crystal nanowires. A MBE apparatus is shown in Figure 1 as well as an example of software interface to control material deposition onto a substrate. A schematic illustration of the essential parts of a MBE deposition chamber is shown in Figure 2A. The entire apparatus is under ultra-high vacuum (10-11 Torr). The deposition chamber is the most crucial element in the MBE apparatus. A cryogenic shell filled with liquid nitrogen surrounds the chamber. The substrate is held on a heating stage with translatable movement (X, Y, and Z movement) and on a horizontal axis manipulator, which can automatically and continuously rotate and heat the substrate. The substrate can be positioned with respect to the beam at any angle between the horizontal and vertical plane of the chamber. The manipulator can also incorporate a non-inductively wound high-efficiency heating foil that will be able to heat the substrate between 400oC to 800oC. Heating the substrate surface allows atoms to crystallize into the lower free energy lattice structure of the substrate.

The MBE chamber is also divided into three essential zones where different physical phenomena occur [59], schematically shown in Figure 2B. In the first zone, the molecular beams are generated. The molecular beams travel and then intersect each other and mix in the second zone. Crystallization onto the substrate occurs in the third zone.

A molecular beam epitaxy apparatus arranges atoms in a single-crystal fashion using a crystalline substrate such that the lattice of the newly formed crystal duplicates the lattice of the substrate, schematically shown in Figure 2C. The crystalline substrate is placed into the deposition chamber and heated. The materials of interest are kept in cells and are then heated to form a stream of atoms. The atomic streams impinge upon the substrate in a line-of-sight fashion, creating an atomic layer on the substrate surface. Fast acting shutters enable the user to control the deposition, resulting in a well-defined profile. One or two atomic layers are deposited between shutter exposures. The crystal structure of the layers is determined by the structure of the substrate, the thermodynamics of the materials, and the substrate temperature. Deposition rate in MBE is low – about an atomic layer per second, giving the user control over film thickness. Creating enough layers to fabricate the nanowires would take approximately 30 minutes to an hour, which is faster or on par with current techniques employed to create nanowires.

Figure 1: (A) Software graphical interface to control material deposition in the MBE chamber. (B)

MBE apparatus in a clean room.

6

Figure 2: (A) Cross-sectional view of the deposition chamber in a MBE apparatus, illustrating the

geometry and configuration of the evaporation sources, shutters and substrate manipulator [60]. (B) Schematic illustration of the three zones where the basic processes of MBE. Each zone is indicated in

the diagram. Figure adapted from [59]. (C) Schematic illustration of single crystal film growth by MBE.

SPECIFIC AIMS

A technique to fabricate aligned nanowires will increase understanding of the role

of size and dimensionality in one-dimensional structures that is necessary for nanotechnology and nanoelectronics applications. Fabricating aligned nanowires will make electronic transport characterization straightforward. By combining techniques such as e-beam lithography and molecular beam epitaxy, nanowires with a consistent length can be fabricated on a single substrate. This proposal has three specific aims to address nanowire fabrication and characterization: Specific Aim 1. To investigate the use of SOI technologies to create a crystalline insulating layer in order to isolate nanowire structures. Specific Aim 2. To combine techniques such as electron beam lithography, plasma-assisted dry etching, and molecular beam epitaxy to fabricate and align nanowires. Specific Aim 3. To develop a simple and robust approach to characterize nanowire properties.

7

SECTION C: PROJECT DESCRIPTION A general scheme of the proposed approach is shown as a block diagram in Figure 2. To maintain sample purity and avoid contamination, all experiments should be undertaken in a Class I clean room environment.

Figure 3: Block diagram of overall nanowire fabrication process.

Three types of substrates will be grown and used for analysis during the experiments: nanowire templates and two types of monitor substrates. “Monitor substrates” will be used to monitor epitaxial growth and in analysis techniques such as HR-TEM, XRD, FE-SEM and EDX. One monitor substrate will consist of only the silicon substrate and oxide layer – no etching will be done. An epitaxial layer will then be grown on the substrate simultaneously with the nanowire template in order to monitor single crystal growth as well as for subsequent XRD and EDX analysis. Another monitor substrate will be fabricated in the exact same fashion as the nanowire template. Nanowire material will also be deposited into the monitor substrate simultaneously with the nanowire template. The wires will then be removed from the monitor substrate and used for HR-TEM characterization. 1. Oxygen implantation. The proposed study will begin by creating an insulating layer on a high-quality, crystalline substrate. The initial studies will use crystalline silicon substrates. Standard SIMOX techniques, illustrated in Figure 4, will be used to implant a 100 nm to 200 nm thick layer of oxide material onto the silicon substrate. An implantation energy of 190eV at a dose of 4.4 x 1017 atoms/cm2 has been shown to produce a 100 nm oxide layer [51]. As the ions bombard the surface, the substrate will be heated to 600oC to ensure that the oxygen ions will diffuse through the lattice and reduce deformity of the crystal structure (a “soft anneal) [61]. After oxygen ion implantation, another thermal annealing step is necessary to fabricate a crystalline oxide layer. Annealing will be done in an argon gas atmosphere

8

since better material qualities have been achieved when carried out in an argon environment [51]. The substrate will then be annealed at 1405oC using a lamp furnace to re-establish the crystal structure of the oxide layer.

Figure 4: Schematic of oxygen ion implantation: High energy oxygen ions bombard the silicon

surface to form a single crystal oxide layer [12].

2. E-beam Lithography. A nanowire template will be masked by depositing a photoresist layer on a silica substrate followed by electron beam lithography, schematically shown in Figure 5. An e-beam resist layer, such as polymethylmethacrylate (PMMA) is deposited on top of the substrate. The substrate will next be inserted into an e-beam lithography apparatus. A pattern corresponding to the positioning of the wires will be programmed into the machine. The resist will then be selectively exposed corresponding to nanowire placement on the pattern.

To study the role of size and dimensionality of nanowire systems, nanowires with four different widths will be studied: 10 nm, 25 nm, 50 nm, and 75 nm. All nanowires will be approximately 5 µm to 10 µm long, although the substrate length restricts the ultimate length. The nanowires will be spaced 100 nm apart. All four diameter sizes will be fabricated onto one substrate. Although these diameters were chosen based on previous studies on nanowire fabrication [33], e-beam lithography has been able to fabricate feature sizes as small as 5 nm [57,62]. Using this method, it will be straightforward to determine what sizes play a role in quantum confinement.

The resist will then be lifted-off using ultrasonic agitation [58,63], leaving a nanowire template. The mask pattern can be used to repeatedly pattern wires on other substrates.

9

Figure 5: (A) Schematic for fabricating a physical template using electron beam lithography for

nanowires. The e-beam resist in this figure is an example of a positive resist. (B and C) Examples of e-beam lithography patterns etched onto (B) PMMA [58] and (C) nickel [57]. Lines between 5 nm to

7nm were etched onto the PMMA substrate in (B) while 20 nm lines were etched into the nickel substrate in (C).

Two different methods can be used to deposit an e-beam resist layer on the silica

substrate. In one method, a resist layer can be deposited on the substrate through spin-coating. Resist layers as thin as 50 nm have been obtained from spin-coating [57]. In another method, layers as thin as 30 Å – 100 Å can be formed using Langmuir-Blodgett (LB) techniques [55]. Organic monolayers floating on a water surface are transferred onto a solid substrate in order to create LB resist films. Films of poly(methyl methacrylate) have been deposited onto substrates using the LB technique for e-beam lithography [64-66].

Figure 6: Schematic of a plasma-assisted dry of the resist-covered substrate.

10

3. Plasma-Assisted Dry Etch of Nanowire Templates [67]. Schematically shown in Figure 6A, the resist-covered oxidized silicon plates will then be placed in a chemically assisted ion beam etching system (CAIBE). A 100 nm trench will be etched into each area not masked by a resist layer using a CF4/CHF3 gas mixture with a chamber pressure of 200 mTorr. Under these parameters, the oxide layer will be etched at a rate of 22Å/second. NOTE: some substrates will not be etched – they will be used as monitor substrates to examine epitaxial growth, as shown in Figure 6B. 4. Epitaxial Growth of Nanowires [60]. Molecular beam epitaxy (MBE) is a versatile technique for growing thin epitaxial structures. High quality epitaxial layers are routinely grown on large substrates (~3 inches) for industrial applications. In MBE, thin films crystallize via reactions between thermal-energy atomic beams of the constituent elements and the substrate surface, which is heated to elevated temperatures in an ultra-high vacuum environment. The growth of the layer depends on the evaporation rate of the source. Since the growth rate is typically low, 1 monolayer/second, the growth of the film is very smooth.

The substrates (including the monitor templates) will be loaded onto a cassette that can hold multiple substrates in an entry chamber on the MBE apparatus. The chamber allows rapid loading and unloading from the instrument. The cassette will be then initially and rapidly evacuated in the loading chamber using a roughing pump. A transfer system, consisting of a rack-and-pinion trolley design, will move the cassette from the entry chamber to and from the stage in the deposition chamber and deposition chamber substrate holder. Transfer forks on the trolley will allow movement of the substrate onto and off the substrate trolleys to the stage. There, the substrate enters the deposition chamber, where it is further evacuated to 10-11 Torr using a cryo-pump. Viewports along the trolley will also allow visual access for manipulation.

A schematic for growing nanowires on the template is shown in Figure 7. The wire templates will be placed in the MBE growth chamber on a heated sample stage with a manipulator under ultra-high vacuum. Growth temperatures will depend on the materials used for the wires. For example, silicon has been grown with MBE at 400oC [68]. Shutters will control the deposition rate. A layer approximately 10 nm thick will be deposited onto the wafer. Since the nanowires will have a small diameter (~10 nm) and a small layer will be grown, epitaxial growth should take ~30 minutes to an hour.

The wires produced will have a flattened rectangular shape due to the shape of the template. Although the wire templates will have 4 sets of widths for the nanowires, the deposition thickness will remain constant to assure quantum confinement in one direction. As a result, quantum confinement in the other dimension will be examined by the feature sizes obtained from e-beam lithography.

In addition to growing nanowire material on the wire template, material will be simultaneously deposited onto monitor templates (with non-etched silicon layers).

Within 18 months, silicon nanowires will be made to study the growth of semiconductor nanowires. These fabricated nanowires can also be compared to other semiconductor nanowires fabricated with other methods from literature in order to compare structural characteristics. These nanowires can be characterized prior to electrode fabrication.

11

Figure 7: Schematic of nanowire growth on a template using molecular beam epitaxy.

4.1. Growth Monitoring in MBE with RHEED [60]. Growth will be interrogated on

the flat monitor template by using Reflection High Energy Electron Diffraction (RHEED). By using a non-etched monitor substrate that is fabricated under the same conditions as the nanowire templates, layer growth can be monitored without interference from the diffraction patterns that may result from the nanowire template. In RHEED, a high-energy electron beam (10 keV to 30 keV) strikes the sample at a grazing incidence, creating a diffraction pattern on a phosphor screen. The phosphor screen in the deposition chamber allows the RHEED unit to monitor the epitaxial growth. Electrons penetrate through a few monolayers, and the diffracted intensity is directly displayed on the screen without any focusing, scanning, or mechanical manipulations. The diffraction pattern is instantaneously displayed. RHEED analysis will give information on the average structure of the surface, giving qualitative information of the surface. If the surface is more periodic, the diffraction pattern will be sharper, which will be used to measure interatomic spacing. The crystal periodicity perpendicular to the incident beam is inversely proportional to the periodicity of the diffracted spots and will be used to determine the crystal orientation at the surface or the lattice parameters of the epitaxial film.

12

5. Doping Silicon Nanowires by Ion Implantation [69]. Prior to wet etching of the SiO2 after molecular beam epitaxy deposition of nanowire materials, the silicon nanowires will be doped with impurities such as boron and phosphorus. Ion implantation is the principle method for doping materials. The same method is used for oxygen implantation to create a silicon dioxide layer on the substrate. Dopants can be deposited at any depth using ion implantation, independent of the thermodynamics of diffusion and problems with solid solubility and precipitation. Ion beams penetrating the substrate damage the crystal lattice, but subsequent annealing can restore the crystallinity of the substrate. Typical annealing temperatures of 700oC to 1000oC and a dopant dose of ~1016 ions/cm2 are used during implantation. The acceleration energy and the beam current control the depth of the penetration of the dopants as well as the dopant concentration. The average distance that the ions travel depends on the acceleration energy, the ion mass, and the stopping power of the material. A post thermal annealing at a temperature above 900oC removes damage from the silicon lattice and activates the implanted impurities. 6. Structural Characterization by High-Resolution Transmission Electron Microscopy (HR-TEM) [70]. Nanowires from monitor templates containing the nanowire pattern will be dispersed onto a TEM grid to directly measure nanowire structure. The structural properties of the nanowires can be examined before and after electrode deposition using high-resolution transmission electron microscopy (HR-TEM), as shown in Figure 8. By examining the interference pattern between forward-scattered and backward-scattered electrons from the substrate, HR-TEM can directly image objects with atomic scale resolution. In particular, the crystal structure will be examined in order to identify if the nanowire formation is crystalline or polycrystalline. HR-TEM will also be able to determine any structural defects such as grain boundaries, stacking faults, crystal dislocations, etc.

13

Figure 8: HR-TEM image of a Si/SiGe nanowire. Scale bar represents 3 nm. Inset shows the crystal

pattern of the nanowire [15].

7. Structural and Purity Characterization by X-Ray Diffraction (XRD). The crystal structure grown on all substrates will be further analyzed using XRD on the non-etched monitor templates. X-Ray diffraction (XRD) analysis of the nanowire sample will determine the crystal structure of the nanowires as well as determine the overall purity. XRD analyzes the fine structure of a material using diffraction. A diffractometer will be used to analyze the nanowires. A diffractometer can make a pattern from any crystalline solid. A computer controls the diffractometer and records the data generated. The diffractometer contains an X-Ray tube to generate X-Rays. For example, it can contain a tungsten filament and a copper target, and by applying a voltage, electrons are accelerated towards the copper target to generate copper X-Rays (1.54 Å). A chiller attached to the system cools the X-Ray tube, and a regulator provides a smooth and steady stream of electricity to the instrument. The diffractometer will also contain a slit to collimate the X-Rays before they hit the surface. The substrate is mounted in the sample chamber, and the X-Rays hit and scatter from the sample. The diffracted beams can then be measured by a scintillation counter, which measures X-Ray intensity. The scintillation counter is mounted on an angle-measure device that rotates through a range of angles and can enable the scintillation counter to measure X-Ray intensity at any angle relative to the specimen. An example of a XRD spectrum of a silicon nanowire sample is shown in Figure 9.

14

Figure 9: XRD spectrum of a silicon nanowire sample. The vertical bars show the standard XRD

pattern of Si from the ICDD database [71].

8. Structural Characterization with Field Emission Scanning Electron Microscopy (FE-SEM). For additional structural analysis, the nanowire samples will be viewed with the FE-SEM in order to examine structural features. The nanowire template can be directly examined. By using a field emission source, a FE-SEM has high spatial resolution since it has very narrow beams at low and high-energy electron energy, minimizing sample damage and charging. As a result, a field emission SEM will provide resolution down to 1 nm, 3 to 6 times better than a conventional SEM. FE-SEM can also probe closer to the immediate material surface since it can provide low-energy electrons, and there is virtually not need for applying a conductive surface to a sample since there is reduced charging of the sample. 9. Elemental Analysis by Energy Dispersive X-Ray Spectrometry (EDX). In addition to atomic-level image formation, the high-energy electrons used in TEM can be used in energy dispersive X-Ray spectrometry (EDX), which will then be used to examine the purity of the nanowire samples. The nanowires dispersed on the TEM grid from the monitor template will be used for examination. EDX data will be compared to purity data obtained from XRD analysis in order to further verify the composition of the nanowires. A spectrum can be acquired from a small region of the nanowires using a highly focused electron beam. As an electron beam hits the sample surface, X-Ray fluorescence is generated from the atoms in its path. The energy of each X-Ray generated is characteristic of the element that produced it, and an EDX system collects those X-Rays and compares them with known standards. A spectrum is generated by the system, which sorts and plots the energies of the X-Rays and automatically identifies and labels the elements generating the peaks. An example of an EDX spectrum from a silicon nanowire is shown in Figure 10. The oxygen peak arose from the oxygen layer on the substrate surface.

15

Figure 10: EDX spectrum of a silicon nanowire [71]

10. Creating Electrodes with E-beam Evaporation. After the nanowires are fabricated, electrodes can be created on the nanowire substrate using a combination of e-beam lithography, as previously described, and e-beam evaporation, as shown in Figure 11A. An e-beam resist can be deposited on top of the deposited nanowires. Using e-beam lithography, 1 µm electrodes will be created at the ends of each nanowire. E-beam evaporation will be used to deposit metal for the electrodes. The e-beam resist can then be removed, leaving electrodes, which can be used to directly measure the electron transport properties of the nanowires. Characterization can be performed on the substrate to verify the integrity of the nanowire structures.

Evaporation is based on sublimating a heated material onto a substrate in a vacuum. In e-beam evaporation, a high intensity electron gun focuses onto a target material, which is contained in a crucible or other container, shown in Figure 11B. The beam is magnetically directed onto the evaporant that melts locally. A thin film is evaporated onto a substrate by sublimating a heated material onto a substrate in a high vacuum. Evaporation is a direct line-of-sight process in that the evaporants must impinge on the substrate. Evaporation is fast (e.g. 0.5 µm/min for Al) and comparatively simple. Using proper experimental conditions, pure films can be created.

16

Figure 11: (A) Fabricating electrodes for nanowires using e-beam lithography and e-beam

evaporation. The electrodes will be used to study electrical properties of the nanowires. (B) Diagram of metal evaporation using an electron beam.

11. Conductivity Measurements of Nanowires. Using e-beam lithography, additional electrodes can be connected to the electrodes attached to the fabricated nanowires. Successively larger electrodes can be fabricated, as shown in Figure 12, in order interface nanowires to the macroscale. The electrodes from the constructed nanowire array will be then connected to a pin socket where each macroelectrode will have a fitting for each pin. Each pin pair will then be individually addressed and analyzed through current analysis software, and the constructed nanowire array will be directly connected to a potentiostat. Current vs. voltage plots will be taken to measure the electron transport through each nanowire. A potentiostat such as an Autolab PGSTAT30 would be able to measure current through each nanowire. Several experiments can be conducted with this format. Since different nanowires with different diameters can be fabricated on one substrate, measurements can be performed to see how conductivity depends on nanowire width. By addressing each set of pins, different nanowire dimensions can be easily examined without further fabrication. By using MBE, nanowires can also be fabricated using different materials such that different material properties, such as metallic and semiconducting materials, can be investigated in a straightforward manner. Current measurements from I-V plots in the literature have shown currents ranging from hundreds of pAs to tens of µAs [10,14,24,40,42]. The measurements were done on metallic (e.g. Au, Pt) and semiconducting (e.g. doped Si, GaAs, GaN) nanowires. The nanowires investigated were either polycrystalline or single crystal with diameters ranging from 15 nm to 200 nm. For nanowires of the same material and

17

diameter, a single crystal nanowire should allow more current to flow, due to less electron scattering through the crystal lattice, than a polycrystalline or amorphous wire. The I-V plots also showed that all the nanowires exhibited linear behavior, non-quantum device characteristics, which could be due to the diameter of the nanowire. As the diameter decreases, a quantum-like behavior should appear on an I-V plot. An I-V graph of a quantum wire should have step-like increases in current as the voltage increases. Each increase in current step would be spaced farther apart, depending on the diameter of the wire. As the diameter of the wire decreases, the interval between a current step would increase.

Figure 12: Wiring schematic to measure conductivity of each nanowire using macroelectrodes.

Research Significance This research will provide information about the role of size and dimensionality in nanowire structures, specifically how size plays a role in quantum confinement. We will combine well-proven techniques in microelectronics fabrication to create silicon nanowire arrays to probe size dependence on quantum confinement and to examine their associate electronic transport characteristics. By directly analyzing various nanowire diameters, one will be able to directly correlate size to electronic properties. The aforementioned sizes will probe the size dependence in quantum confinement, directly correlating a size to quantum behavior. This research will also be able to directly test electronic transport in doped silicon wires, also examining how size and crystal structure may affect their transport efficiencies. Since these nanowires do not need to be prepared in a separate step for characterization, which would potentially damage them, this technique can be directly examined as a method to create nanowires. Timeline of Research Steps

18

First year: The first year will be used to mainly hone nanofabrication techniques using oxygen ion implantation and e-beam lithography to create the nanowire templates and the monitor substrates. Oxygen ion implantation will be used to fabricate a single crystal silicon dioxide layer onto a single crystal silicon template. Investigating the most efficient implantation energy to create a single crystal oxide layer, implantation dose, and annealing temperatures will be the primary goals during the first year. E-beam lithography will then be used to make templates for nanowire fabrication. High quality crystalline substrates will be obtained, and a thin layer of resist will be deposited onto the surface. E-beam lithography will then etch 4 sets of nanowires, each with a different diameter, onto a substrate: 10 nm, 25 nm, 50 nm, and 75 nm wide nanowires. Each set will contain 30 to 50 nanowires in order to examine reproducibility of the technique. Subsequent plasma etching of the substrate will produce the nanowire templates for MBE deposition. Second year: The second year will investigate MBE as a method to deposit nanowire material. A MBE instrument will deposit a 10 nm thick layer onto the template. During the second year, doped silicon nanowires will be studied. The nanowires will then be characterized with HR-TEM and FE-SEM to analyze dimensions and crystal structure (mainly HR-TEM), XRD to further analyze crystal structure, and EDX will examine sample purity and dopant concentration. Another e-beam resist will then be deposited on top of the nanowire substrate, and e-beam lithography will then be used to etch electrode templates at each nanowire terminal. Electrodes will then be grown using e-beam evaporation. The resist will then be removed, exposing nanowires with electrodes at each end. Nanowire characteristics will be examined again in order to verify that no defects were caused by electrode fabrication. These electrodes will be used for electronic characterization of the nanowires.

Third year: Different wiring configurations will be explored during the third year. For example, electrodes can be successively increased to connect nanowires to a macroscale instrument. For example, the wires can be connected to a series of electrodes with the following dimensions: 100 nm electrodes 500 nm electrodes 1 micron electrodes

20 micron electrodes 50 micron electrodes 100 micron electrodes. Other wiring dimensions will also be explored to find the optimum wiring procedure. A wiring schematic can be followed similar to the one shown in Figure 12, where the largest electrode can be directly addressable. The largest macroscopic electrode pads will then be connected to a pin socket, where each nanowire will be accessed through a pin-pair.

The nanowires will be connected through the macroscale electrodes to a macroscale instrument to analyze conductivity. An instrument, such as a potentiostat, will then take current vs. voltage plots to characterize electrical properties of each nanowire. The I-V plot information (current range, resistance, shape of the plot) from Si nanowires will be compared to other Si nanowires made with different techniques in the literature [31,72]. For example, polycrystalline nanowires with approximately 10 nm diameters have recently been arrayed and fabricated [14], and this technique will be able to directly compare electron transport between single crystalline and polycrystalline materials. It is expected that nanowires made with MBE using a physical template will create more defect free nanowires, which cause less electron-scattering and will give

19

lower resistance measurements, and it is expected that the single crystal nanowires made with this technique will have smaller resistance measurements compared to polycrystalline wires.

Quantum behavior can also be investigated with this proposal by incrementally decreasing nanowire size. Non-quantum wires should yield a linear I-V plot, and quantum wire should exhibit currents in quantum steps depending on the voltage range. Using this proposed technique, it should be possible to decrease the size of the wires until quantum behavior is observed.

Since each substrate will contain nanowires of different nanowire diameters, the instrument will directly examine how size affects electron transport in nanostructures. With each successive size, we will be able to analyze how size may affect electrical characteristics. Better understanding will be gained on how quantum confinement is affected by size in metallic materials. Future Work. Other nanowire materials can be explored using ideas presented in this proposal. Oxidizable metals such as Al, Cu, Fe, Sn, can also be used as nanowire material. By using a substrate that can undergo oxygen ion implantation, the deposited nanowire material will have the best crystal lattice match from MBE. For example, to create aluminum nanowires, a single crystal aluminum plate would be oxidized to isolate nanowires from each other. The substrate would then be etched to form a nanowire template, and MBE deposition of Al would form the nanowires. Using this proposed technique, a wider range of nanowire materials can be used. Ion implantation has been used to oxide copper [73], aluminum [74-76], and iron [77]. In addition to the electronic studies mentioned, this proposal can open a variety of new research studies. Since all these nanowires are aligned, this technique can be explored as a possibility to array nanowires for nanoelectronics. These nanowires can also be removed from their substrate to be used as interconnects for nanoelectronic devices. Other properties, such as mechanical, optical, and magnetic properties can also be explored using this technique since the nanowires are connected to electrodes. These properties can be exploited to fabricate nanowire devices. For example, semiconducting nanowires have been used in applications such as nanolasers [78,79] or field effect transistors [80], and nanowires fabricated from this technique may create more defect-free nanowires in a reproducible manner for nanotechnology application. In addition to creating metallic and semiconducting nanowires, different metallic and superconducting alloys (with appropriate temperature studies) can be fabricated in order to explore new materials that may be appealing for nanoelectronic applications.

20

REFERENCES 1. D. Snoke, Science 273 (5280), 1351 (1996). 2. J. D. Joannopoulos, P. R. Villeneuve, and S. H. Fan, Nature 386 (6621), 143 (1997). 3. J. R. Heath, P. J. Kuekes, G. S. Snider, and R. S. Williams, Science 280 (5370), 1716

(1998). 4. C. P. Collier, E. W. Wong, M. Belohradsky, F. M. Raymo, J. F. Stoddart, P. J.

Kuekes, R. S. Williams, and J. R. Heath, Science 285 (5426), 391 (1999). 5. M. Bockrath, D. H. Cobden, P. L. McEuen, N. G. Chopra, A. Zettl, A. Thess, and R.

E. Smalley, Science 275 (5308), 1922 (1997). 6. C. M. Lieber, Solid State Commun. 107 (11), 607 (1998). 7. P. D. Yang and C. M. Lieber, J. Mater. Res. 12 (11), 2981 (1997). 8. P. D. Yang and C. M. Lieber, Science 273 (5283), 1836 (1996). 9. J. T. Sheu, K. S. You, C. H. Wu, and K. M. Chang, J. Vac. Sci. Technol. B 20 (6),

2824 (2002). 10. S. W. Chung, J. Y. Yu, and J. R. Heath, Appl. Phys. Lett. 76 (15), 2068 (2000). 11. Y. Cui, X. F. Duan, J. T. Hu, and C. M. Lieber, J. Phys. Chem. B 104 (22), 5213

(2000). 12. Y. Ishikawa, N. Shibata, and S. Fukatsu, Nucl. Instrum. Methods Phys. Res. Sect. B-

Beam Interact. Mater. Atoms 147 (1-4), 304 (1999). 13. D. D. D. Ma, C. S. Lee, F. C. K. Au, S. Y. Tong, and S. T. Lee, Science 299 (5614),

1874 (2003). 14. N. A. Melosh, A. Boukai, F. Diana, B. Gerardot, A. Badolato, P. M. Petroff, and J.

R. Heath, Science 300 (5616), 112 (2003). 15. Y. Wu, R. Fan, and P. Yang, Nano Lett 2 (2), 83 (2002). 16. X. Y. Zhang, L. D. Zhang, G. W. Meng, G. H. Li, N. Y. Jin-Phillipp, and F. Phillipp,

Adv. Mater. 13 (16), 1238 (2001). 17. S. Iijima, Nature 354 (6348), 56 (1991). 18. S. J. Tans, A. R. M. Verschueren, and C. Dekker, Nature 393 (6680), 49 (1998). 19. J. A. Misewich, R. Martel, P. Avouris, J. C. Tsang, S. Heinze, and J. Tersoff, Science

300 (5620), 783 (2003). 20. K. Liu, M. Burghard, S. Roth, and P. Bernier, Appl. Phys. Lett. 75 (16), 2494 (1999). 21. Y. Huang, X. F. Duan, Y. Cui, and C. M. Lieber, Nano Lett. 2 (2), 101 (2002). 22. M. S. Fuhrer, J. Nygard, L. Shih, M. Forero, Y. G. Yoon, M. S. C. Mazzoni, H. J.

Choi, J. Ihm, S. G. Louie, A. Zettl, and P. L. McEuen, Science 288 (5465), 494 (2000).

23. Z. Yao, H. W. C. Postma, L. Balents, and C. Dekker, Nature 402 (6759), 273 (1999). 24. Y. Huang, X. F. Duan, Y. Cui, L. J. Lauhon, K. H. Kim, and C. M. Lieber, Science

294 (5545), 1313 (2001). 25. M. R. Diehl, S. N. Yaliraki, R. A. Beckman, M. Barahona, and J. R. Heath, Angew.

Chem. Int. Ed. 41 (2), 353 (2002). 26. P. C. Collins, M. S. Arnold, and P. Avouris, Science 292 (5517), 706 (2001). 27. J. T. Hu, L. S. Li, W. D. Yang, L. Manna, L. W. Wang, and A. P. Alivisatos, Science

292 (5524), 2060 (2001). 28. C. C. Tang, S. S. Fan, H. Y. Dang, P. Li, and Y. M. Liu, Appl. Phys. Lett. 77 (13),

1961 (2000).

21

29. S. Y. Li, C. Y. Lee, and T. Y. Tseng, J. Cryst. Growth 247 (3-4), 357 (2003). 30. R. S. Wagner and W. C. Ellis, Appl. Phys. Lett. 4 (5), 89 (1964). 31. A. M. Morales and C. M. Lieber, Science 279 (5348), 208 (1998). 32. X. F. Duan and C. M. Lieber, J. Am. Chem. Soc. 122 (1), 188 (2000). 33. X. F. Duan and C. M. Lieber, Adv. Mater. 12 (4), 298 (2000). 34. C. R. Martin, Science 266 (5193), 1961 (1994). 35. W. Q. Han, S. S. Fan, Q. Q. Li, and Y. D. Hu, Science 277 (5330), 1287 (1997). 36. E. W. Wong, B. W. Maynor, L. D. Burns, and C. M. Lieber, Chem. Mat. 8 (8), 2041

(1996). 37. H. J. Dai, E. W. Wong, Y. Z. Lu, S. S. Fan, and C. M. Lieber, Nature 375 (6534),

769 (1995). 38. C. G. Wu and T. Bein, Science 266 (5187), 1013 (1994). 39. Z. H. Wu, X. Y. Mei, D. Kim, M. Blumin, and H. E. Ruda, Appl. Phys. Lett. 81 (27),

5177 (2002). 40. J. R. Kim, H. M. So, J. W. Park, J. J. Kim, J. Kim, C. J. Lee, and S. C. Lyu, Appl.

Phys. Lett. 80 (19), 3548 (2002). 41. C. C. Tang, S. S. Fan, H. Y. Dang, P. Li, and Y. M. Liu, 77 (13), 1961 (2000). 42. Y. Huang, X. F. Duan, Q. Q. Wei, and C. M. Lieber, Science 291 (5504), 630 (2001). 43. X. F. Duan, Y. Huang, Y. Cui, J. F. Wang, and C. M. Lieber, Nature 409 (6816), 66

(2001). 44. P. A. Smith, C. D. Nordquist, T. N. Jackson, T. S. Mayer, B. R. Martin, J. Mbindyo,

and T. E. Mallouk, Appl. Phys. Lett. 77 (9), 1399 (2000). 45. V. V. Afanasev, A. Stesmans, and M. E. Twigg, Phys. Rev. Lett. 77 (20), 4206

(1996). 46. A. Ogura, Appl. Phys. Lett. 74 (15), 2188 (1999). 47. O. Potavin, S. Haendler, J. Jomaah, F. Balestra, and C. Raynaud, Solid-State

Electron. 46 (3), 367 (2002). 48. P. V. Pavlov and E. V. Shitova, Soviet Phys. Doklady 12 (1), 11 (1967). 49. M. Watanabe and A. Tooi, Japan J. Appl. Phys. 5, 737 (1966). 50. J. Blake, in Encyclopedia of Physical Science and Technology, edited by R. A.

Meyers (Academic Press, 2001), Vol. 14, pp. 805. 51. J.-P. Colinge, Silicon on Insulator Technology: Materials to VLSI, 2nd ed. (Kluwer

Academic Publishers, Boston, 1997). 52. G. K. Celler, P. L. F. Hemment, K. W. West, and J. M. Gibson, Appl. Phys. Lett. 48

(8), 532 (1986). 53. C. J. Griffin, J. A. Kilner, R. J. Chater, A. Statonbevan, K. J. Reeson, P. L. F.

Hemment, and J. R. Davis, Nucl. Instrum. Methods Phys. Res., Sect. B 39 (1-4), 215 (1989).

54. G. W. Neudeck, K. D. Merritt, and J. P. Denton, Microelectron. Eng. 36 (1-4), 391 (1997).

55. M. Madou, Fundamentals of Microfabrication. (CRC Press, Boca Raton, 1997). 56. L. F. Thompson, C. G. Wilson, and M. J. Bowden, Introduction to Microlithography:

Theory, Materials, and Processing. (American Chemical Society, Washington, D. C., 1983).

57. C. Vieu, F. Carcenac, A. Pepin, Y. Chen, M. Mejias, A. Lebib, L. Manin-Ferlazzo, L. Couraud, and H. Launois, Appl. Surf. Sci. 164, 111 (2000).

22

58. W. Chen and H. Ahmed, Appl. Phys. Lett. 62 (13), 1499 (1993). 59. M. A. Herman, Vacuum 32 (9), 555 (1982). 60. M. A. Herman and H. Sitter, Molecular Beam Epitaxy: Fundamentals and Current

Status. (Springer, New York, 1996). 61. P. L. F. Hemment, MRS Symp. Proc. 53, 207 (1986). 62. J. T. Hu, T. W. Odom, and C. M. Lieber, Accounts Chem. Res. 32 (5), 435 (1999). 63. W. Chen and H. Ahmed, Appl. Phys. Lett. 63 (8), 1116 (1993). 64. P. Davidsson, A. Lindell, T. Makela, M. Paalanen, and J. Pekola, Microelectron.

Eng. 45 (1), 1 (1999). 65. T. Miyashita, M. Nakaya, and A. Aoki, Supramol. Sci. 5 (3-4), 363 (1998). 66. C. N. Kim, D. W. Kang, E. R. Kim, and H. Lee, Synth. Met. 85 (1-3), 1407 (1997). 67. J. Walsh and C.-Y. Hong. 68. T. Isu, M. Hata, A. Watanabe, and Y. Katayama, J. Vac. Sci. Technol. B 7 (4), 714

(1989). 69. J. F. Ziegler, Ion Implantation: Science and Technology, 2nd ed. (Academic Press,

Inc., Boston, 1988). 70. B. Fultz and J. M. Howe, Transmission Electron Microscopy and Diffractometry of

Materials. (Springer, Berlin, 2001). 71. J. F. Qi, T. Matsumoto, and Y. Masumoto, Jpn. J. Appl. Phys. Part 2 - Lett. 40 (2B),

L134 (2001). 72. J.-R. Kim, H. M. So, J. M. Park, J.-J. Kim, J. Kim, C. J. Lee, and C. Lyu, 80 (19),

3548 (2002). 73. M. Delfino, M. Jaczynski, A. E. Morgan, C. Vorst, M. E. Lunnon, and P. Maillot, J.

Electrochem. Soc. 134 (8A), 2027 (1987). 74. A. Gangulee, F. M. Dheurle, V. A. Ranieri, and R. A. Fiorio, J. Vac. Sci. Technol. 16

(2), 156 (1979). 75. R. Gunzel, E. Wieser, E. Richter, and J. Steffen, J. Vac. Sci. Technol. B 12 (2), 927

(1994). 76. A. Nishida, K. Horai, and T. Fujita, Jpn. J. Appl. Phys. Part 1 - Regul. Pap. Short

Notes Rev. Pap. 28 (3), 384 (1989). 77. T. Fujihana, A. Sekiguchi, Y. Okabe, K. Takahashi, and M. Iwaki, Surf. Coat.

Technol. 51 (1-3), 19 (1992). 78. J. C. Johnson, H. Q. Yan, R. D. Schaller, L. H. Haber, R. J. Saykally, and P. D.

Yang, J. Phys. Chem. B 105 (46), 11387 (2001). 79. M. H. Huang, S. Mao, H. Feick, H. Q. Yan, Y. Y. Wu, H. Kind, E. Weber, R. Russo,

and P. D. Yang, Science 292 (5523), 1897 (2001). 80. L. J. Lauhon, M. S. Gudiksen, C. L. Wang, and C. M. Lieber, Nature 420 (6911), 57

(2002).

23