F2MC-8L FAMILY 8-BITMICROCONTROLLER APPLICATIONNOTE · The sample program uses the above resource to produce an inverter output for a 3-phase induction motor using a magnetic flux

FUJITSU SEMICONDUCTOR CONTROLLER MANUAL

CM25-00105-1E

F2MC-8L FAMILY8-BIT MICROCONTROLLER

APPLICATION NOTEVolume II

1. The products described in this manual and the specifications thereof may be changed without prior notice. To obtain up-to-date information and/or specifications, contact your Fujitsu sales representative or Fujitsu authorized dealer.

2. Fujitsu will not be liable for infringement of copyright, industrial property right, or other rights of a third party caused by the use of information or drawings described in this manual.

3. The contents of this manual may not be transferred or copied without the express permission of Fujitsu.

4. The products contained in this document are not intended for use with equipments which require extremely high reliability such as aerospace equipments, undersea repeaters, nuclear control systems or medical equipments for life support.

5. Some of the products described in this manual may be strategic materials (or special technology) as defined by the Foreign Exchange and Foreign Trade Control Law. In such cases, the products or portions thereof must not be exported without permission as defined under the Law.

1996 FUJITSU LIMITED Printed in Japan

PREFACE

This manual contains example application programs that you can refer to when developing systems using the F2MC-8L Family 8-Bit Fujitsu Flexible Microcontroller.

This manual is based on the F2MC-8L Family. Chapter 1 gives a basic outline and Chapter 2 and subsequent chapters describe the sample programs.

We hope that this manual may be of some help to users of the F2MC-8L Family.

1

CONTENTS

CHAPTER 1 INTRODUCTION ................................................................................... 1-3

CHAPTER 2 UART....................................................................................................... 2-32.1 Overview ............................................................................................................... 2-32.2 Sample Program Specification .............................................................................. 2-32.2.1 Summary Specification ......................................................................................... 2-32.2.2 Circuit Diagram ..................................................................................................... 2-42.2.3 Data Format ........................................................................................................... 2-42.2.4 Subroutine Calls .................................................................................................... 2-52.2.5 General Flowchart ................................................................................................. 2-72.2.6 Used Resource Registers and RAM in the Example ............................................. 2-92.3 Sample Program .................................................................................................. 2-112.3.1 Settings of Initial Register and RAM .................................................................. 2-112.3.2 Detailed Flowchart .............................................................................................. 2-14

CHAPTER 3 DTMF CONTROL.................................................................................. 3-33.1 Overview ............................................................................................................... 3-33.2 Sample Program Specifications ............................................................................. 3-33.2.1 Summary Specification ......................................................................................... 3-33.2.2 Circuit Block Diagram .......................................................................................... 3-43.2.3 Timing Diagram .................................................................................................... 3-43.2.4 General Flowchart ................................................................................................. 3-53.2.5 Used Resource Registers and RAM in the Example ............................................. 3-63.3 Sample Program .................................................................................................... 3-73.3.1 Settings of Initial Register and RAM ................................................................... 3-73.3.2 Detailed Flowchart .............................................................................................. 3-10

CHAPTER 4 SOFTWARE MODEM .......................................................................... 4-34.1 Overview ............................................................................................................... 4-34.2 Sample Program Specifications ............................................................................. 4-34.2.1 Summary Specification ......................................................................................... 4-34.2.2 Circuit Block Diagram .......................................................................................... 4-44.2.3 Data Format ........................................................................................................... 4-44.2.4 General Flowchart ................................................................................................. 4-54.2.5 Used Resource Registers and RAM in the Example ............................................. 4-64.3 Sample Program .................................................................................................... 4-84.3.1 Settings of Initial Register and RAM .................................................................... 4-84.3.2 Detailed Flowchart .............................................................................................. 4-13

2

CHAPTER 5 FUZZY LOGIC ....................................................................................... 5-35.1 Overview ............................................................................................................... 5-35.2 Sample Program Specifications ............................................................................. 5-35.2.1 Summary Specifications ........................................................................................ 5-35.2.2 General Flowchart ................................................................................................. 5-75.2.3 Used Resource Registers and RAM in the Example ............................................. 5-85.3 Sample Program .................................................................................................. 5-105.3.1 Settings of Initial Register and RAM .................................................................. 5-105.3.2 Detailed Flowchart .............................................................................................. 5-13

CHAPTER 6 UP/DOWN COUNTER ......................................................................... 6-36.1 Overview ............................................................................................................... 6-36.2 Sample Program Specifications ............................................................................. 6-36.2.1 Summary Specification ......................................................................................... 6-36.2.2 Circuit Block Diagram .......................................................................................... 6-46.2.3 General Flowchart ................................................................................................. 6-56.2.4 Used Resource Registers and RAM in the Example ............................................. 6-66.3 Sample Program .................................................................................................... 6-86.3.1 Settings of Initial Register and RAM ..................................................................... 6-8

CHAPTER 7 INVERTER CONTROL......................................................................... 7-37.1 Overview ............................................................................................................... 7-37.2 Sample Program Specifications ............................................................................. 7-37.2.1 Summary Specification ......................................................................................... 7-37.2.2 Circuit Block Diagram .......................................................................................... 7-77.2.3 General Flowchart ................................................................................................. 7-87.2.4 Used Resource Registers and RAM in the Example ............................................. 7-97.3 Sample Program .................................................................................................. 7-117.3.1 Settings of Initial Register and RAM .................................................................. 7-117.3.2 Detailed Flowchart .............................................................................................. 7-13

CHAPTER 8 REALTIME I/O....................................................................................... 8-38.1 Overview ............................................................................................................... 8-38.2 Sample Program Specifications ............................................................................. 8-38.2.1 Summary Specification ......................................................................................... 8-38.2.2 Circuit Block Diagram .......................................................................................... 8-48.2.3 Data Format ........................................................................................................... 8-48.2.4 General Flowchart ................................................................................................. 8-58.2.5 Used Resource Registers and RAM in the Example ............................................. 8-78.3 Sample Program .................................................................................................... 8-98.3.1 Settings of Initial Register and RAM .................................................................... 8-98.3.2 Detailed Flowchart .............................................................................................. 8-13

3

CHAPTER 9 EXAMPLE D/A AND VFD APPLICATION CIRCUITS ................... 9-39.1 Example D/A Application Circuits ....................................................................... 9-39.1.1 PWM Method ........................................................................................................ 9-39.1.2 Resistance Method ................................................................................................ 9-69.2 Example VFD Application Circuit ........................................................................ 9-79.2.1 Example VFD Application Circuit ........................................................................ 9-7

1-3

Chapter 1:Introduction

UARTThe F2MC-8L Family have internal UART resources for communication protocols such as RS-232C(which is widely used as a serial communications interface in personal computers).

Two-wire high speed data communications can be implemented using this resource.

DTMF ControlSome F2MC-8L Family products have internal DTMF generators suitable for control of telephone linesand similar.

The MB89170/170A and MB89890 Family have internal DTMF generators and can output continuousDTMF and signal tones. Besides, all CCITT tones (0 - 9, *, #, and A - D) can be output.

Software ModemThe MB89890 Family has an internal modem signal output circuit and modem timer (pulse width counttimer).

These resources, together with a simple external circuit, enable digital signals to be converted andtransmitted as analog signals. Similarly, a received analog signal can be converted back to the originaldigital signal.

Fuzzy LogicThe MB94140 is a fuzzy controller that uses the same core as the F2MC-8L Family.

The fuzzy controller uses the F2RU-6 fuzzy logic engine. This engine consists of a grade operation unit,membership function memory, min-MAX operation unit, de-fuzzify unit, CPU-I/O unit, and control unit.The engine can perform fuzzy logic operations for various numbers of I/O and fuzzy rules.

Also, table-lookup type fuzzy logic processing can be implemented on the F2MC-8L Family (which do nothave a fuzzy logic engine). Although adjustment of rules and membership functions is more difficult forthis type of fuzzy logic processing, it is a practical option when adjustment is not required.

Up/Down CountersSome F2MC-8L Family products have internal up/down counter resources.

Up/down counters are suitable as rotary encoder counters or similar. The counters enable easyimplementation of applications such as monitoring and control of rotational direction and number ofrevolutions and calculating rotational speed.

1-4 Chapter 1: Introduction

Inverter ControlThe MB89860/850 Family have internal timer units suitable for inverter control. The timer in the timerunit can be used in either up/down mode, and an inverter output can be implemented by setting a valueobtained from a magnetic flux control PWM algorithm as the compare value.

The timer unit output pin outputs "H" when the timer unit's count is greater than the compare value, and"L" when the count is less than the compare value. An interrupt is generated when the timer value goes to00h. Use the interrupt to calculate the next compare value.

The sample program uses the above resource to produce an inverter output for a 3-phase induction motorusing a magnetic flux control PWM algorithm.

Real-Time I/OSome F2MC-8L Family products have internal real-time I/O.

Real-time I/O consists of 16-bit timers, input capture, and output compare. These can be used to facilitatemeasurement of periods (or frequencies) and pulse widths as well as setting of port outputs.

Example D/A and VFD Application CircuitsMicrocontrollers, not necessarily the F2MC-8L Family, sometimes require analog signals to controlexternal devices. However, as microcontrollers cannot output analog signals directly, it is sometimesnecessary to use an external circuit to convert a digital signal output to an analog signal. This conversionto an analog signal is performed by a D/A converter.

Also, some F2MC-8L Family products have internal high withstand voltage ports. Vacuum fluorescentdisplay tubes (VFD) are widely used in non-portable AV equipment and other household appliances. Asdriving a VFD requires a high voltage (up to 30 V), the high withstand voltage ports are used for thispurpose.

2.1 Overview

2-3

Chapter 2:UART

2.1 Overview

The F2MC-8L Family have internal UART resources for communication protocols such as RS-232C(which is widely used as a serial communications interface in personal computers).

High speed data communications using two signal lines can be implemented using this resource.

2.2 Sample Program Specification

2.2.1 Summary SpecificationThe sample program performs data communications using two signal lines (transmit and receive).

The number of bits, number of stop bits, and parity can be independently specified.

Transmit and receive buffers are provided with reserved capacity of 10 bytes each.

The example also shows how to call routines from a C language program.

(1) Target microcontroller

MB89630 FamilyMain clock = 10 MHz

(2) Used resources

• UART

(3) Used ports (See circuit diagram)

Input: P32/UI1Output: P31/UO1

(4) UART specifications

• Communications speed: 9600 bps

• Protocol: Full duplex

• Number of data bits: 7 or 8 bits (selectable)

• Number of stop bits: 1 or 2 bits (selectable)

• Parity bit: None, odd, or even (selectable)


2-4 Chapter 2: UART

2.2.2 Circuit Diagram

Fig. 2-1 Circuit Diagram

2.2.3 Data Format

Fig. 2-2 Signal Format

MB89630

VCC

VSS

RST

P32/UI1

P31/UO1

X0 X1

10.00MHz

VCC

Receive data

Transmit data

START b0 b1 b2 b3 b4 b5 b6 b7 STOP

START b0 b1 b2 b3 b4 b5 b6 b7

START b0 b1 b2 b3 b4 b5 b6

START b0 b1 b2 b3 b4 b5 b6 P

STOPSTOPP

STOP

STOPSTOP

• 8 data bits, 1 stop bit, no parity

• 8 data bits, 2 stop bits, even or odd parity

• 7 data bits, 1 stop bit, no parity

• 7 data bits, 2 stop bits, even or odd parity


2-5

2.2.4 Subroutine Calls• UART initialization: _UART_INITIAL

(1) Input parameter Initial data

(2) Calling sequenceMOV A, #B' 0000**** ← Initial dataPUSHW ACALL _UART_INITIALPOPW A

• Fetch received data: _UART_RECEIVE

(1) Output parameter EP: Received data(2) Calling sequence

CALL _UART_RECEIVEMOVW A, EP← Move received data to accumulator.

• Set transmit data: _UART_TRANS

(1) Input parameter Transmit data(2)Output parameter Transmit buffer write status 1: Successfully written(3)Calling sequence

MOV A, #H' ** ← Transmit dataPUSHW ACALL _UART_TRANSPOPW AMOVW A, EP ← Copy write status to accumulator.

0 0 0 0 - - - -

7 6 5 4 3 2 1 0

Number of data bits 0: 7 bits 1: 8 bits

Parity 00: None 01: Odd 10: Even

Number of stop bits 0: 1 stop bit 1: 2 stop bits

Initial data


2-6 Chapter 2: UART

• Fetch UART status: _UART_STATUS

(1)Output parameter EP: UART status

(2)Calling sequenceCALL _UART_STATUSMOVW A, EP← Move UART status to accumulator.

- - - 0 0 0 - -

7 6 5 4 3 2 1 0

Receive data present or not?1: Receive data present

Transmit buffer 1: Full

Parity error 1: Parity error

UART status

Framing error 1: Framing error

Overrun error 1: Overrun error


2-7

2.2.5 General Flowchart

Fig. 2-3 General Flowchart

Main routine

UART receive complete interrupt

No

Yes

Initial setting

Receive error occurred?

Data processing

Store received data Halt reception

Store error status

End

UART transmit complete interrupt

Transmit data present?

Data transmission com-plete Data transmission

End

Yes

No


2-8 Chapter 2: UART


UART initial setting

Set UART operation mode

Set initial data

End

Fetch transmit and receive status


Check for errors

End

Fetch receive data Set transmit data

Start transmission

Set dataReturn receive data

End

End


2-9

2.2.6 Used Resource Registers and RAM in the Example(1) Resources

• UART resource

(2) List of used resource registers

Table 2-1 Used Resource Registers

Address Register Register Contents

07H SYCC System clock control register

0DH PDR3 Port 3 data register

0EH DDR3 Port 3 I/O direction register

2DH SMC UART serial mode control register

2EH SRC UART rate control register

2FH SSD UART serial status and data register

30H SODR UART serial output data register

30H SIDR UART serial input data register

7DH ILR2 Interrupt level setting register 2

7EH ILR3 Interrupt level setting register 3


2-10 Chapter 2: UART

(3) RAM allocation

(4) Flag contents

Table 2-2 RAM Allocation

Address Symbol Function

80H WORK Work area

81H to 8AH RECEIVE_BUFFER Receive buffer

8BH to 94H TRANS_BUFFER Transmit buffer

95H 96H

PRECEIVE_WRITE +1

Receive data write pointer

97H 98H

PRECEIVE_READ+1

Receive data read pointer

99H 9AH

PTRANS_WRITE +1

Transmit data write pointer

9BH

9CH

PTRANS_READ +1

Transmit data read pointer

9DH STATUS UART status area

9EH MODE UART mode area

Table 2-3 9DH Flag Contents

Bit Symbol Function

0 F_RCVBUFF Receive data present or not? 1: Present

1 F_TRANSBUFF Transmit buffer status 1: Buffer full

5 F_EROVR Overrun error flag 1: Overrun error

6 F_ERFR Framing error flag 1: Framing error

7 F_ERPRTY Parity error flag 1: Parity error

Table 2-4 9EH Flag Contents

Bit Symbol Function

0 F_DTL Number of data bits 0: 7 bits 1: 8 bits

1 F_PRTY0 Parity 00: None01: Odd10: Even2 F_PRTY1

3 F_STOP Number of stop bits 0: 1 stop bit 1: 2 stop bits

2.3 Sample Program

2-11

2.3 Sample Program

2.3.1 Settings of Initial Register and RAM (1) Settings of I/O port

(2) Settings of system clock control register

0 0 0 0 0 - 1 0

7 6 5 4 3 2 1 0

P31: For transmit data output ("H" level output)

P32: For receive data input ("0" or "1")

0 0 0 0 0 0 1 0

7 6 5 4 3 2 1 0

∗ ∗ ∗ ∗ ∗∗

∗ ∗ ∗ ∗ ∗∗P31: Set as output port

P32: Set as input port

∗ As these ports are unused, set as inputs.

PDR3

DDR3

0 0 0 1 1 1 1 1

7 6 5 4 3 2 1 0

∗ ∗∗CS1, CS0: System operating clock 4/fch = 0.4 µs

SCS: Set the system clock as the main clock.

WT1, WT0: Oscillation stabilization time 218/fch = 26.2 ms

∗ Set unused bits to "0".

SYCC

2.3 Sample Program


(3) Settings of UART serial mode control register

(4) Settings of UART serial rate control register

- - - - 1 0 0 1

7 6 5 4 3 2 1 0

UOE: UART output enable

UCKE: Use as a standard port

∗

∗Set unused bits to "0".

SMC

SMDE: Set to "asynchronous

MC1, MC0: Set during initialization0 = 2 bits, 1 = 1 bit

MC1 MC0 Data bits

0 087

11

10

9

SBL: Set during initialization0 = 2 bits, 1 = 1 bit

PEN: Set during initialization0 = No parity, 1 = Use parity

0 0 0 1 1 0 0 0

7 6 5 4 3 2 1 0

∗∗RC2, RC1, RC0: 104/9615 (µs/baud)

SC1, SC0: Select dedicated baud rate

CR: Not applicable when dedicated baud rate selected.


SRC

2.3 Sample Program

2-13

(5) Settings of UART serial status and data register

(6) Settings of interrupt level setting register

0 0 1 0 1 0 - 1

7 6 5 4 3 2 1 0

RD8/RP: Set during initialization.Not used when parity is off.Parity input value when parity is on.

TD8/TP: Set during initialization.Valid only when parity is on.0 = Odd parity, 1 = Even parity

∗Set unused bits to "0".

SSD

PSEL: Use P30 - P32

TIE: Transmit interrupt disabled (after a reset)

TDRE: Set output buffer empty

RDTF, ORFE: Read-only

RIE: Receive interrupt enabled

0 0 1 1 1 1 1 1

7 6 5 4 3 2 1 0

∗∗L71, L70: Set UART receive interrupt level to 0.

L81, L80: Set UART transmit interrupt level to 2.


ILR2

1 1 1 1 1 1 0 0

7 6 5 4 3 2 1 0

ILR3

∗ ∗ ∗ ∗

∗∗ ∗ ∗ ∗ ∗

2.3 Sample Program


2.3.2 Detailed Flowchart

Fig. 2-5 Flowchart

RESET

Yes

Set stack pointer

Successfully written?

_INITIALInitial settings

No

Enable interrupts

PRC_DATATransmit and receive

data processing

PRC_DATA

_UART_STATUSFetch transmit and

receive status

Receive data present?

_UART_RECEIVEFetch receive data

_UART_TRANSSet transmit data

Receive error?

Yes

No

Error processingSet "E"

in transmit data

RET

MAIN

Transmit and receive data processing

No

Yes

2.3 Sample Program

2-15

Fig. 2-6 Flowchart

_INITIAL

Disable interrupts

_UART_INITIALInitial UART settings

Set register bank pointer

Set interrupt level

Clear RAM

Set system operating clock(4/fch = 0.40 µs)

Set I/O ports

RET

Initial settings

2.3 Sample Program


Fig. 2-7 Flowchart

_UART_INITIAL

Set UART register

Set UART mode

Clear transmit and receive buffers

Clear transmit and receive buffers

RET

Set number of data bits

Set number of stop bits

Initial UART settings

Enable UART receive interrupt

Set parity

2.3 Sample Program

2-17

Fig. 2-8 Flowchart

_UART_RECEIVE _UART_TRANS

Save transmit dataUpdate save pointer

Start transmissionEnable transmit

interrupt

Set return valueto 01H

RET

RET

Fetch received data

No

Yes

Set transmit data

Mask error section of

STATUS

Store error section ofSTATUS

Clear error statuses

Return stored statuses

Receive datapresent?

Receive error?

Check UARTbuffer state

Return UART status

RET

_UART_STATUS

No

Yes

No

YesNo

Yes

Set return valueto FFH

Receive datapresent?

Return received dataUpdate read data

Set return valueto 00H

Space available in transmit buffer?


2.3 Sample Program


Fig. 2-9 Flowchart

_UART_INT_RECEIVE

No

Yes

Save A and T registers

Receive error occurred?

Read SSD

Check for parity error

UART receive complete interrupt

No

RET I

Set parity error flagCheck for framing error

Parity error?

Framing error?

Check for overrun error

Overrun error?

Set framing error flag

Set overrun error flag

Read SIDR

Space in buffer?

Read SIDR

Save received dataUpdate save pointer

Restore A and T registers

Yes

Yes

Yes

Yes

No

No

No

No

2.3 Sample Program

2-19

Fig. 2-10 Flowchart

_UART_INT_TRANS

Yes


Transmit data present?

Read SSD

UART transmit com-plete interrupt

No

RET I

Transmission completeDisable transmit

complete interrupt

Transmit dataUpdate read pointer


2.3 Sample Program


NAME UART;*****************************************;* Sample UART Program *;*****************************************;******************************;* Resource Definition *;******************************RES630 DIRSEG;

ORG 0007HSYCC RB 0 ; System clock control registerCS0 RBIT 1 ; System clock selection bitCS1 RBIT 1 ; System clock selection bitSCS RBIT 1 ; System clock select bitWT0 RBIT 1 ; Oscillation stabilization time selection bitWT1 RBIT 1 ; Oscillation stabilization time selection bit

RBIT 1 ; Dummy bitRBIT 1 ; Dummy bit

SCM RBIT 1 ; System clock monitor bit;

ORG 000DHPDR3 RB 1 ; Port 3 data registerDDR3 RB 1 ; Port 3 direction register;

ORG 002DHSMC RB 0 ; Serial mode control registerUOE RBIT 1 ; Enable UART outputUCKE RBIT 1 ; Enable UART clock

RBIT 1 ; Dummy bitSMDE RBIT 1 ; Synchronous or asynchronous transmissionMC0 RBIT 1 ; Mode controlMC1 RBIT 1 ; Mode controlSBL RBIT 1 ; Number of stop bitsPEN RBIT 1 ; Enable parity;

ORG 002EHSRC RB 0 ; Serial rate control registerRC0 RBIT 1 ; Baud rate selectionRC1 RBIT 1 ; Baud rate selectionRC2 RBIT 1 ; Baud rate selectionSCS0 RBIT 1 ; Clock selectSCS1 RBIT 1 ; Clock selectCR RBIT 1 ; Clock rate


;ORG 002FH

SSD RB 0 ; Serial status and data registerRD8_RP RBIT 1 ; ParityTD8_TP RBIT 1 ; ParityPSEL RBIT 1 ; Port selection bit

2.3 Sample Program

2-21

RIE RBIT 1 ; Receive interrupt request enable bitTIE RBIT 1 ; Transmit interrupt enable bitTDRE RBIT 1 ; SODR status bitORFE RBIT 1 ; Overrun or framing error bitRDRF RBIT 1 ; SIDR status bit;

ORG 0030HSIDR RB 0 ; Serial input data registerSODR RB 1 ; Serial output data register;

ORG 007DHILR2 RB 1 ; Interrupt level setting register 2ILR3 RB 1 ; Interrupt level setting register 3RES630 ENDS;*************************;* RAM Definition *;*************************

SSEGPUBLIC STACK_TOP ; Stack definition

RW 32STACK_TOP RW 0

ENDS;RAM DIRSEG ABS

ORG 80H;WORK RB 1 ; Work area;RECEIVE_BUFFER RB 10 ; Receive bufferTRANS_BUFFER RB 10 ; Transmit buffer;PRECEIVE_WRITE RW 1 ; Receive data write pointerPRECEIVE_READ RW 1 ; Receive data read pointer;PTRANS_WRITE RW 1 ; Transmit data write pointerPTRANS_READ RW 1 ; Transmit data read pointer;STATUS RB 0 ; UART status save areaF_RCVBUFF RBIT 1 ; Receive data presentF_TRNSBUFF RBIT 1 ; Transmit buffer full

RBIT 1 ; Dummy bitRBIT 1 ; Dummy bitRBIT 1 ; Dummy bit

F_EROVR RBIT 1 ; Overrun errorF_ERFR RBIT 1 ; Framing errorF_ERPRTY RBIT 1 ; Parity error;MODE RB 0 ; Mode data areaF_DTL RBIT 1 ; Number of data bitsF_PRTY0 RBIT 1 ; Parity

2.3 Sample Program


F_PRTY1 RBIT 1 ; ParityF_STOP RBIT 1 ; Number of stop bits

RBIT 1 ; Dummy bitRBIT 1 ; Dummy bitRBIT 1 ; Dummy bitRBIT 1 ; Dummy bit

;RAM ENDS;;*******************************;* Constant Definitions *;*******************************U7BIT EQU 00000000BU8BIT EQU 00000001BUPNON EQU 00000000BUPODD EQU 00000010BUPEVEN EQU 00000100BUSTOP1 EQU 00000000BUSTOP2 EQU 00001000B;PROG CSEG

PUBLIC RESET;**********************;* Initial Settings *;**********************RESET:

MOVW SP,#STACK_TOP;

MOVW A,#0030HMOVW PS,A

;CALL _INITIAL ; Initial setting processing

;SETI

;************************;* Main Routine *;************************MAIN:

CALL PRC_DATA ; Transmit and receive data processing

JMP MAINPROG ENDS;;*****************************;* Initial Setting Processing*;*****************************PROG CSEG

PUBLIC _INITIAL_INITIAL:

CLRI ; Disable interrupts;

2.3 Sample Program

2-23

MOV SYCC,#00011111B ; Set system operating clock (4/FCH = 0.40 µs);

MOV PDR3,#00000010B ; Set UART port I/OMOV DDR3,#00000010B

;MOVW A,#0080H ; Clear RAM

_INITIAL_010:MOVW A,#0000HXCHW A,TMOVW @A,TINCW AINCW AMOVW A,#0250HXCHW A,TCMPW ABNC _INITIAL_010

;; Initialize UART (8 data bits, 1 stop bit, no parity)MOV A,#U8BIT or USTOP or UPNONPUSHW ACALL _UART_INITIALPOPW A

;; Set interrupt levelMOV ILR2,#00111111B ; UART receive interrupt:LEVEL=1 MOV ILR3,#11111110B ; UART receive interrupt:LEVEL=2

;RET

PROG ENDS;*******************************;* Name PRC_DATA *;* Function Data handling *;*******************************PROG CSEG

PUBLIC PRC_DATAPRC_DATA:

CALL _UART_STATUS ; Fetch transmit and receive statusesMOVW A,EPAND A,#00000001BBZ PRC_DATA_010 ; No

;CALL _UART_RECEIVE ; Fetch receive dataMOVW A,EPMOV WORK,AJMP PRC_DATA_020

;PRC_DATA_010:

MOVW A,EP ; Receive error?AND A,#11100000BBZ PRC_DATA_030 ; NoMOV A,#'E' ; Set error code

2.3 Sample Program


MOV WORK,A;PRC_DATA_020:

MOV A,WORKPUSHW ACALL _UART_TRANS ; Set transmit dataPOPW AMOVW A,EP

CMP A,#0 ; Successfully written?BZ PRC_DATA_020 ; No

;PRC_DATA_030:

RETPRG ENDS;*******************************;* Name _UART_INITIAL *;* Function Initialize UART *;*******************************UART CSEG

PUBLIC _UART_INITIAL_UART_INITIAL:

PUSHW IXMOVW A,SPMOVW IX,A

;MOV SRC,#00011000B ; Set SRC registerMOV SSD,#00100000B ; Set SSD register

;MOV SODR,#11111111B ; Set SODR register (Set output data to FFH)

;MOV A,@IX+5 ; Save UART modeMOV MODE,A

;MOVW A,#TRANS_BUFFER ; Clear transmit and receive buffersMOVW PTRANS_READ,AMOVW PTRANS_WRITE,AMOVW A,#RECEIVE_BUFFERMOVW PRECEIVE_READ,AMOVW PRECEIVE_WRITE,A

;MOV STATUS,#0 ; Initialize UART status

;; Set SMC register ; Set number of bitsMOV A,#00001001BBBC F_DTL,U_INIT_010OR A,#00010000B ; Set data length to 8 bits

U_INIT_010:;

; Set parity

2.3 Sample Program

2-25

BBS F_PRTY0,U_INIT_020 ; Use parityBBC F_PRTY1,U_INIT_035 ; Do not use parity

U_INIT_020:OR A,#10000000B; Set parity on

;BBC F_DTL,U_INIT_025 ; Check number of bitsOR A,#00100000B ; Set data length to 9 bitsJMP U_INIT_030

U_INIT_025:OR A,#00010000B ; Set data length to 8 bits

U_INIT_030:; Check even or oddCLRB TD8_TPBBS F_PRTY0,U_INIT_035 ; Even?SETB TD8_TP

;U_INIT_035:;

; Set number of stop bitsBBS F_STOP,U_INIT_040 ; 1 stop bit?OR A,#01000000B ; Set 1 stop bit

U_INIT_040:MOV SMC,A ; Set SMC register

;SETB RIE ; Enable UART receive interrupt

;MOVW A,IXMOVW SP,A

POPW IXRET

UART ENDS;********************************;* Name _UART_TRANS *;* Function Set transmit data *;********************************UART CSEG

PUBLIC _UART_TRANS_UART_TRANS:


;MOVW A,#TRANS_BUFFER+9 ; Check transmit buffer spaceMOVW A,PTRANS_WRITEINCW ACMPW ABNC U_TRANS_010 ; If end of buffer, set to topMOVW A,#TRANS_BUFFER ; Set buffer top address

U_TRANS_010:;

2.3 Sample Program


MOVW A,PTRANS_READ ; Check if space available in bufferCMPW ABZ U_TRANS_020 ; Is space available in buffer?

;XCHW A,T ; Set transmit dataMOVW EP,AMOV A,@IX+5MOV @EP,A

;MOVW A,EP ; Update write pointerMOVW PTRANS_WRITE,A

;MOVW EP,#1 ; Transmit OK

;SETB TIE ; Enable transmit complete interrupt

;JMP U_TRANS_030

;U_TRANS_020:

MOVW EP,#0 ; Transmit failed;U_TRANS_030:

MOVW A,IXMOVW SP,APOPW IXRET

UART ENDS;*********************************;* Name _UART_RECEIVE*;* Function Fetch receive data *;*********************************UART CSEG

PUBLIC _UART_RECEIVE_UART_RECEIVE:

MOVW A,PRECEIVE_WRITE ; Is there data in the buffer?MOVW A,PRECEIVE_READCMPW ABZ U_RCV_020 ; No

;; Receive data presentMOVW A,#RECEIVE_BUFFER+9 ; Update read pointerMOVW A,PRECEIVE_READINCW ACMPW ABNC U_RCV_010MOVW A,#RECEIVE_BUFFER

U_RCV_010:PUSHW A

;MOV A,@A ; Read data

2.3 Sample Program

2-27

MOVW EP,A;

POPW A ; Update read pointerMOVW PRECEIVE_READ,AJMP U_RCV_030

;U_RCV_020:

MOVW EP,#00FFH ; No dataU_RCV_030:

RETUART ENDS;********************************;* Name _UART_STATUS *;* Function Check UART status *;********************************UART CSEG

PUBLIC _UART_STATUS_UART_STATUS:


;MOV A,STATUSAND A,#11111100B ; Clear buffer statusMOV STATUS,A

;MOVW A,PRECEIVE_WRITE ; Receive data present?MOVW A,PRECEIVE_READCMPW ABZ U_STATUS_010 ; No

;MOV A,STATUS ; Set the "receive data present" statusOR A,#00000001BMOV STATUS,A

;U_STATUS_010:

MOVW A,#TRANS_BUFFER+9 ; Check if space is available in transmit bufferMOVW A,PTRANS_WRITEINCW ACMPW ABNC U_STATUS_020MOVW A,#TRANS_BUFFER

U_STATUS_020:MOVW A,PTRANS_READ ; Buffer Full?CMPW ABNZ U_STATUS_030 ; No

;MOV A,STATUS ; Set transmit buffer fullOR A,#00000010BMOV STATUS,A

;

2.3 Sample Program


U_STATUS_030:MOV A,STATUS ; Is receive data present?AND A,#00000001BBZ U_STATUS_040 ; No

;MOV A,STATUS ; If receive data is present, return the "no

error" statusAND A,#00000011BMOVW EP,AJMP U_STATUS_050

;U_STATUS_040:

MOV A,STATUS ; Set the statusMOVW EP,A

;MOV A,STATUS ; Is there a receive error?AND A,#11100000B

BZ U_STATUS_050 ; No;

AND A,#00011111B ; Clear error statusMOV STATUS,A

;U_STATUS_050:

MOVW A,IXMOVW SP,APOPW IXRET

UART ENDS;**********************************************;* Name _UART_INT_RECEIVE *;* Function UART receive complete interrupt *;**********************************************UART CSEG

PUBLIC _UART_INT_RECEIVE_UART_INT_RECEIVE:

PUSHAT ; Save A and T registersPUSHW IX ; Save IX register

;MOV A,SSD ; Read SSD (to clear interrupt source, etc.)

;MOV A,STATUS ; Is there a receive error?AND A,#11100000BBNZ U_INT_RCV_060 ; Yes

;; Parity error checkBBC PEN,U_INT_RCV_030 ; Is parity on?

;BBC TD8_TP,U_INT_RCV_010 ; Even parity? BBS RD8_RP,U_INT_RCV_030 ; No parity errorJMP U_INT_RCV_020 ; Parity error

2.3 Sample Program

2-29

;U_INT_RCV_010:

BBC RD8_RP,U_INT_RCV_030 ; No parity errorU_INT_RCV_020:

SETB F_ERPRTY ; Parity errorJMP U_INT_RCV_060 ; To halt reception processing

;U_INT_RCV_030:

; Framing error checkAND A,#11000000BCMP A,#01000000B ; Framing error?BNZ U_INT_RCV_040 ; NoSETB F_ERFR ; Framing errorJMP U_INT_RCV_060 ; To halt reception processing

;U_INT_RCV_040:

; Overrun error checkCMP A,#11000000B ; Overrun error?BNZ U_INT_RCV_070 ; No

U_INT_RCV_050:SETB F_EROVR ; Overrun error

U_INT_RCV_060:MOV A,SIDRJMP U_INT_RCV_090

;U_INT_RCV_070:

MOVW A,#RECEIVE_BUFFER+9 ; Check for receive buffer spaceMOVW A,PRECEIVE_WRITEINCW ACMPW ABNC U_INT_RCV_080

;MOVW A,#RECEIVE_BUFFER

;U_INT_RCV_080:

MOVW A,PRECEIVE_READ ; Full?

CMPW ABZ U_INT_RCV_050 ; Yes

;XCHW A,T ; Update write pointerMOVW PRECEIVE_WRITE,AMOVW IX,A

;MOV A,SIDR ; Read received dataMOV @IX,A ; Save

;U_INT_RCV_090:

POPW IX ; Restore IX registerPOPAT ; Restore A and T registersRETI

2.3 Sample Program


UART ENDS

;***********************************************;* Name _UART_INT_TRAN *;* Function UART transmit complete interrupt *;***********************************************UART CSEG

PUBLIC _UART_INT_TRANS_UART_INT_TRANS:

PUSHAT ; Save A and T registers;

MOV A,SSD ; Read SSD (to clear interrupt source, etc.)MOVW A,PTRANS_READ ; Transmit data present?MOVW A,PTRANS_WRITECMPW ABZ U_INT_TRANS_020 ; No

;; Transmit data presentMOVW A,#TRANS_BUFFER+9 ; Read transmit dataMOVW A,PTRANS_READINCW ACMPW ABNC U_INT_TRANS_010 ; If end of buffer, set to topMOVW A,#TRANS_BUFFER ; Set buffer top address

U_INT_TRANS_010:PUSHW AMOV A,@A ; Read transmit dataMOV SODR,A ; Set transmit dataPOPW AMOVW PTRANS_READ,A ; Update read pointerJMP U_INT_TRANS_030

;U_INT_TRANS_020:

CLRB TIE ; Disable transmit complete interrupt;U_INT_TRANS_030:

POPAT ; Restore A and T registers;

RETI;UART ENDS;*******************************; Vector addresses *;*******************************VECTOR CSEG ABS

ORG 0FFEAHDW _UART_INT_TRANS ; IRQ8 (UART transmit interrupt)DW _UART_INT_RECEIVE ; IRQ7 (UART receive interrupt)

;ORG 0FFFDH

2.3 Sample Program

2-31

DB 00H ; Mode data (Single chip mode)DW RESET ; Reset vector

VECTOR ENDSEND

3.1 Overview

3-3

Chapter 3: DTMF Control

3.1 Overview

Some F2MC-8L Family products have internal DTMF generators suitable for control of telephone linesand similar.

The MB89170/170A and MB89890 Family have internal DTMF generators and can output continuousDTMF and signal tones. All CCITT tones (0 to 9, *, #, and A to D) can be output.

3.2 Sample Program Specifications

3.2.1 Summary Specification(1) Target microcontroller

MB89170A FamilyMain clock = 3.58 MHzSubclock = 32.768 kHz

(2) DTMF Control

Outputs the DTMF signal corresponding to the dialing data (0 to 9, *, #, and A to D) input by dial keyinput processing.

The DTMF signal, which combines high and low frequency components, is output from the DTMF pin.The DTMF signal is output continuously for 100 ms, then halted for 100 ms (the output OFF period).

(3) Used ports (See circuit block diagram)

Input: P00/LI0 to P03/LI3 (Dial key input ports)Output: P20 to P23 (Key scan select ports)

DTMF (DTMF signal output pin)


3-4 Chapter 3: DTMF Control

3.2.2 Circuit Block Diagram

Fig. 3-1 Hardware Structure

3.2.3 Timing Diagram

Fig. 3-2 Timing Diagram for the Dial Keys and DTMF Signal Output

P00/LI0

P02/LI2

P03/LI3

P20

P21

P22

P23

DTMF

P01/LI1

MB89170/170A

X0A X1A X0 X1

RST

vss

Vcc

Vcc

3.58MHz32.768

kHZ

DTMF signal output

1 2 3

4 5 6

7 8 9

A

B

C

D* 0 #

0 key

9 key

4 key

DTMF "4" signal continuously output


Output OFF


OFFON

OFFONOFFON

DTMF output pinOutput OFF

100msec 100msec100msec100msec100msec


3-5



Main routine

DTMF output timer monitoring

Initial settings Timer up for output ON time?

No

Dial key input processing

DTMF output control processing


Set DTMF output OFF request flag

Timer up for output OFF time?

Set DTMF output complete flag

DTMF output controlprocessing

DTMF output request?

Output DTMF signal corresponding to

dial key

Start output ON period timer

Halt DTMF output

Start output OFF period timer

Set DTMF output enable state

DTMF output OFF request?

DTMF output complete?

End

End

Yes

No

No

No

No

Yes

Yes

Yes

Yes




• Timebase timer (for DTMF output timing)

• DTMF generator (DTMF output)


(3) RAM allocation

(4) Flag contents



00H PDR0 Port 0 data register

01H DDR0 Port 0 I/O direction register



0AH TBTC Timebase timer control register

20H DTMC DTMF control register

21H DTMD DTMF data register



80H FLAG Flag area

81H DTM_CODE DTMF control code area

82H KEY_DATA Dial key code save area

83H ON_TIME DTMF output ON time count area

84H OFF_TIME DTMF output OFF time count area

Fig. 3-3 Contents of Address 80H

Bit Symbol Function

0 F_DTMFOUT DTMF output request flag 1: Upon output request

1 F_DTMFOFF DTMF output OFF request flag 1: Upon output OFF request

2 F_DTMFEND DTMF output complete flag 1: Upon output complete

3 F_ONTIMACTTimer count request flag for the DTMF output ON period

1: Upon timer count request

4 F_OFTIMACTTimer count request flag for the DTMF output OFF period

1: Upon timer count request

3.3 Sample Program

3-7

3.3 Sample Program


(2) Settings of system clock control register

(3) Settings of timebase timer control register

0 0 0 0 0 0 0 0

7 6 5 4 3 2 1 0

P00 - P03: Set as input ports

1 1 1 1 1 1 1 1

7 6 5 4 3 2 1 0

* * **

P20 - P27: Output "H"ports


DDR0

PDR2

0 0 0 0 0 1 1 1

7 6 5 4 3 2 1 0

* **CS1, CS0: System operating clock 4/fch = 1.11 µs

SCS: Set the main clock as the system clock. (3.58 MHz)

WT1, WT0: Oscillation stabilization time 23/fch = 0 ms

SYCC


0 0 0 0 0 0 1 0

7 6 5 4 3 2 1 0

* **TBR: Clear timebase timer

TBC1, TBC0: Set interval time (9.15 ms)

TBIE: Disable interval interrupt

TBTC

TBOF: Clear overflow flag for interval timer

3.3 Sample Program


(4) Settings of DTMF control register

(5) Settings of flag area

(6) Setting for the DTMF control code area

(7) Setting for the dial key code save area

0 0 0 0 0 0 0 0

7 6 5 4 3 2 1 0

* **OUTE: Set source oscillation frequency to 3.58 MHz

RDIS: Enable generation of high-frequency-group tones

CDIS: Enable generation of low-frequency-group tones

DTMF

CSEL: Disable DTMF signal output

*



0 0 0 0 0 0 0 0

7 6 5 4 3 2 1 0

* **F_DTMFOUT: Clear DTMF output request flag

F_DTMFOFF: Clear DTMF output OFF request flag

F_DTMFEND: Clear DTMF output complete flag

FLAG

F_ONTIMACT: Clear timer count request flag for the DTMF output ON period

F_OFTIMACT: Clear timer count request flag for the DTMF output OFF period

7 6 5 4 3 2 1 0Area to store a code indicating the DTMF output stateInitial value = 00H: The "DTMF output available" code

DTMF _CODE

7 6 5 4 3 2 1 0Save area for the dial key code corresponding to the pressed keyInitial value = FFH: Key off code

KEY_ DATA

3.3 Sample Program

3-9

(8) Setting for the count area for the DTMF output ON period

(9) Setting for the count area for the DTMF output OFF period

7 6 5 4 3 2 1 0Count area for the DTMF output ON periodCount update resolution: 9.15 msON_TIME

Initial value = 00H

7 6 5 4 3 2 1 0Count area for the DTMF output OFF period

Initial value = 00HOFF_TIME Count update resolution: 9.15 ms

3.3 Sample Program



Fig. 3-4 Flowchart

RESET

TMR_CTLDTMF output timer

monitoring

Set system control register

KEYIN_PRCDial key input

processing

DTMF_CTLDTMF output control

processing

Set stack pointer

Set I/O ports

Initialize RAM area

Set timebase timer control register

Set DTMF control register

MAIN

3.3 Sample Program

3-11

Fig. 3-5 Flowchart

DTMF_CTL

DTMF output request?

Clear DTMF output request flag

Set status code to "DTMF ON output"

Clear DTMF output OFF request flag

Set status code to "DTMF OFF output"

Clear DTMF output complete flag

DTMF output OFF request?

DTMF output complete?

RET

No

No

NoYes

Yes

Yes

DTMF output control processing

Fetch DTMF output data from table based

on the dial data

Set fetched data in DTMF data register

Start DTMF signal output

Start DTMF output ON timer

Halt DTMF output

Start DTMF output OFF timer

Set status code to "DTMF

output available"

3.3 Sample Program


Fig. 3-5a Flowchart

TMR_CTL

Interval timer overflow?(9.15 ms)

Clear interval timer overflow flag

Is there a request for the timer count

for the DTMF output ON period?

Time up?

RET

No

No

No

Yes

Yes

Yes


Timer count for the DTMF output

ON period

Set DTMF output OFF request flag

Timer count for the DTMF output

OFF period

Time up?

Set DTMF output complete flag

Is there a request for the timer count for the DTMF output OFF

period?

No

Yes

Yes

No

3.3 Sample Program

3-13

NAME DTMF;*******************************************************;* *;* Sample DTMF control program *;* *;*******************************************************;;*************************************;* MB89170 Resource Definition *;*************************************RES170 DIRSEG ABS

ORG 0000HPDR0 RB 1 ; Port 0 data registerDDR0 RB 1 ; Port 0 direction register;

ORG 0004HPDR2 RB 1 ; Port 2 data register;

ORG 0007HSYCC RB 1 ; System clock control register;

ORG 000AHTBTC RB 0 ; Timebase timer control registerTBR RBIT 1 ; Timebase timer clear bitTBC0 RBIT 1 ; Interval time specification bitTBC1 RBIT 1 ; Interval time specification bit


TBIE RBIT 1 ; Interval interrupt enable bitTBOF RBIT 1 ; Interval timer overflow bit;

ORG 0020HDTMC RB 0 ; DTMF control registerOUTE RBIT 1 ; DTMF output control bitRDIS RBIT 1 ; Low tone generation control bitCDIS RBIT 1 ; High tone generation control bitCSEL RBIT 1 ; Source oscillation frequency selection bit

RBIT 1 ; Dummy bitRBIT 1 ; Dummy bitRBIT 1 ; Dummy bitRBIT 1 ; Dummy bit

;DTMD RB 1 ; DTMF data register;RES170 ENDS;;*******************************;* RAM Definition *;*******************************RAM DIRSEG ABS

3.3 Sample Program


ORG 0080HFLAG RB 0 ; Flag areaF_DTMFOUT RBIT 1 ; DTMF output request flagF_DTMFOFF RBIT 1 ; DTMF output OFF request flagF_DTMFEND RBIT 1 ; DTMF output complete flagF_ONTIMACT RBIT 1 ; Timer count request flag for DTMF output

ON periodF_OFTIMACT RBIT 1 ; Timer count request flag for DTMF output

OFF periodRBIT 1 ; Dummy bitRBIT 1 ; Dummy bitRBIT 1 ; Dummy bit

;DTMF_CODE RB 1 ; DTMF control code areaKEY_DATA RB 1 ; Dial key code save areaON_TIME RB 1 ; DTMF output ON period count areaOFF_TIME RB 1 ; DTMF output OFF period count area;RAM ENDS;DTMF_READY EQU 00H ; "DTMF output available" status codeDTMF_ON EQU 01H ; "DTMF ON output" status codeDTMF_OFF EQU 02H ; "DTMF OFF output" status code;DTMF CSEG PUBLIC

EXTRN KEYIN_PRC ; Dial key input processing;*******************************;* Initial Settings *;*******************************RESET:

MOV SYCC,#00000111B ; Set system clock (4/Fc)MOVW A,#280H ; Set stack pointerMOVW SP,A

;MOVW A,#0030H ; Set PS (interrupt level "11")MOVW PS,A

;MOV DDR0,#00000000B ; Set ports P00 - P07 as input portsMOV PDR2,#11111111B ; Output initial data to ports P20 - P27

;MOV FLAG,#00H ; Flag areaMOV DTMF_CODE,#DTMF_READY ; "DTMF output available" status codeMOV KEY_DATA,#0FFH ; Initialize dial key code save areaMOV ON_TIME,#00H ; Initialize count area for DTMF output ON

periodMOV OFF_TIME,#00H ; Initialize count area for DTMF output OFF

period;

MOV TBTC,#00000010B ; Set timebase timer control register (9.15 ms);

MOV DTMC,#00000000B ; Set DTMF control register

3.3 Sample Program

3-15

;*******************************;* Main Routine *;*******************************MAIN:

CALL TMR_CTL ; Monitor DTMF output timer;

CALL KEYIN_PRC ; Dial key input processing;

CALL DTMF_CTL ; DTMF output control processing;

JMP MAIN;***************************************;* DTMF Output Control Processing *;***************************************DTMF_CTL:

BBC F_DTMFOUT,DTMFCTL_020 ; DTMF output request present? No;

CLRB F_DTMFOUT ; Clear DTMF output request flagMOV DTMF_CODE,#DTMF_ON ; Set "DTMF ON output" status code

;MOVW A,#0000HMOV A,KEY_DATA ; Fetch DTMF output data based on dial key

codeCLRCMOVW A,#DTMF_TBL ; Top address of the DTMF output data tableADDCW AMOV A,@A ; Fetch DTMF output data

;MOV DTMD,A ; Set DTMF output dataMOV DTMC,#00000001B ; Start DTMF signal output

;MOV ON_TIME,#0BH ; Start timer for the DTMF output ON period

(100 ms)SETB F_ONTIMACT ; Set timer count request flag for the DTMF

output ON period;DTMFCTL_EXT:

RET;DTMFCTL_020:

BBC F_DTMFOFF,DTMFCTL_040 ; DTMF output OFF request present? No;

CLRB F_DTMFOFF ; Clear DTMF output OFF request flag

MOV DTMF_CODE,#DTMF_OFF ; Set "DTMF OFF output" status code;

MOV DTMC,#00000000B ; Halt DTMF signal output

;MOV OFF_TIME.#0BH ; Start timer for the DTMF output OFF period

(100 ms)

3.3 Sample Program


SETB F_OFTIMACT ; Set timer count request flag for the DTMFoutput OFF period

JMP DTMFCTL_EXT;DTMFCTL_040:

BBC F_DTMFEND,DTMFCTL_EXT ; DTMF output complete? No;

CLRB F_DTMFEND ; Clear DTMF output complete flag;

MOV DTMF_CODE,#DTMF_READY ; Set "DTMF output available" status codeJMP DTMFCTL_EXT

;;///// DTMF Output Data Table;DTMF_TBL: ;Register value ;Dial number:DATA CODE

DB 0AH ;(0) :00DB 01H ;(1) :01DB 02H ;(2) :02DB 03H ;(3) :03DB 04H ;(4) :04DB 05H ;(5) :05DB 06H ;(6) :06DB 07H ;(7) :07DB 08H ;(8) :08DB 09H ;(9) :09DB 0BH ;(*) :0ADB 0CH ;(#) :0BDB 0DH ;(A) :0CDB 0EH ;(B) :0DDB 0FH ;(C) :0EDB 00H ;(D) :0F

;;***************************************;* DTMF Output Timer Monitoring *;***************************************TMR_CTL:

BBC TBOF,TMRCTL_EXT ; Is the interval time (9.15 ms) up? No;

CLRB TBOF ; Clear interval time overflow bitBBC F_ONTIMACT,TMRCTL_020 ; Is there a timer count request for the DTMF

output ON period? No;

MOV A,ON_TIME ; Timer count for the DTMF output ON periodCLRCSUBC A,#01HMOV ON_TIME,ABNZ TMRCTL_020 ; Time up? No

;CLRB F_ONTIMACT ; Clear timer count request flag for the DTMF

output ON period

3.3 Sample Program

3-17

SETB F_DTMFOFF ; Set the DTMF output OFF request flag;TMRCTL_020:

BBC F_OFTIMACT,TMRCTL_EXT ; Is there a timer count request for the DTMFoutput OFF period? No

;MOV A,OFF_TIME ; Timer count for the DTMF output OFF

periodCLRCSUBC A,#01HMOV OFF_TIME,ABNZ TMRCTL_EXT ; Time up? No

;CLRB F_OFTIMACT ; Clear timer count request flag for the DTMF

output OFF periodSETB F_DTMFEND ; Set the DTMF output complete flag

;TMRCTL_EXT:

RET;DTMF ENDS;*******************************;* Vector Addresses *;*******************************VECTOR CSEG ABS

ORG 0FFFDHDB 00H ; Reset modeDW RESET ; Reset vector

VECTOR ENDSEND

4.1 Overview

4-3

Chapter 4:Software Modem

4.1 Overview

The MB89890 Family has an internal modem signal output circuit and modem timer (pulse width counttimer).

These resources, together with a simple external circuit, enable digital signals to be converted andtransmitted as analog signals. Similarly, a received analog signal can be converted back to the originaldigital signal.



MB89890 FamilyMain clock = 8.000 MHz

(2) Software modem

Data transfer is performed using the modem signal output and modem timer (pulse width count timer)resources.

• Transmitting data

Outputs data at 2400 bps baud rate using the modem signal output resource.Modulation is performed using frequency modulation.

• Receiving data

Data is received by using the modem timer (pulse width count timer) resource to resolve differentcarrier frequencies into "1"s and "0"s.

Whether a signal is a "1" or a "0" is determined from the time between input pulse edges. An internaldigital low pass filter is used to eliminate noise on the input pulses (the noise canceller clock provides a1 µs sample pitch).

(3) Used ports (see circuit block diagram)

Input: P32/MSKI (Modem signal input port)Output: P63/MSKO (Modem signal output port)


4-4 Chapter 4: Software Modem



4.2.3 Data Format

Fig. 4-2 Data Format of Modem Signals

MB89890

VCC

VSS

RST

P32/MSKI

P31/MSKO

X0 X1

8.000MHz

VCC Modem transmission data Demodulation

filter

Modulation filter

Modem transmission data

“1” “0”“1’’“0’’“1’’“0’’

[2400 bps transmission]

Whether the received data is a "1" or a "0" is determined fromthe time between input pulse edges.

Data

208µsec 416µsec 2400Hz 1200Hz

MSKO pin (output)

MSKI pin (input)

Range for a "0": 188 µs - 228 µs Range for a "1": 396 µs - 436 µs


4-5



Main routine

Initial settings

Modem monitor processing


End

Modem transmit interrupt

Modem receive interrupt

Determine if input data is a "1" or a "0"

Modem data input processing

Modem data output processing

End

End

Post-processing after modem

transmit/receive

Modem transmit monitor processing

Modem receive monitor processing




• Modem timer (pulse width counter): For modem reception

• Modem signal output: For modem transmission





0CH PDR3 Port 3 data register

0DH DDR3 Port 3 I/O direction register



2AH MODC Modem output control register

2BH MODA Modem output data register

34H MDC1 Modem timer control 1 register

35H MDC2 Modem timer control 2 register

36H MLDH "H" level data register

37H MLDL "L" level data register

7CH ILR1 Interrupt level setting register #1


4-7

(3) RAM allocation

(4) Flag contents



80H FLAG Flag area

81H 82H 83H

MDSNDBUF +1 +2

Modem output buffer

84H 85H 86H

MDSNDDAT +1 +2

Modem output request data storage area

87H 88H

SNDBUFPT +1

Output buffer pointer storage area

89H SND8SHT 8-bit shift counter (for transmission)

8AH MDRCVCOD Receive data area

8BH 8CH 8DH

MDRCVBUF +1 +2

Modem receive data save buffer

8EH 8FH 90H

MDRCVDAT +1 +2

Modem receive data save area

91H 92H

RCVBUFPT +1

Receive buffer pointer save area

93H RCV8SHT 8-bit shift counter (for reception)

Table 4-2 Address 80H Contents

Bit Symbol Function

0 F_MRCVEND Sets modem receive complete flag when 1: Receive complete

1 F_MRCVIN Sets modem input data present flag when 1: Input data present

2 F_MSNDBSY Sets modem output in progress flag when 1: Output in progress

3 F_MSNDEND Sets modem transmit complete flag when 1: Transmit complete

4 F_MSNDREQ Sets modem transmit request flag when 1: Transmit request present

5 F_HARFPL Sets half period flag when 1: Half period pulse width received

4.3 Sample Program


4.3 Sample Program

4.3.1 Settings of Initial Register and RAM (1) Settings of system clock control register

(2) Settings of I/O port


0 0 0 0 0 1 1 1

7 6 5 4 3 2 1 0

* **CS1, CS0: System operating clock 4/fch = 0.5 µs

SCS: Set the system clock as the main clock (8 MHz).

WT1, WT0: Oscillation stabilization time 23/fch = 0 ms

SYCC

0 0 0 0 0 0 0 0

7 6 5 4 3 2 1 0

P32/MSKI: Set as input port

1 1 1 1 1 1 1 1

7 6 5 4 3 2 1 0

* * * * **

Output "H" to P63/MSKO


DDR3

PDR6

*

0 0 0 0 1 0 0 0

7 6 5 4 3 2 1 0

P63/MSKO: Set as output port* * * * **

DDR6

*

0 0 1 0 1 1 1 1

7 6 5 4 3 2 1 0

* * **

L20, L21: Set modem output interrupt level to 2

L30, L31: Set modem timer interrupt level to 1


ILR1

4.3 Sample Program

4-9

(4) Settings of modem timer control 1 register

(5) Settings of modem timer control 2 register

(6) Settings of modem output control register

0 0 0 0 0 1 1 0

7 6 5 4 3 2 1 0

**MDIF: Clear edge detect flag

ESL1, ESL0: Enable both edge detect interrupts

LOF: Clear "L" level measurement overflow flag

MDC1

HOF: Clear "H" level measurement overflow flag

MOIE: Disable overflow interrupt


0 0 0 0 0 1 0 1

7 6 5 4 3 2 1 0

* * **NCS1, NCS0: Set count clock to 2 µs

MCS1, MCS0: Set noise canceller clock to 1 µs


MDC2

0 0 0 1 0 1 1 0

7 6 5 4 3 2 1 0

*STAT: Halt modem output

CSL1, CSL0: Set 2400 bps output for an 8 MHz source oscillation

MOEN: Set P63/MSKO as the modem output port

MODC

SIOE: Disable use as a serial I/O output

DEIE: Disable empty interrupt


HIZE: Enable MSKO pin Hi-z

4.3 Sample Program


(7) Settings of modem output control register

(8) Settings of flag area

(9) Settings of modem output buffer

(10) Settings of modem output request data storage area

0 0 0 0 0 0 0 0

7 6 5 4 3 2 1 0

MDA0: Clear modem output data bit to 0


MODA

0 0 1 0 0 0 0 0

7 6 5 4 3 2 1 0

**F_MRCVEND: Clear modem receive complete flag

F_MRCVIN: Clear modem input data present flag

F_MSNDBSY: Clear modem output in progress flag

FLAG

F_MSNDEND: Clear modem transmit complete flag

F_MSNDREQ: Clear modem transmit request flag


F_HARFPL: Set half period flag

7 6 5 4 3 2 1 0Initialize modem output bufferInitial value = 000000HMDSND

BUF+1

+2

7 6 5 4 3 2 1 0Initialize modem output request data storage areaInitial value = 000000HMDSND

DAT+1

+2

4.3 Sample Program

4-11

(11) Settings of 8-bit shift counter (transmit)

(12) Settings of receive data area

(13) Settings of modem receive data storage buffer

(14) Settings of modem receive data storage area

(15) Settings of 8-bit shift counter (receive)

(16) Settings of output buffer pointer storage area

7 6 5 4 3 2 1 0Initialize 8-bit shift counter (for modem transmission)Initial value = 08H

SND8SHT

7 6 5 4 3 2 1 0Initialize modem receive data areaInitial value = 00H

MDRCV COD

7 6 5 4 3 2 1 0Initialize modem receive data storage bufferInitial value = 000000HMDRCV

BUF+1

+2

7 6 5 4 3 2 1 0Initialize modem receive data storage areaInitial value = 000000HMDRCV

DAT+1

+2

7 6 5 4 3 2 1 0Initialize 8-bit shift counter (for modem reception)Initial value = 08H

RCV8SHT

7 6 5 4 3 2 1 0Initialize output buffer pointer storage areaSet top address of modem output bufferInitial value = #MDSNDBUF

SNDBUF PT

+1

Upper

Lower

4.3 Sample Program


(17) Settings of receive buffer pointer storage area

7 6 5 4 3 2 1 0Initialize receive buffer pointer storage areaSet top address of modem receive data storage bufferInitial value = #MDRCVBUF

RCVBUF PT

+1

Upper

Lower

4.3 Sample Program

4-13


Fig. 4-4 Flowchart

RESET

MODM_CTLModem monitor

processing

Set system clock control register

MODM_PRCPost-processing after

modem transmit/receive

Set stack pointer

Set I/O ports

Initialize RAM area

Set interrupt levels

Set modem timer control register

MAIN

Set modem output control register

Enable interrupts

A

A

4.3 Sample Program


Fig. 4-5 Flowchart

MODM_CTL

Yes

Clear modem receive complete flag

MDSND_CTLModem output

monitor processing

No

MDRCV_CTLModem input monitor

processing

Modem output in progress?

Modem output monitor processing

RET

MDSND_CTL

Set modem input data present flag

Modem transmit request present?Modem transmit

complete?

Clear modem transmit request flag

Clear modem transmit complete flag

Clear modem output in progress flag

Set modem output in progress flag

Set output request data in modem

output buffer

Set output buffer pointer

Enable modem output interrupt

Modem receive complete?

MDRCV_CTL

RET


Modem input monitor processing

RET

No

NoNo

Yes

YesYes

4.3 Sample Program

4-15

Fig. 4-6 Flowchart

INT_MDRCV

"H" pulse width over?

Save "L" pulse width count

Clear "H", "L" pulse width overflow

interrupt source flag

Restore A, T, and IX registers

Save "H" pulse width count

Clear edge detect interrupt source flag

Enable pulse width overflow interrupt

Store modem data

Modem timer interrupt(receive)

RET I

No

No

No

Yes

Yes

Yes

Save A, T, and IX registers

"L" pulse width over?

Falling edge?

Set error code in the receive data area

Set modem receive complete flag

Initialize receive buffer pointer

Initialize 8-bit shift counter

Set half period flag

4.3 Sample Program


Fig. 4-7 Flowchart

Half period?

Clear half period flag

Modem data store processing

No

No

No

Yes

Yes

Yes

DF ← 0

Is pulse width count within "1"

range?

8-bit shift complete?

Is pulse width count within "0" range?

CF ← 1


Set error code in the receive data area



Set data at receive buffer specified by

receive buffer pointer

Update 8-bit shift counter


Update receive buffer pointer

Have 3 bytes been received?

Set modem receive complete flag

Set receive data inthe receive data

storage area

Initialize receive buffer pointer

Set normal code in the receive data area

A

A

Yes

No

Yes

No

4.3 Sample Program

4-17

Fig. 4-8 Flowchart

Output data = "1"?

Modem output interrupt (transmit)

No

No

No

Yes

Yes


3 bytes output completed?

INT_MDSND

Get data from location specified by output buffer pointer

Update 8-bit shift counter

Set "1" in modem output register

8-bit shift complete?


Update output buffer pointer


Set "0" in modem output register

Disable modem output interrupt

Set modem transmit complete flag

RET I

Yes

4.3 Sample Program


NAME MODEM;*******************************************************;* *;* Sample Modem Transmit/Receive Program *;* *;*******************************************************;;*************************************;* MB89890 Resource Definition *;*************************************RES890 DIRSEG ABS

ORG 0007HSYCC RB 1 ; System clock control register;

ORG 000CHPDR3 RB 1 ; Port 3 data registerDDR3 RB 1 ; Port 3 I/O direction register;

ORG 0012HPDR6 RB 1 ; Port 6 data registerDDR6 RB 1 ; Port 6 I/O direction register;

ORG 002AHMODC RB 0 ; Modem output control registerSTAT RBIT 1 ; Modem output enable/disable bitCSL0 RBIT 1 ; Source oscillation frequency baud rate setting

bitCSL1 RBIT 1 ; Source oscillation frequency baud rate settingTEST RBIT 1 ; Test bitMOEN RBIT 1 ; External pin control bit for modem outputSIOE RBIT 1 ; Enable/disable use as a serial I/O outputDEIE RBIT 1 ; Empty interrupt enable/disable bitHIZE RBIT 1 ; Hi-Z output enable/disable bit;MODA RB 0 ; Modem output data registerMDA0 RBIT 1 ; Modem output data bit 0MDA1 RBIT 1 ; Modem output data bit 1

RBIT 1 ; Dummy bitRBIT 1 ; Dummy bitRBIT 1 ; Dummy bitRBIT 1 ; Dummy bitRBIT 1 ; Dummy bit

DEMP RBIT 1 ; Flag to indicate whether data is present in bufferregister

;;

ORG 0034HMDC1 RB 0 ; Modem timer control 1 registerMDIF RBIT 1 ; Edge detect flag bitESL0 RBIT 1 ; Edge select/interrupt enable bitESL1 RBIT 1 ; Edge select/interrupt enable bit

4.3 Sample Program

4-19

LOF RBIT 1 ; Overflow flag bit for "L" level measurementHOF RBIT 1 ; Overflow flag bit for "H" level measurementMOIE RBIT 1 ; Overflow interrupt enable bitMSIG RBIT 1 ; Input pulse level sense bit

RBIT 1 ; Dummy bit;MDC2 RB 1 ; Modem timer control 2 registerMLDH RB 1 ; "H" level data registerMLDL RB 1 ; "L" level data register;

ORG 007CHILR1 RB 1 ; Interrupt level setting register #1;RES890 ENDS;;*******************************;* RAM Definition *;*******************************RAM DIRSEG ABS

ORG 0080HFLAG RB 0 ; Flag areaF_MRCVEND RBIT 1 ; Modem receive complete flagF_MRCVIN RBIT 1 ; Modem input data present flagF_MSNDBSY RBIT 1 ; Modem output in progress flagF_MSNDEND RBIT 1 ; Modem transmit complete flagF_MSNDREQ RBIT 1 ; Modem transmit request flagF_HARFPL RBIT 1 ; Half period flag


;MDSNDBUF RB 3 ; Modem output bufferMDSNDDAT RB 3 ; Modem output request data storage areaSNDBUFPT RB 2 ; Output buffer pointer storage areaSND8SHT RB 1 ; 8-bit shift counter (for transmit);MDRCVCOD RB 1 ; Receive data areaMDRCVBUF RB 3 ; Modem receive data storage bufferMDRCVDAT RB 3 ; Modem receive data storage areaRCVBUFPT RB 2 ; Storage area for receive buffer pointerRCV8SHT RB 1 ; 8-bit shift counter (for receive);RAM ENDS;MDRCV_OK EQU 01H ; Modem receive OK codeMDRCV_NG EQU 02H ; Modem receive error codeMDMIN0 EQU 94 ; Lower limit for "0" (188 µs count value)MDMAX0 EQU 115 ; Upper limit for "0" (229 µs count value)MDMIN1 EQU 198 ; Lower limit for "1" (396 µs count value)MDMAX1 EQU 219 ; Upper limit for "1" (438 µs count value);MODEM CSEG PUBLIC

4.3 Sample Program


EXTRN MODM_PRC ; Modem transmit/receive post-processing

;***************************;* Initial Settings‘ *;***************************RESET:

MOV SYCC,#00000111B ; Set system clock (4/Fc)MOVW A,#880H ; Set stack pointerMOVW SP,A

;MOVW A,#0030H ; Set PS (interrupt level "11")MOVW PS,A

;MOV DDR3,#00000000B ; Set port P32/MSKI as an input portMOV DDR6,#00001000B ; Set port P63/MSKO as an output portMOV PDR6,#11111111B ; Output initial data to port P63/MSKO

;MOVW A,#0000HMOVW MDSNDBUF,A ; Initialize modem output bufferMOV MDSNDBUF+2,AMOVW MDSNDDAT,A ; Initialize modem output request data storage areaMOV MDSNDDAT+2,AMOV SND8SHT,#08H ; Initialize 8-bit shift counter (for transmit)

;MOV MDRCVCOD,A ; Initialize receive data areaMOVW MDRCVBUF,A ; Initialize modem receive data storage bufferMOV MDRCVBUF+2,AMOVW MDRCVDAT,A ; Initialize modem receive data storage areaMOV MDRCVDAT+2,AMOV RCV8SHT,#08H ; Initialize 8-bit shift counter (for receive)

;MOVW A,#MDSNDBUF ; Top address of modem output bufferMOVW SNDBUFPT,A ; Initialize output buffer pointer storage areaMOVW A,#MDRCVBUF ; Top address of modem receive data storage bufferMOVW RCVBUFPT,A ; Initialize receive buffer pointer storage area

;MOV FLAG,#00H ; Flag areaSETB F_HARFPL ; Set half period flag

;MOV ILR1,#00101111B ; Modem receive: level 1, Modem transmit: level 2

;MOV MDC1,#00000110B ; Enable both edge detect interruptsMOV MDC2,#00000101B ; Set timer count clockMOV MODC,#00010110B ; Set 2400 bpsMOV MODA,#00000000B ; Initialize modem output data register

;SETI ; Enable interrupts

;;*******************************;* Main Routine *;*******************************

4.3 Sample Program

4-21

MAIN:CALL MODM_CTL ; Modem monitor processing

;CALL MODM_PRC ; Modem transmit/receive post-processing

;JMP MAIN

;;*******************************;* Modem Monitor Processing *;*******************************MODM_CTL:;

CALL MDSND_CTL ; Modem output monitor processing;

CALL MDRCV_CTL ; Modem input monitor processing;

RET;;**************************************;* Modem Input Monitor Processing *;**************************************MDRCV_CTL:

BBC F_MRCVEND,MDRCV_EXT ; Modem receive complete? No;

CLRB F_MRCVEND ; Clear modem receive complete flagSETB F_MRCVIN ; Set modem input data present flag

;MDRCV_EXT:

RET;;***************************************;* Modem Output Monitor Processing *;***************************************MDSND_CTL:

BBC F_MSNDBSY,MDSND_020 ; Modem output in progress? No;

BBC F_MSNDEND,MDSND_EXT ; Modem transmit complete? No;

CLRB F_MSNDEND ; Clear modem transmit complete flagCLRB F_MSNDBSY ; Clear modem output in progress flag

;MDSND_EXT:

RET;MDSND_020:

BBC F_MSNDREQ,MDSND_EXT ; Modem transmit request present? No;

CLRB F_MSNDREQ ; Clear modem transmit request present flag

SETB F_MSNDBSY ; Set modem output in progress flag;

4.3 Sample Program


MOVW A,MDSNDDAT ; Set output request data in modem output buffer

MOVW MDSNDBUF,AMOV A,MDSNDDAT+2MOV MDSNDBUF+2,AMOVW A,#MDSNDBUF ; Top address of modem output bufferMOVW SNDBUFPT,A ; Set output buffer pointer

;MOV MODC,#01010111B ; Enable modem transmit interrupt. Enable

modem outputJMP MDSND_EXT

;;*******************************;* Modem Timer Interrupt *;*******************************INT_MDRCV:

PUSHW A ; Save A, T, and IX registersXCHW A,TPUSHW APUSHW IX

;BBS HOF,INTRCV_020 ; "H" pulse width over? Yes

;BBC LOF,INTRCV_040 ; "L" pulse width over? No

;INTRCV_020:

CLRB HOF ; Clear "H" pulse width overflow interrupt flag

CLRB LOF ; Clear "L" pulse width overflow interrupt flag

;MOV MDRCVCOD,#MDRCV_NG ; Set error code in receive data areaSETB F_MRCVEND ; Set modem receive complete flagMOVW A,#MDRCVBUF ; Top address of modem receive data

storage bufferMOVW RCVBUFPT,A ; Initialize receive buffer pointer storage

areaMOV RCV8SHT,#08H ; Initialize 8-bit shift counter (for receive)SETB F_HARFPL ; Set half period flag

;INTRCV_EXT:

POPW IX ; Restore A, T, and IX registersPOPW AXCHW A,TPOPW ARETI

;INTRCV_040:

BBS MSIG,INTRCV_060 ; Falling edge? No;

MOV A,MLDH ; "H" pulse width count

4.3 Sample Program

4-23

JMP INTRCV_080;INTRCV_060:

MOV A,MLDL ; "L" pulse width count;INTRCV_080:

CLRB MDIF ; Clear edge detect interrupt source flag;

SETB MOIE ; Enable pulse width overflow interrupt;

CMP A,#MDMIN0 ; Within "0" range?BC INTRCV_100 ; No

;CMP A,#MDMAX0 ; Within "0" range?BNC INTRCV_100 ; No

;CLRC ; Set receive data to "0"BBC F_HARFPL,INTRCV_120 ; Half period? No

;CLRB F_HARFPL ; Clear half period flagJMP INTRCV_EXT

;INTRCV_100:

CMP A,#MDMIN1 ; Within "1" range?BC INTRCV_160 ; No

;CMP A,#MDMAX1 ; Within "1" range?BNC INTRCV_160 ; No

;SETC ; Set receive data to "1"

;INTRCV_120:

SETB F_HARFPL ; Set half period flagMOVW A,RCVBUFPT ; Fetch receive buffer pointerMOVW IX,AMOV A,@IXROLC A ; Set receive dataMOV @IX,A

;MOV A,RCV8SHT ; Update 8-bit shift counterCLRCSUBC A,#01HMOV RCV8SHT,ABNZ INTRCV_EXT ; 8-bit shift complete? No

;MOV RCV8SHT,#08H ; Initialize 8-bit shift counterINCW IX ; Update receive buffer pointerMOVW A,IXMOVW RCVBUFPT,AMOVW A,#MDRCVBUF+3CMPW A ; 3 bytes received?

4.3 Sample Program


BNZ INTRCV_EXT ; No;

MOV MDRCVCOD,#MDRCV_OK ; Set receive OK code in receive data area;INTRCV_140:

MOVW A,#MDRCVBUF ; Initialize receive buffer pointerMOVW RCVBUFPT,AMOVW A,MDRCVBUF ; Set receive data in receive data save areaMOVW MDRCVDAT,AMOV A,MDRCVBUF+2MOV MDRCVDAT+2,ASETB F_MRCVEND ; Set modem receive complete flagJMP INTRCV_EXT

;INTRCV_160:

MOV MDRCVCOD,#MDRCV_NG ; Set error code in receive data areaSETB F_HARFPL ; Set half period flagMOV RCV8SHT,#08H ; Initialize 8-bit shift counterJMP INTRCV_140

;;*******************************;* Modem Output Interrupt *;*******************************INT_MDSND:

PUSHW A ; Save A, T, and IX registersXCHW A,TPUSHW APUSHW IX

;MOVW A,#MDSNDBUF+3MOVW A,SNDBUFPTCMPW A ; Output of 3 bytes completed?BZ INTSND_060 ; Yes

;MOVW IX,AMOV A,@IXROLC A ; Fetch output dataMOV @IX,ABNC INTSND_040 ; Output data = "1"? No

;SETB MDA0 ; Set "1" in modem output register

;INTSND_020:;

MOV A,SND8SHT ; Update 8-bit shift counterCLRCSUBC A,#01HMOV SND8SHT,ABNZ INTSND_EXT ; 8-bit shift complete? No

;MOV SND8SHT,#08H ; Initialize 8-bit shift counter

4.3 Sample Program

4-25

INCW IX ; Update receive buffer pointerMOVW A,IXMOVW SNDBUFPT,A

;INTSND_EXT:

POPW IX ; Restore A, T, and IX registersPOPW AXCHW A,TPOPW ARETI

;INTSND_040:

CLRB MDA0 ; Set "0" in modem output registerJMP INTSND_020

;INTSND_060:

SETB F_MSNDEND ; Set modem transmit complete flagCLRB DEIE ; Disable modem output interruptJMP INTSND_EXT

;MODEM ENDS;*******************************;* Vector Addresses *;*******************************VECTOR CSEG ABS

ORG 0FFF4HDW INT_MDRCV ; Modem timer interrupt (receive)DW INT_MDSND ; Modem output interrupt (transmit)ORG 0FFFDHDB 00H ; Reset modeDW RESET ; Reset vector

VECTOR ENDSEND

5.1 Overview

5-3

Chapter 5:Fuzzy Logic

5.1 Overview

The MB94140 is a fuzzy controller that uses the same core as the F2MC-8L Family.

The fuzzy controller uses the F2RU-6 fuzzy logic engine. This engine consists of a grade operation unit,membership function memory, min-MAX operation unit, de-fuzzify unit, CPU-I/O unit, and control unit.The engine can perform fuzzy logic operations for various numbers of I/O and fuzzy rules.

Also, table-lookup type fuzzy logic processing can be implemented on the F2MC-8L Family (which do nothave a fuzzy logic engine). Although adjustment of rules and membership functions is more difficult forthis type of fuzzy logic processing, it is a practical option when adjustment is not required.


5.2.1 Summary SpecificationsThe sample program performs rotational control using two-input/one-output fuzzy logic. The number ofrules can be set between 1 and 255. This example has four rules.

An example table-lookup program is also given.

(1) Target microcontroller (fuzzy controller)

MB94146Main clock = 10.00 MHz

(2) Target fuzzy logic engine

F2RU-6Input = 6-bit (64 elements)Output = 6-bit (64 elements)Logic = min-MAX centroid method

(3) Fuzzy logic specificationsInputs

1: Rotational deviation (Target - Actual value)2: Cumulative rotational deviations (Previous cumulative deviations + Current deviation)

Output1: Control quantity (Output value)


5-4 Chapter 5: Fuzzy Logic

Rules1. If the rotational deviation is "plus 1" and the cumulative rotational deviation is "plus 2", the control

quantity is "large 1".

2. If the rotational deviation is "minus 1" and the cumulative rotational deviation is "minus 2", the control quantity is "small 1".

3. If the rotational deviation is "plus 1" and the cumulative rotational deviation is "minus 2", the control quantity is "large 2".

4. If the rotational deviation is "minus 1" and the cumulative rotational deviation is "plus 2", the control quantity is "small 2".

Membership functions

Fig. 5-1

Fig. 5-2

Plus

Rotational deviation

00h 0Eh 14h 2Ah 32h 3Fh

Cumulative rotational deviation

Plus

00h 10h 18h 28h 30h 3Fh


5-5

Fig. 5-3

(4) Summary of fuzzy logic using the min-MAX centroid method

Figure 5-4 shows the fuzzy logic technique called the min-MAX centroid method which is used in theF2RU-6. For rule 1, the rotational deviation grade for the membership function for input 1 ("plus 1") andthe cumulative rotational deviation grade for the membership function for input 2 ("plus 2") are obtainedand a min operation (select the lowest value) performed. The operation result and the output membershipfunction "large 2" are then used as inputs to another min operation. Similar processing is performed forrules 2, 3, and 4 and a min operation performed on the output membership function. These are thencombined by performing a MAX operation (select the largest value) on the output membership functionsafter the min operations. Finally, the centroid of the combined results is obtained by equation 5-1 and usedas the output value (control quantity).

That is, the condition section (IF section) processing uses the min operation, the consequence section(THEN section) processing uses the MAX operation, and the de-fuzzify processing uses the gravitymethod.

Equation 5-1

Sm

all

Sm

all

Control quantity

00h

06h

0Eh

12h 1Ah

26h 2Eh

32h

3Ah

3Fh

gravity

n: Position on horizontal axis Gn: Grade at position n

=

Σ (n·Gn)

Gn(n=0, 1, 2, 63)

Σ



Fig. 5-4 Summary of Fuzzy Logic Processing (min-MAX Centroid method)

Rule 4: If the rotational deviation is "minus 1" and the cumulative rotational deviation is "plus 2", the control quantity is "small 2".

Rule 1: If the rotational deviation is "plus 1" and the cumulative rotational deviation is "plus 2", the control quantity is "large 1".

Cumulative rotational deviation

Plus 1

Rotational deviation

Plus 2

Larg

e 1

+ (MAX operation)

min operation

Rotational deviation Cumulative rotational deviation + (MAX operation)

Rule 2: If the rotational deviation is "minus 1" and the cumulative rotational deviation is "minus 2", the control quantity is "small 1".

Rule 3: If the rotational deviation is "plus 1" and the cumulative rotational deviation is "minus 2", the control quantity is "large 2".

Sm

all 1

Minus 1 Minus 2

min operation

Rotational deviation Cumulative rotational deviation + (MAX operation)

min operation

Plus 1 Minus 2

Larg

e 2

Rotational deviation Cumulative rotational deviation

Centroid (De-fuzzify)

Larg

e 2

Larg

e 1

Sm

all 1

Sm

all 2

Minus 1 Plus 2

Sm

all 2

min operation

min operationÚ

↓

minoperation

Ú↓

min operation

↑

min operation

Ú

↑


5-7



Main routine

Yes

Initial settings

Control input processing

NoLogic rules/lookup table selection

Fuzzy logic processing

(fuzzy logic engine/table-lookup method)


Initialize engine

Initialize rule numbers

Condition processing 1

(calculate input 1 grade)

Control output processing

Is there an unprocessed rule?


(calculate input 2 grade and perform

min operation)

Consequence processing

(expand outputmembership

function)

Update rule number

De-fuzzifyprocessing

END


Calculate table data address

Fetch table data

END

(Fuzzy logic engine)

(Table-lookup method)




• F2RU-6 (Fuzzy logic engine)


(3) RAM allocation



31H FLRA F2RU-6 label register A

32H FLRB F2RU-6 label register B

33H FLRC F2RU-6 label register C

34H FLRD F2RU-6 label register D

35H FLRX F2RU-6 data register X

36H FGRY F2RU-6 grade register Y

37H FCOMR F2RU-6 command register

38H FCSR F2RU-6 control/status register



80H _FUZIN1 Input 1 (rotational deviation) data storage area

81H_FUZIN2 Input 2 (cumulative rotational deviation) data

storage area

82H _FUZOUT Output (control quantity) data storage area

83H 84H

_RULEPNT Storage area for top address of rules (H)(When using fuzzy logic engine) (L)

85HRULENO Rule number storage area

(When using fuzzy logic engine)

83H 84H

_TBLPNT Storage area for top address of lookup table (H)(When using table-lookup method) (L)


5-9

(4) Rule Data Structure

Fig. 5-6 Rule Data Structure

(5) Lookup Table Data Structure

Fig. 5-7 Lookup Table Data Structure

Address of membership function data storage area MF of input 1

2 (Plus 1)

Rule 1Number of rules

4

* MF: Membership function

_RULEPNT

+0 +1, 2, +4+3 +5

MF of input 11 (Minus 1)

MF of output8 (Large 1)

MF of input 24 (Plus 2)

Rule 4

Membership function 1 ("Minus 1")

MF of output6 (Small 2)

MF of input 24 (Plus 2)

_FLRC value0Eh

_FLRB value00h

_FLRA value00h

Membership function 8 ("Large 1")

_FLRC value0Eh

_FLRC value3Fh - 3Ah

_FLRB value3Fh - 3Ah

_FLRA value3Ah

_FLRD value3Fh - 3Ah

+12 +13 +14

+0 +1 +3+2

+29 +30 +31 +32

* _FUZOUT(n, m): Value of _FUZOUT when _FUZIN1 = n and _FUZIN2 = m

_FUZOUT(0, 1)

_FUZOUT(0, 63)

_FUZOUT(0, 0)

_TBLPNT

_FUZOUT(1, 0)

_FUZOUT(63, 0)

_FUZOUT(63, 1)

_FUZOUT(63, 63)

+0 +1 +64+63

+4032 +4033 +4095

5.3 Sample Program


5.3 Sample Program

5.3.1 Settings of Initial Register and RAM (1) Initialization of F2RU-6 control status register

(2) Initialization of F2RU-6 label registers A - D

0 0 0 0 0 0 0 0

7 6 5 4 3 2 1 0

**BUSY: Busy flag (Read-only, then set to "0")

ERR: Clear error flag

YFIF: Clear fill end interrupt request flag

FCSR

FRIF: Clear consequence processing interrupt request flag


DFIF: Clear de-fuzzify interrupt request flag

FIE: Clear fuzzy interrupt enable bit


0 0 0 0 0 0 0 0

7 6 5 4 3 2 1 0

**Membership function label parameter A

FLRA

0 0 0 0 0 0 0 0

7 6 5 4 3 2 1 0

**Membership function label parameter B

FLRB

0 0 0 0 0 0 0 0

7 6 5 4 3 2 1 0

**Membership function label parameter C

FLRC

0 0 0 0 0 0 0 0

7 6 5 4 3 2 1 0

**Membership function label parameter D

FLRD

5.3 Sample Program

5-11

(3) Initialization of F2RU-6 data register X

(4) Initialization of F2RU-6 grade register Y


0 0 0 0 0 0 0 0

7 6 5 4 3 2 1 0

**Data parameter

FDRX

0 0 0 0 0 0 0 0

7 6 5 4 3 2 1 0

**Grade value

FGRY


* *

5.3 Sample Program


(5) Setting input 1 (rotational deviation) data save area

(6) Setting input 2 (cumulative rotational deviation) data save area

(7) Setting output (control quantity) data save area

(8) Setting rule top address storage area

(9) Setting lookup table top address storage area

(10) Setting rule number save area

7 6 5 4 3 2 1 0Area used to store input 1 (rotational deviation) dataInitial value = 00H

_FUZIN1

∗ Unused

* *

7 6 5 4 3 2 1 0Area used to store input 2 (cumulative rotational deviation) dataInitial value = 00H

_FUZIN2

* *

∗ Unused

7 6 5 4 3 2 1 0Area used to store the output (control quantity) dataInitial value = 00H

_FUZOUT

* *

∗ Unused

7 6 5 4 3 2 1 0Area used to store the rule top addressInitial value = 0000H_RULEPNT

+1

Upper

Lower

7 6 5 4 3 2 1 0Area used to store the lookup table top addressInitial value = 0000H_TBLPNT

+1

Upper

Lower

7 6 5 4 3 2 1 0Area used to store the current rule numberInitial value = 00H

RULENO

5.3 Sample Program

5-13


Fig. 5-8 Flowchart

RESET

Set stack pointer/program status register

_FUZZYFRUFuzzy logic processing


Initialize RAM area

Only when using the fuzzy logic engine

_SYSINTInitialize resources

other than the F2RU-6

Initialize F2RU-6 control status register

Initialize F2RU-6 data register X

Initialize F2RU-6 grade register Y

_GETFUZINControl inputprocessing

Select logic rules

_PUTFUZOUTControl output

processing

_FUZZYTBLFuzzy logic processing


Select lookup table

When using the table-lookup method

When using the fuzzy logic engine

Initialize F2RU-6 label registers A - D

MAIN:

5.3 Sample Program


Fig. 5-9 Flowchart

_FUZZYFRU

Yes

Initialize F2RU-6 control status register

No

Initialize rule number

FRUIF1Condition processing 1

Any unprocessed rule?

RET

(Calculate input 1 grade)



Initialize F2RU-6 membership function

memory

Initialize rule processing address

(EP)

FRUIF2Condition processing

2

FRUTHENConsequence

processing

Update rule number

FRUDEFUZDe-fuzzify processing

(Calculate input 2 grade and perform min operation)

(Expand output membership function)

5.3 Sample Program

5-15

Fig. 5-10 Flowchart

Yes

No

Initialize grade register Y

Execution of membership function memory fill command

complete?

Initialize F2RU-6 membership function memory

Set membership function memory

fill command

5.3 Sample Program


Fig. 5-11 Flowchart

FRUIF1

Yes

Calculate data storage address of input 1

membership function (henceforth MF)

Execution of grade calculation 1

command complete?

Set MF data A in label register A


No

RET

Set MF data B in label register B

Set input 1 data in data register X

Set MF data C in label register C

Set MF data D in label register D

Set grade calculation 1 command in command

register

(Calculate input 1 grade)

5.3 Sample Program

5-17

Fig. 5-12 Flowchart

FRUIF2

Yes

Calculate data storage address of input 2


Execution of grade calculation 2

command complete?



No

RET


Set input 2 data in data register X



Set grade calculation 2 command in command

register

(Calculate input 2 grade and perform min operation)

(Request grade calculation and min operation)

5.3 Sample Program


Fig. 5-13 Flowchart

FRUTHEN

Yes

Calculate data storage address of output


Execution of consequence processing command complete?


Consequence processing

No

RET




Set consequence processing command in

command register

(Expand output membership function)

(Request consequence processing)

5.3 Sample Program

5-19

Fig. 5-14 Flowchart

FRUDEFUZ

Yes

Set de-fuzzify command in

command register

Execution of de-fuzzify com-mand complete?

De-fuzzify processing

No

RET

Store logic result in output data

storage area

(Request de-fuzzify processing)

No errors?

Set #0FFH in output data storage area

Yes

No

5.3 Sample Program


Fig. 5-15 Flowchart

_FUZZYTBL

Calculate table offset


RET


Calculate data address

Store logic result in output data storage area

5.3 Sample Program

5-21

NAME FUZZY;*******************************************************;* *;* Sample Fuzzy Logic Program *;* *;*******************************************************;;* Assembling this program with the value in the following line set to 0produces the table-lookup version of this program.

&SET FFRURESON1; 1 = Logic engine version, Other value= Table-lookup version;************************************;* MB94140 Resource Definition *;************************************RES94140 DIRSEG ABS

ORG 0031HFLRA RB 1 ; FFRU-6 label register AFLRB RB 1 ; FFRU-6 label register BFLRC RB 1 ; FFRU-6 label register CFLRD RB 1 ; FFRU-6 label register DFDRX RB 1 ; FFRU-6 data register XFGRY RB 1 ; FFRU-6 grade register YFCOMR RB 1 ; FFRU-6 command registerFCSR RB 0 ; FFRU-6 control status registerBUSY RBIT 1 ; Busy flag 1: Busy, 0: ReadyERR RBIT 1 ; Error flag 1: Error, 0: No errorYFIF RBIT 1 ; Fill complete interrupt request 1: CompleteFRIF RBIT 1 ; Consequence processing complete interrupt

request 1: CompleteDFIF RBIT 1 ; De-fuzzify processing complete interrupt

requestFIE RBIT 1 ; Fuzzy interrupt enable 1: Enable

RBIT 1 ; Not usedRBIT 1 ; Not used

;RES94140 ENDS;;*******************************;* RAM Definition *;*******************************RAM DIRSEG ABS

PUBLIC _FUZIN1,_FUZIN2,_FUZOUTORG 0080H

_FUZIN1 RB 1 ; Input 1 data storage area_FUZIN2 RB 1 ; Input 2 data storage area_FUZOUT RB 1 ; Output data storage area

&IF FFRURESON EQ 1&THEN

_RULEPNT RW 1 ; Storage area for rule top addressRULENO RB 1 ; Storage area for current rule number

&ELSE

5.3 Sample Program


_TBLPNT RW 1 ; Storage area for lookup table top address&ENDIF

;RAM ENDS;RAMHIGH DSEG ABS

ORG 0250HST_AREA RB 48 ; Stack areaST_AREA_EXRAMHIGH ENDS;; FFRU6 Command DefinitionsF6NOP EQU 00H ; NOPF6FIL EQU 01H ; Membership function memory fillF6CGM EQU 02H ; Consequence processingF6DFZ EQU 03H ; De-fuzzifyF6MW EQU 04H ; Write membership function memory 1F6MWI EQU 05H ; Write membership function memory 2

(with automatic address increment)F6MR EQU 06H ; Read membership function memory 1F6MRI EQU 07H ; Read membership function memory 2

(with automatic address increment)F6CG EQU 08H ; Grade calculation 1F6CGA EQU 09H ; Grade calculation 2 (with min operation);FUZZY CSEG PUBLIC

EXTRN _SYSINITEXTRN _GETFUZINEXTRN _PUTFUZOUT

;*******************************;* Initial Settings *;*******************************RESET:

MOVW SP,#ST_AREA_EX ; Set stack pointer;

MOVW A,#0030H ; Set program status registerMOVW PS,A

;; Initialize RAM areaMOV _FUZIN1,#00HMOV _FUZIN2,#00HMOV _FUZOUT,#00H&IF FFRURESON EQ 1&THENMOVW A,#0000HMOVW _RULEPNT,AMOV RULENO,#00H&ELSEMOVW A,#0000HMOVW _TBLPNT,A&ENDIF

5.3 Sample Program

5-23

&IF FFRURESON EQ 1&THENMOV FCSR,#00000000B ; Initialize FFRU-6 control status registerMOV FLRA,#00H ; Initialize FFRU-6 label registers A - DMOV FLRB,#00HMOV FLRC,#00HMOV FLRD,#00HMOV FDRX,#00H ; Initialize FFRU-6 data register XMOV FGRY,#00H ; Initialize FFRU-6 grade register Y&ENDIF

CALL _SYSINIT ; Initialize other resources;*******************************;* Main Routine *;*******************************MAIN:

CALL _GETFUZIN ; Control input processing;

&IF FFRURESON EQ 1&THENMOVW A,#_RULE ; Select logic rulesMOVW _RULEPNT,ACALL _FUZZYFRU ; Fuzzy logic processing (fuzzy logic engine)

;&ELSEMOVW A,#_TABLE ; Select lookup tableMOVW _TBLPNT.ACALL _FUZZYTBL ; Fuzzy logic processing (table-lookup

method)&ENDIF

;CALL _PUTFUZOUT ; Control output processing

;JMP MAIN&IF FFRURESON EQ 1&THEN

;*************************************************;* Fuzzy Logic (Fuzzy Logic Engine Version) *;*************************************************_FUZZYFRU:

MOV FCSR,#00000000B ; Initialize FFRU-6 control status register; Initialize FFRU-6 Membership Function

MemoryMOV FGRY,#00H ; Initialize FFRU-6 grade register YMOV FCOMR,#F6FIL ; Set membership function memory fill

commandFUZZYFRU01:

BBS BUSY,FUZZYFRU01 ; Execution of membership function memory fill command complete?

MOVW A,_RULEPNT ; Initialize rule number

5.3 Sample Program


MOV A,@AMOV RULENO,A;MOVW A,#0000H ; Initialize rule processing address (EP)MOVW A,#0000HMOV A,RULENOMOV A,RULENOCLRCADDCW ACLRCADDCW AMOVW A,_RULEPNTCLRCADDCW AMOVW EP,A

;FUZZYFRU10:

MOV A,RULENO ; Is there an unprocessed rule?BZ FUZZYFRU20 ; No

;FUZZYFRU11:

CALL FRUIF1 ; Condition processing 1 (calculate input 1 grade)CALL FRUIF2 ; Condition processing 2 (calculate input 2 grade

and perform min operation)CALL FRUTHEN ; Consequence processing (expand output

membership function)MOV A,RULENO ; Update rule numberDECW AMOV RULENO,AJMP FUZZYFRU10

;FUZZYFRU20:

CALL FRUDEFUZ ; De-fuzzify processingRET

;****************************************************;* Condition Processing 1 (Calculate Input 1 Grade) *;****************************************************FRUIF1:

MOVW A,_RULEPNT ; Input 1 membership function (henceforth MF)MOVW IX,A ; Calculate data storage addressMOVW A,#0000HMOV A,@EPDECW ACLRCROLC AROLC AMOVW A,@IX+1CLRCADDCW AMOVW IX,A

5.3 Sample Program

5-25

;MOV A,@IX+0 ; Set MF data A in label register AMOV FLRA,AMOV A,@IX+1 ; Set MF data B in label register BMOV FLRB,AMOV A,@IX+2 ; Set MF data C in label register CMOV FLRC,AMOV A,@IX+3 ; Set MF data D in label register DMOV FLRD,AMOV A,_FUZIN1 ; Set input 1 data in data register XAND A,#03FHMOV FDRX,AMOV FCOMR,#F6CG ; Set grade calculation 1 command in command

registerFRUIF101:

BBS BUSY,FRUIF101 ; Is execution of the grade calculation 1 command complete?

RET;*********************************************;* Condition Processing 2 (Calculate Input 2 *;* Grade and Perform min Operation) *;*********************************************FRUIF2:

MOVW A,_RULEPNT ; Input 2 membership function (henceforth MF)MOVW IX,A ; Calculate data storage addressMOVW A,#0000HINCW EPMOV A,@EPDECW ACLRCROLC AROLC AMOVW A,@IX+1CLRCADDCW AMOVW IX,A

;MOV A,@IX+0 ; Set MF data A in label register AMOV FLRA,AMOV A,@IX+1 ; Set MF data B in label register BMOV FLRB,AMOV A,@IX+2 ; Set MF data C in label register CMOV FLRC,AMOV A,@IX+3 ; Set MF data D in label register DMOV FLRD,AMOV A,_FUZIN2 ; Set input 2 data in data register XAND A,#03FHMOV FDRX,AMOV FCOMR,#F6CGA ; Set grade calculation 2 command in command

registerFRUIF201:

5.3 Sample Program


BSS BUSY,FRUIF201 ; Execution of grade calculation 2 command complete?

RET;**********************************;* Consequence Processing (Expand*;* Output Membership Function) *;**********************************FRUTHEN:

MOVW A,_RULEPNT ; Output membership function (henceforth MF)MOVW IX,A ; Calculate data storage addressMOVW A,#0000HINCW EPMOV A,@EPDECW ACLRCROLC AROLC AMOVW A,@IX+1CLRCADDCW AMOVW IX,A

;MOVW A,EPMOVW A,#0005HCLRCSUBCW AMOVW EP,A

;MOV A,@IX+0 ; Set MF data A in label register AMOV FLRA,AMOV A,@IX+1 ; Set MF data B in label register BMOV FLRB,AMOV A,@IX+2 ; Set MF data C in label register CMOV FLRC,AMOV A,@IX+3 ; Set MF data D in label register DMOV FLRD,AMOV FCOMR,#F6CGM ; Set consequence processing command in

command registerFRUTHEN01:

BSS BUSY,FRUTHEN01 ; Execution of consequence processing command complete?

RET;*******************************;* De-Fuzzify Processing *;*******************************FRUDEFUZ:

MOV FCOMR,#F6DFZ ; Set de-fuzzify command in command registerFRUDEFUZ01:

BBS BUSY,FRUDEFUZ01 ; Execution of de-fuzzify command complete?BBS ERR,FRUDEFUZ02 ; No errors?MOV A,FDRX ; Store logic result in output data storage area

5.3 Sample Program

5-27

AND A,#3FHJMP FRUDEFUZ03

FRUDEFUZ02:MOV A,#0FFH ; Set #0FFH in output data save area

FRUDEFUZ03:MOV _FUZOUT,ARET

;;***************************************;* Membership Function Definitions *;***************************************MFFU1 equ 1 ; "Minus 1"MFSEI1 equ 2 ; "Plus 1"MFFU2 equ 3 ; "Minus 2"MFSEI2 equ 4 ; "Plus 2"MFSYO1 equ 5 ; "Small 1"MFSYO2 equ 6 ; "Small 2"MFDAI2 equ 7 ; "Large 2"MFDAI1 equ 8 ; "Large 1";

; A ,B ,C ,DMFTBL:

db 00H ,00H-00H,0EH-00H,2AH-00H ; MFFU1db 14H ,32H-14H,3FH-14H,3FH-14H ; MFSEI1db 00H ,00H-00H,10H-00H,28H-00H ; MFFU2db 18H ,30H-18H,3FH-18H,3FH-18H ; MFSEI2db 00H ,00H-00H,00H-00H,06H-00H ; MFSYO1db 0EH ,12H-0EH,12H-0EH,1AH-0EH ; MFSYO2db 26H ,2EH-26H,2EH-26H,32H-26H ; MFDAI2db 3AH ,3FH-3AH,3FH-3AH,3FH-3AH ; MFDAI1

;*******************************;* Logic Rule Definitions *;*******************************_RULE:

db 4 ; Number of rulesdw MFTBL ; MF data top address; Input 1, Input 2, Outputdb MFSEI1 ,MFSEI2 ,MFDAI1 ; Rule 1db MFFU1 ,MFFU2 ,MFSYO1 ; Rule 2db MFSEI1 ,MFFU2 ,MFDAI2 ; Rule 3db MFFU1 ,MFSEI2 ,MFSYO2 ; Rule 4

&ELSE;************************************************;* Fuzzy Logic Processing (Table-Lookup Method) *;************************************************_FUZZYTBL:

MOVW A,#0000H ; Calculate table offsetMOVW A,#0000HMOV A,_FUZIN2AND A,#03FH

5.3 Sample Program


MOV A,_FUZIN1AND A,#03FHCLRCRORC ASWAPRORC ASWAPCLRCRORC ASWAPRORC ACLRCADDCW A

;MOVW A,_TBLPNT ; Calculate data addressCLRCADDCW A

;MOV A,@AMOV _FUZOUT,A ; Store logic result in output data storage areaRET

;;********************************;* Lookup Table Definitions *;********************************_TABLE:

; +0 +1 +2 +3 +4 +5 +6 +7DB 02H, 02H, 02H, 02H, 02H, 02H, 02H, 02H ; +0DB 02H, 02H, 02H, 02H, 02H, 02H, 02H, 02H ; +8

(Omitted)

DB 02H, 06H, 06H, 08H, 0AH, 0AH, 0CH, 0CH ; +1048DB 0DH, 0FH, 0FH, 10H, 10H, 11H, 12H, 12H ; +1056

(Omitted)

DB 2DH, 2DH, 2DH, 2EH, 2FH, 30H, 30H, 30H ; +3096DB 32H, 33H, 33H, 34H, 36H, 39H, 39H, 39H ; +3104

(Omitted)

DB 3EH, 3EH, 3EH, 3EH, EH, 3EH, 3EH, 3EH ; +4080DB 3EH, 3EH, 3EH, 3EH, 3EH, 3EH, 3EH, 3EH ; +4088

&ENDIFFUZZY ENDS;;*******************************;* Vector Addresses *;*******************************

5.3 Sample Program

5-29

VECTOR CSEG ABSORG 0FFFDHDB 00H ; Reset modeDW RESET ; Reset vector

VECTOR ENDSEND

6.1 Overview

6-3

Chapter 6:Up/Down Counters

6.1 Overview

Some F2MC-8L Family products have internal up/down counter resources.

Up/down counters are suitable as rotary encoder counters or similar. The counters enable easyimplementation of applications such as monitoring and control of rotational direction and number ofrevolutions or calculating rotational speed.



MB89670 SeriesMain clock = 10.00 MHz

(2) Operation specification

The sample program uses the up/down counter function to count the phase difference and then calculatedisplacement values from the output waveform of a dual-axis (vertical and horizontal) rotary encoder.(Monitoring the vertical and horizontal displacement values enables the coordinates to be calculated.)The displacement value is determined from the phase difference count value over a 20 ms period.

Figure 6-1 shows the output waveform of a rotary encoder and the corresponding phase difference count.The maximum number of encoder revolutions per second is 20.

Therefore, from the number of encoder points shown in Figure 6-1 (the points marked as l), T > 6.25 ms.

Fig. 6-1

1 2 3 4 5CW CCW

OUT-A

OUT-B

T

* A phase difference count occurs at the timings indicated by ↓.

Count

T


6-4 Chapter 6: Up/Down Counters


Input: P33/UDB1 (B phase waveform input port for the horizontal axis encoder)P34/UDA1 (A phase waveform input port for the horizontal axis encoder)P36/UDB2 (B phase waveform input port for the vertical axis encoder)P37/UDA2 (A phase waveform input port for the vertical axis encoder)



VCC

RST

X0

10.00MHz

X1

VCC

VCC

VSS

OUT-BOUT-A

Rotary encoder (for horizontal axis)

Rotary encoder (for vertical axis)

VCC

OUT-BOUT-A

P33P34

P36P37


6-5



No

Yes

End

Save registers

8/16-bit timer interrupt

Post-processing after displacement value calculation

Is there a displacement value ready notification?

Initial processing

Main routine

Store U/D counter

Update horizontal displacement

Clear U/D counter

Update vertical displacement

Restore registers

Set displacement value ready notification




• Up/down counter (to determine rotational direction and number of revolutions)

• 8/16-bit timer counter (provides the 20 ms timing)






24H T2CR 8/16-bit timer control register 2

25H T1CR 8/16-bit timer control register 1

26H T2DR Upper 8/16-bit timer data register

27H T1DR Lower 8/16-bit timer data register

30H UDCR1 Up/down count register 1

31H UDCR2 Up/down count register 2

32H CCRA1 Up/down counter control register A-1

33H CCRA2 Up/down counter control register A-2

34H CCRB1 Up/down counter control register B-1

35H CCRB2 Up/down counter control register B-2

36H CSR1 Up/down counter status register 1

37H CSR2 Up/down counter status register 2

7CH ILR1 Interrupt level register 1


6-7

(3) RAM allocation

(4) Flag contents



80H FLAG Flag area

81H X Horizontal displacement (absolute value)

82H Y Vertical displacement (absolute value)

83H RCR1_BUF Counter storage buffer 1

84H RCR2_BUF Counter storage buffer 2

Table 6-3 Contents of Address 80H

Bit Symbol Function

0 F_XY_ENDDisplacement value ready notify flag

1: Displacement value ready

1 F_X_UNDERSign flag for horizontal displacement direction

1: Minus direction

2 F_Y_UNDERSign flag for vertical displacement direction

1: Minus direction

6.3 Sample Program


6.3 Sample Program

6.3.1 Settings of Initial Register and RAM(1) Settings of system clock control register

(2) Settings of port 3 I/O direction register

(3) Settings of interrupt level register

(4) Data register settings for the 8/16-bit timer

0 0 0 0 0 0 1 1

7 6 5 4 3 2 1 0

CS1, CS0: System operating clock 4/fch = 0.40 µs

WT1, WT0: Oscillation stabilization time 214/fch = 1.60 ms

* * **

SYCC

* Set unused bits to "0".

0 0 0 0 0 0 0 0

7 6 5 4 3 2 1 0

P33, P34, P36, P37: Set as input ports

** * *

DDR3


0 0 1 1 1 1 1 1

7 6 5 4 3 2 1 0

Set 8/16-bit timer interrupt level to "1".

** * *

ILR1


**

Lower

T2DRT1DR

Upper Data register = 1562(20ms÷12.8msec = 1562)

7 6 5 4 3 2 1 0

6.3 Sample Program

6-9

(5) Settings of up/down counter control register A-1

(6) Settings of up/down counter control register A-2

(7) Settings of up/down counter status register 1

(8) Settings of up/down counter status register 2

0 0 1 1 0 0 0 0

7 6 5 4 3 2 1 0

UDCC1: Counter-1 clear bit

CMS11, CMS10: Mode selection = Multiply-by-four phase difference count

* * *

CCRA1


*

MOCH: Operating channel selection = 8-bit mode

0 0 1 1 0 0 0 0

7 6 5 4 3 2 1 0

UDCC2: Counter-2 clear bit

CMS21, CMS20:Mode selection = Multiply-by-four phase difference count

* * **

CCRA2


*

1 0 0 0 0 0 0 0

7 6 5 4 3 2 1 0

CSTR1: Start/stop count 1 operation (1 = start)

* * * *

CSR1


** *

1 0 0 0 0 0 0 0

7 6 5 4 3 2 1 0

CSTR2: Start/stop count 2 operation (1 = start)

* * * *

CSR2


** *

6.3 Sample Program


(9) Settings of 8/16-bit timer control register 1

(10) Settings of 8/16-bit timer control register 2

0 1 0 0 1 0 0 1

7 6 5 4 3 2 1 0

TC10, 11: Timer clock source = 12.8 µs

T1CR


** *

STR1: Timer start bit

T1IF: Clear interrupt request bit

T1IE: Interrupt enable setting

0 0 0 0 0 0 0 0

7 6 5 4 3 2 1 0

T2CR


** * *****

6.3 Sample Program

6-11

Fig. 6-4 Flowchart

No

Yes

Initialize counter control register A

Set 8/16-bit timer data register to 20 ms

Set interrupt level8/16-bit timer: level 1

Set I/O ports

Clear RAM

Set stack pointer

Set system control register

Initialize counter status registers 1 and 2

Displacement value ready notify flag = "1"?

Initialize 8/16-bit timer control register

RESET

XY_PRC

Clear displacement value ready notify flag

MAIN

6.3 Sample Program


Fig. 6-5 Flowchart

No

Yes

XY_EDIT_INT

RET I


Clear interrupt source


8/16-bit timer interrupt processing

Set the horizontal displacement direction sign flag

Is displacement in minus direction?

Clear U/D count registers 1 and 2

Save U/D count registers 1 and 2 in count storage buffers 1 and 2

Clear the horizontal displacement direction sign flag

Horizontal displacement ← Count storage buffer 1

Horizontal displacement ← #0 - Count storage buffer 2

Set the vertical displacement direction sign flag

Displacement in minus direction?

Vertical displacement ← Count storage buffer 2

Vertical displacement ← #0 - Count storage buffer 2

Clear the vertical displacement direction sign flag

Set displacement value ready notify flag

No

Yes

6.3 Sample Program

6-13

NAME UD_CONT;*******************************************************;* *;* Sample Up/Down Counter Program *;* *;*******************************************************;;*******************************;* MB89670 Family *;*******************************RES670 DIRSEG ABS

ORG 0007HSYCC RB 0 ; System control registerCS0 RBIT 1 ; System clock selection bitCS1 RBIT 1 ; System clock selection bitSCS RBIT 1 ; System clock select bitWT0 RBIT 1 ; Oscillation stabilization time selection bitWT1 RBIT 1 ; Oscillation stabilization time selection bit


SCM RBIT 1 ; System clock monitor bit;

ORG 000DHDDR3 RB 1 ; Port 3 I/O direction register;

ORG 0024HT2CR RB 0 ; 8/16-bit timer control register 2STR2 RBIT 1 ; Timer start bitSTP2 RBIT 1 ; Timer stop bitCS20 RBIT 1 ; Clock source selection bitCS21 RBIT 1 ; Clock source selection bitOS20 RBIT 1OS21 RBIT 1T2IE RBIT 1 ; Interrupt enable bitT2IF RBIT 1 ; Interrupt request flag bit;T1CR RB 0 ; 8/16-bit timer control register 1STR1 RBIT 1 ; Timer start bitSTP1 RBIT 1 ; Timer stop bitTC10 RBIT 1 ; Clock source selection bitTC11 RBIT 1 ; Clock source selection bitOS10 RBIT 1 ; Rectangular wave output control bitOS11 RBIT 1 ; Rectangular wave output control bitT1IE RBIT 1 ; Interrupt enable bitT1IF RBIT 1 ; Interrupt request bit;T2DR RB 1 ; 8/16-bit timer data registerT1DR RB 1 ; 8/16-bit timer data register;

ORG 0030HUDCR1 RB 1 ; Up/down count register 1

6.3 Sample Program


UDCR2 RB 1 ; Up/down count register 2;CCRA1 RB 0 ; Up/down counter control register A-1UDCC1 RBIT 1 ; UDCR1 clear bit

RBIT 1RBIT 1RBIT 1

CMS10 RBIT 1 ; CH-1 mode selection bitCMS11 RBIT 1 ;

RBIT 1MOCH RBIT 1 ; Operating channel selection bit;CCRA2 RB 0 ; Up/down counter control register A-2UDCC2 RBIT 1 ; UDCR2 clear bit

RBIT 1RBIT 1RBIT 1

CMS20 RBIT 1CMS21 RBIT 1 ; CH-2 mode selection bit

RBIT 1RBIT 1

;CCRB1 RB 1 ; Up/down counter control register B-1;CCRB2 RB 1 ; Counter control register B-2;CSR1 RB 0 ; Counter status register 1

RBIT 1RBIT 1RBIT 1RBIT 1RBIT 1RBIT 1RBIT 1

CSTR1 RBIT 1 ; Counter 1 start bit;CSR2 RB 0 ; Up/down counter status register 2


CSTR2 RBIT 1 ; Counter 2 start bit;

ORG 007CHILR1 RB 1 ; Interrupt level register 1;RES670 ENDS;

6.3 Sample Program

6-15

;*******************************;* RAM Definition *;*******************************RAM DIRSEG ABS;

ORG 0080H;FLAG RB 0 ; Flag areaF_XY_END RBIT 1 ; Displacement value ready notify flagF_X_UNDER RBIT 1 ; Horizontal displacement direction sign flagF_Y_UNDER RBIT 1 ; Vertical displacement direction sign flag

RBIT 1 ; UnusedRBIT 1 ; UnusedRBIT 1 ; UnusedRBIT 1 ; UnusedRBIT 1 ; Unused

;X RB 1 ; Horizontal displacement valueY RB 1 ; Vertical displacement valueRCR1_BUF RB 1 ; Up/down counter value storage buffer 1RCR2_BUF RB 1 ; Up/down counter value storage buffer 2;RAM ENDS;

SSEGRB 40H ; Set stack size = 40HENDS

;PRG CSEG PUBLIC;

EXTRN XY_PRC;;*******************************;* Initial Settings *;*******************************RESET:;

MOV SYCC,#00010011B ; Set system control register;

MOVW SP,#280h ; Set stack pointer;

MOVW A,#70hMOVW PS,A ; Set PS (interrupt level "11")

;MOVW EP,#80H ; Clear RAM 80h - 200h

RAMCLR:MOVW A,#0MOV @EP,AINCW EPMOVW A,EPMOVW A,#200H

6.3 Sample Program


CMPW ABNZ RAMCLR

;MOV DDR3,#00000000B ; Set P33, P34, P36, P37 as input ports

;MOV ILR1,#00111111B ; Set interrupt level of 8/16-bit timer to "1"

;MOVW A,#1562MOVW T2DR,A ; Set 8/16-bit timer data register to 20 ms

;MOV CCRA1,#00110000B; Initialize up/down counter control register A-1MOV CCRA2,#00110000B; Initialize up/down counter control register A-2

;MOV CSR1,#10000000B ; Initialize up/down counter status register 1

; (start counter)MOV CSR2,#10000000B ; Initialize up/down counter status register 2

; (start counter);

MOV T1CR,#01001001B ; Initialize 8/16-bit timer control register 1 (start timer)

MOV T2CR,#00000000B ; Initialize 8/16-bit timer control register 2;;;*******************************;* Main Routine *;*******************************MAIN:

BBC F_XY_END,MAIN ; There a displacement value ready notification?;

CLRB F_XY_END ; Clear displacement value ready notify flag;

CALL XY_PRC ; Post-processing after calculating coordinates;

JMP MAIN;;;************************************************;* Displacement Value Calculation Routine *;* (8/16-Bit Timer Interrupt) *;************************************************XY_EDIT_INT:

PUSHW A ; Save accumulatorXCHW A,TPUSHW A ; Save temporary accumulator

;CLRB T1IF ; Clear interrupt request flag

;MOV A,UDCR1 ; Store up/down count register 1 valueMOV RCR1_BUF,A ;

;MOV A,UDCR2 ; Store up/down count register 2 value

6.3 Sample Program

6-17

MOV RCR2_BUF,A;;

CLRB UDCC1 ; Clear up/down count register 1CLRB UDCC2 ; Clear up/down count register 2

;MOV A,RCR1_BUF ; Displacement in minus direction?BP XY_100 ; If no, jump to XY_100

;SETB F_X_UNDER ; Set horizontal displacement direction sign flag

;MOV A,#0 ; Calculate absolute valueMOV A,RCR1_BUF ;CLRC ;SUBC A ;

;MOV X,A ; Set horizontal displacement value

;XY_050:

MOV A,RCR2_BUF ; Displacement in minus direction?BP XY_200 ; If no, jump to XY_200

;SETB F_Y_UNDER ; Set vertical displacement direction sign flag

;MOV A,#0 ; Calculate absolute valueMOV A,RCR2_BUF ;CLRC ;SUBC A ;

;MOV Y,A ; Set vertical displacement value

;XY_080:

SETB F_XY_END ; Set displacement value ready notify flag;

POPW A ; Restore temporary accumulatorXCHW A,TPOPW A ; Restore accumulator

;RETI

;;XY_100:

CLRB F_X_UNDER ; Clear horizontal displacement direction sign flag;

MOV A,RCR1_BUFMOV X,A ; Set horizontal displacement value

;JMP XY_050

;XY_200:

CLRB F_Y_UNDER ; Clear vertical displacement direction sign flag;

6.3 Sample Program


MOV A,RCR2_BUFMOV Y,A ; Set vertical displacement value

;JMP XY_080

;PRG ENDS;;;*******************************;* Vectors *;*******************************VECT CSEG ABS;

ORG 0FFF4H;

DW XY_EDIT_INT ; 8/16-bit timer interrupt;

ORG 0FFFDH;

DB 00H ; Operating mode data;

DW RESET ; Reset vector;VECT ENDS

END

7.1 Overview

7-3

Chapter 7:Inverter Control

7.1 Overview

The MB89860/850 Series have internal timer units suitable for inverter control. The timer in the timer unitcan be used in either up or down mode, and an inverter output can be implemented by setting a valueobtained from a magnetic flux control PWM algorithm as the compare value.

The timer unit output pin outputs "H" when the timer unit's count is greater than the compare value, and"L" when the count is less than the compare value. An interrupt is generated when the timer value goes to00h. Use the interrupt to calculate the next compare value.

The sample program uses the above resource to produce an inverter output for a 3-phase induction motorusing a magnetic flux control PWM algorithm.



MB89860/850 SeriesMain clock = 10.0 MHz

(2) Inverter control specification

• Start-up frequency: 10.0 Hz

• Maximum frequency: 150.0 Hz

• Carrier frequency: 2.5 kHz

• V/F characteristics: See table (sample program)

• Deadtime: 19.2 µs

• Cushion rate time: 1 Hz/0.25 s

• Output type: Magnetic flux control PWM


7-4 Chapter 7: Inverter Control

(3) Magnetic flux control type PWM output

Figure 7-1 is a diagram showing the principle of an inverter. Figure 7-2 shows the voltage vector as afunction of the transistors for each phase.

Fig. 7-1 Diagram Showing the Principle of an Inverter

Fig. 7-2 Voltage Vector

The time that the vector spends in the dotted line sections of Figure 7-2 can be calculated as shown inFigure 7-3.

GND

3-phase induction motor

W phase

V phase

U phase

×6

Region 5

Region 4

Region 3

Region 2

Region 1

Region 0

Im

V6 (0, 1, 0)

V1 (0, 1, 1)

V5 (1, 1, 0)

V2 (0, 0, 1)V3 (1, 0, 1)

V4 (1, 0, 0)

V0 (0, 0, 0)

V7 (1, 1, 1)

Ti:Tj:Tz= ∆φSIN(π/3 - α): ∆φSIN α:

Vi - ∆φ SIN(π/3 - α) + SIN α32

=TSK•SIN(π/3 - α) : TSK•SIN α: Ts− (Ti+Tj)


7-5

Fig. 7-3 Geometry Used to Calculate the Vector Duration

Figure 7-4 shows the U, V, and W phase switching patterns for this case.

Fig. 7-4 Three-Phase Waveform Output

Considering the border between sample periods, a sample period can be split into first and second halves.These have the same vector durations and select the same vectors, but the vector sequence for the first andsecond halves are different and the start and end of the sample period have the same logic levels.

The following shows the combination and sequence of voltage vectors for each region.

Region 0 V0(0, 0, 0) → V2(0, 0, 1) → V1(0, 1, 1)→ V1(0, 1, 1) → V2(0, 0, 1) → V0(0, 0, 0)

Vj

α

Ti

Tz

Tj

Vi

∆φ

Ts

Ti Tj Tz

U

V

t

0

1

Vi Vj Vz

w

t

t

0

1

0

1



Region 1 V2(0, 0, 1) → V3(1, 0, 1) → V7(1, 1, 1)→ V7(1, 1, 1) → V3(1, 0, 1) → V2(0, 0, 1)

Region 2 V0(0, 0, 0) → V4(1, 0, 0) → V3(1, 0, 1)→ V3(1, 0, 1) → V4(1, 0, 0) → V0(0, 0, 0)

Region 3 V4(1, 0, 0) → V5(1, 1, 0) → V7(1, 1, 1)→ V7(1, 1, 1) → V5(1, 1, 0) → V4(1, 0, 0)

Region 4 V0(0, 0, 0) → V6(0, 1, 0) → V5(1, 1, 0)→ V5(1, 1, 0) → V6(0, 1, 0) → V0(0, 0, 0)

Region 5 V6(0, 1, 0) → V1(0, 1, 1) → V7(1, 1, 1)→ V7(1, 1, 1) → V1(0, 1, 1) → V6(0, 1, 0)

Fig. 7-5 Compare Value and 3-Phase Waveform Output Timing


Output: P41 - P43 (U, V, and W phase outputs)

500 × 0.4µs = 200 µs

250

1 0 1 125 249 2 1 0

HL1

0

2

Compare value

498

500

250

250 125

250

HL

HL

HL

HL

250

249

125


7-7



VCC

VSS

RST

U P41

V P42

W P43

U P44

V P45

W P46

X0

P47

×6

10.0 MHz

3-phase induction motor

VCC

X1

MB89860/850

P40





No

Yes

Cushion rate timer count

Any inverter operation command?

Inverter control processing

Initial settings

Main routine

Generate frequency of interest

Inverter stopped?

Calculate data required to obtain Ti and Tj

Start waveform output


Update output frequency

Calculate data required to obtain Ti and Tj

Stop waveform output

End

End

Set waveform output

Zero detect interrupt Timer interrupt

End

Yes

No


7-9


• 8-bit PWM timer

• Timer unit (for waveform output)




0EH PDR4 Port 4 data register

0FH DDR4 Port 4 I/O direction register

1CH CTR1 8-bit PWM control register 1

1DH CMR1 8-bit PWM compare register 1

2DH ZOCTR Output control register for zero detect

2EH CLRBRH Compare clear buffer register H

2FH CLRBRL Compare clear buffer register L

30H TCSR Timer control status register

31H CICR Compare interrupt control register

32H TMCR Timer mode control register

33H COER Compare/port switching register

34H CMCR Compare buffer mode control register

35H DTCR Deadtime timer control register

36H DTSR Deadtime setting register

37H OCTR, OCTBR Output control register, buffer register

38H OCPR0, OCPBR0 Output compare register 0, buffer register 0

3AH OCPR1, OCPBR1 Output compare register1, buffer register 1

3CH OCPR2, OCPBR2 Output compare register2, buffer register 2

3EH OCPR3, OCPBR3 Output compare register3, buffer register 3

7CH ILR1 Interrupt level setting #1

7DH ILR2 Interrupt level setting #2



(3) RAM allocation

(4) Flag contents



80H FLAG0 Flag area

81H FRECM Target frequency storage area

82H FREOUT Output frequency storage area

83H TIME Cushion rate timer counter

84H PHASE_UPDATE Storage area for phase update quantity

86H PHASE_POINT Storage area for phase pointer

88H TI Ti value storage area

8AH TITJ Ti + Tj value storage area

8CH WK0 Work area

8EH DIVI_WORK_I Work area for division (dividend)

108H VF_COEFF VF coefficient

109H INPUT_WORD1 Storage area for 2-byte data for multiplication (109:H 10A:L)

10BH INPUT_WORD2 Storage area for 2-byte data for multiplication (10B:H 10C:L)

10DH PLACE_X2Y2 WORD1(L) x WORD2(L) operation result work area

10FH PLACE_X1Y2 WORD1(H) x WORD2(L) operation result work area

111H PLACE_X2Y1 WORD1(L) x WORD2(H) operation result work area

113H PLACE_X1Y1 WORD1(H) x WORD2(H) operation result work area

115H SUBORDINATE_W Lower multiplication/addition area

117H H_POSITION_W Upper multiplication/addition area

119H DIVI_WORK1 Work area for division (dividend)

11BH DIVI_WORK2 Work area for division (divisor)


Bit Symbol Function

0 FINVDR Inverter stopped flag 0: Stopped, 1: Running

7.3 Sample Program

7-11

7.3 Sample Program

7.3.1 Settings of Initial Register and RAM(1) Settings of I/O port


1 1 1 1 0 0 0 1

7 6 5 4 3 2 1 0

∗ ∗∗P41 - P43: Output "L"

*As these are unused ports, set to "H".

PDR4

∗ ∗

0 0 0 0 1 1 1 0

7 6 5 4 3 2 1 0

∗ ∗∗P41 - P43: Set as output ports

*As these are unused ports, set as inputs.

DDR4

∗ ∗

1 1 1 1 1 1 0 1

7 6 5 4 3 2 1 0

∗ ∗∗L01, L00: Set timer unit 1 interrupt level to 1.


ILR1

∗ ∗

1 1 1 1 1 1 1 0

7 6 5 4 3 2 1 0

∗ ∗∗L41, L40: Set PWM timer 1 interrupt level to 2.


ILR2

∗ ∗

∗

∗

7.3 Sample Program


(3) Settings of 8-bit PWM timer control register

(4) Settings of 8-bit PWM timer compare register

(5) Set flags

(6) Phase angle pointer setting

0 0 1 0 0 0 0 1

7 6 5 4 3 2 1 0

∗TIE: Enable output of counter interrupt


CTR1

OE: General-purpose port

TIR: Clear interrupt request flag

TPE: Start counter

P1, P0: 16 instruction cycles (0.4 x 16 = 6.4 µs)

P/TX: Timer selection

1 0 0 1 1 0 1 1

7 6 5 4 3 2 1 0

CMR1 Register used to store the compare value

Example: To generate an interrupt every 1 ms

1msec = 998.4 µsec= 6.4 × 156 (CMR = 155)

..

0 0 1 0 0 0 0 1

7 6 5 4 3 2 1 0

∗FINVDR: Clear inverter stopped flag

FLAG0

∗ ∗ ∗∗∗∗

PHASE _POINT+1

Phase angle pointer valueInitial value = 0000H

7 6 5 4 3 2 1 0

7.3 Sample Program

7-13


Fig. 7-8 Flowchart

Set interrupt level

Set I/O ports

Clear condition code to 0

Set register bank

Set interrupt level

_INVCONInverter control processing

Generate target frequency

_INITIALInitial settings

Set stack pointer

RESET

MAIN

_INITIAL

RET

Set timer interrupt

Initialize RAM area

Enable interrupts

Initial settings

7.3 Sample Program


Fig. 7-9 Flowchart

No

Yes

_INVCON

Yes

Yes

Yes

No

No

No

Inverter stopped?

Target F ≠ 0?


_STOP_OPRHalt waveform output

Set inverter stopped flag

Output F ← #start-up frequency

Target F ≠ Output F?

Clear inverter stopped flag

Set cushion rate timer

1_REPHASECalculate phase update quantity

Set cushion rate timer

Cushion rate timer OVF?

Update output frequency

Set phase update quantity _REPHASE

Calculate phase update quantity

_SET_VFSet VF coefficient

_SET_VFSet VF coefficient

Set phase update quantity

_BEGIN_OPRStart waveform output

RET

7.3 Sample Program

7-15

Fig. 7-10 Flowchart

_REPHASE _SET_VF

RET RET

RET

Enable deadtime output

Clear phase pointer to 0

Lookup VF coefficient from table using output F

Phase update quantity = 6872 x half-carrier/2 x output F

Calculate phase update quantity

_BEGIN_OPR

Disable OCPR0 - OCPR3 interrupts

Enable zero detect interrupt

Channel 0: Transfer on compare matchChannels 1 - 3: Enable buffer to register transfer on count #00H

Set 1 instruction cycle mode 1 to up/down timer mode

Set RTO1 - RTO3 timer units

Set deadtime8 instruction cycles (3.2 µs)6 counts (19.2 µs)

_N_C_O_MSet initial waveform output

RTO1 - RTO3Up counting: "1"Down counting: "0"

Set deadtime3-phase outputPositive polarity, non-overlapping

Start timer

Set half-carrier in clear register

Specify zero detect time

1

1

Start waveform output

Set VF coefficient

7.3 Sample Program


Fig. 7-11 Flowchart

_N_C_O_M _STOP_OPR

RET

RET

Set initial waveform output

Calculate region N and phase angle α from phase pointer

U(OCPBR1) ← #half-carrier

V(OCPBR2) ← #half-carrier - Ti

W(OCPBR3) ← #half-carrier - Ti + Tj

Halt waveform output

Halt timer

Ti=@(SINφ+253-α)XVFX2/256Tj=@(SINφ+253-α)XVFX2/256

7.3 Sample Program

7-17

Fig. 7-12 Flowchart

_COMPARE

RET I

Ti=@(SINφ+253-α)XVFX2/256Tj=@(SINφ+253-α)XVFX2/256

Restore A, T

Set region N output

Calculate region N and phase angle α from phase pointer


Save A, T

Zero detect interrupt

7.3 Sample Program


Fig. 7-13 Flowchart

E

No

Yes

E

E

E

1

1

2

Yes

Yes

Yes

No

No

No

Region = #2?

Region = #1?



U(OCPBR1) ← #half-carrier

Region = #0?

Set region N output 1/2

Region = #3?V(OCPBR2) ← #half-carrier

U(OCPBR1) ← #half-carrier - Ti + Tj

W(OCPBR3) ← #half-carrier - Ti

U(OCPBR1)

V(OCPBR2)←Ti+Tj

W)OCPBR3)←#0

V(OCPBR2)←Ti

W(OCPBR3)←Ti+Tj

U(OCPBR1)←#0

2/2

7.3 Sample Program

7-19

Fig. 7-14 Flowchart

E

E

E

3

Yes

Yes

No

No

Region = #5?

Region = #4?

1/2

2

3



U(OCPBR1) ←#half-carrier

V(OCPBR2) ← #half-carrier - Ti + Tj

W(OCPBR3) ← #half-carrier

U(OCPBR1) ← #half-carrier - Ti

Set region N output 2/2

U(OCPBR1)←Ti+Tj

V(OCPBR2)←#0

W(OCPBR3)←Ti

1/2

1/2

7.3 Sample Program


Fig. 7-15 Flowchart

Yes

No

Restore A, T

Decrement cushion rate timer

Cushion rate timer ≠ #0?

Start timer


Save A, T

Timer interrupt (every 1 ms)

RET I

_TIMERINT

7.3 Sample Program

7-21

NAME INVCON;*******************************************************;* Sample Inverter Control Program *;*******************************************************;

SSEGPUBLIC STACK_TOPRW 32

SATCK_TOP RW 0ENDS

;;********************************;* MB89850 Resource Definitions *;********************************RES850 DIRSEG ABS

ORG 0EHPDBR ; Port data buffer registerPDR4 RB 1 ; Port 4 data registerDDR4 RB 1 ; Port 4 I/O direction register;

ORG 1CHCTR1 RB 0 ; 8-bit PWM control register 1TIE RBIT 1 ; Counter interrupt enable bitOE RBIT 1 ; Output signal control bitTIR RBIT 1 ; Interrupt request flag bitTPE RBIT 1 ; Counter operation enable bitP0 RBIT 1 ; Clock selection bitP1 RBIT 1 ; Clock selection bitPTX RBIT 1 ; Timer/PWM operation switching bitCMR1 RB 1 ; 8-bit PWM compare register 1;

ORG 2DHZOCTR RB 1 ; Output control register for zero detectCLRBR RW 1 ; Compare clear buffer register (2E:2F) = (H:L);

ORG 30HTCSR RB 0 ; Timer control status registerTMIR RBIT 1 ; Timer overflow/compare clear match interrupt

request flagTMIE RBIT 1 ; Timer interrupt enable bitTZIR RBIT 1 ; Zero detect interrupt request flagTZIE RBIT 1 ; Zero detect interrupt enable bitTCIR RBIT 1 ; Timer clear interrupt request flagTCIE RBIT 1 ; Timer clear interrupt enable bitSTCR RBIT 1 ; Software timer clear bit;

ORG 31HCICR RB 0 ; Compare interrupt control registerCIR0 RBIT 1 ; OCPR0 = "1" for timer value timingCIR1 RBIT 1 ; OCPR1 = "1" for timer value timingCIR2 RBIT 1 ; OCPR2 = "1" for timer value timing

7.3 Sample Program


CIR3 RBIT 1 ; OCPR3 = "1" for timer value timingCIE0 RBIT 1 ; Interrupt request bit for CIR0CIE1 RBIT 1 ; Interrupt request bit for CIR1CIE2 RBIT 1 ; Interrupt request bit for CIR2CIE3 RBIT 1 ; Interrupt request bit for CIR3;

ORG 32HTMCR RB 0 ; Timer mode control registerTCS0 RBIT 1 ; Timer count clock select bitTCS1 RBIT 1 ; Timer count clock select bitCES0 RBIT 1 ; Edge select bit for external trigger inputCES1 RBIT 1 ; Edge select bit for external trigger input

RBIT 1 ; DummyTSTX RBIT 1 ; Test mode setting bitMODE RBIT 1 ; Timer count mode setting bitTMST RBIT 1 ; Timer start/stop bit;

ORG 33HCOER RB 0 ; Compare/port switching registerRTO0 RBIT 1 ; Real-time output setting bitRTO1 RBIT 1 ; Real-time output setting bitRTO2 RBIT 1 ; Real-time output setting bitRTO3 RBIT 1 ; Real-time output setting bit;

ORG 34HCMCR RB 0 ; Compare buffer mode control registerBFS0 RBIT 1 ; Buffer mode selection bit 0BFS1 RBIT 1 ; Buffer mode selection bit 1TREN RBIT 1 ; Transfer enable bit;

ORG 35HDTCR RB 0 ; Deadtime timer control registerDT0 RBIT 1 ; Deadtime timer control bitDT1 RBIT 1 ; Deadtime timer control bitDTIF RBIT 1 ; DTTI pin input interrupt request flagDTIE RBIT 1 ; DTTI pin input interrupt enable bitTOC0 RBIT 1 ; DTTI pin input conditions setting bitTOC1 RBIT 1 ; DTTI pin input conditions setting bitTOCE RBIT 1 ; 3-phase waveform output halt/input enable bitDMOD RBIT 1 ; 3-phase waveform output mode selection bit;

ORG 36HDTSR RB 0 ; Deadtime setting registerDTC0 RBIT 1 ; Deadtime count registerDTC1 RBIT 1 ; Deadtime count registerDTC2 RBIT 1 ; Deadtime count registerDTC3 RBIT 1 ; Deadtime count register

RBIT 1 ; DummyRBIT 1 ; Dummy

NRSL RBIT 1 ; Noise cancel function selection bitDCSL RBIT 1 ; Deadtime timer clock source selection bit

7.3 Sample Program

7-23

;ORG 37H

OCTBR RB 1 ; Output control buffer registerOCPBR0 RW 1 ; Output compare buffer register 0 (38:39) = (H:L)

OCPBR1 RW 1 ; Output compare buffer register 1 (40:41) = (H:L)



;ORG 7CH

;

ILR1 RB 1 ; Interrupt level setting register #1ILR2 RB 1 ; Interrupt level setting register #2ILR3 RB 1 ; Interrupt level setting register #3RES850 ENDS;;*******************************;* RAM Definitions *;*******************************RAM DIRSEG ABS

ORG 80HFLAG0 RB 0 ; Flag areaFINVDR RBIT 1 ; Inverter stopped flag


;FRECM RB 1 ; Target frequency storage areaFREOUT RB 1 ; Output frequency storage areaTIME RB 1 ; Cushion rate timer counterPHASE_UPDATE RB 2 ; Storage area for phase update quantityPHASE_POINT RB 2 ; Phase pointer storage areaTI RB 2 ; Ti value storage areaTITJ RB 2 ; Ti + Tj value storage areaWK0 RB 2 ; Work areaDIVI_WORK_I RB 2 ; Work area for division (dividend)RAM ENDS;DRAM DSEG ABS

ORG 108HVF_COEFF RB 1 ; VF coefficientINPUT_WORD1 RB 2 ; Storage area for 2-byte data for multiplication

(109:H 10A:L)

7.3 Sample Program


INPUT_WORD2 RB 2 ; Storage area for 2-byte data for multiplication (10B:H 10C:L)

PLACE_X2Y2 RB 2 ; WORD1(L) x WORD2(L) operation result work area

PLACE_X1Y2 RB 2 ; WORD1(H) x WORD2(L) operation result work area

PLACE_X2Y1 RB 2 ; WORD1(L) x WORD2(H) operation result work area

PLACE_X1Y1 RB 2 ; WORD1(H) x WORD2(H) operation result work area

SUBORDINATE_WRB 2 ; Multiplication result area (lower)H_POSITION_W RB 2 ; Multiplication result area (upper)DIVI_WORK_1 RB 2 ; Work area for division (dividend)DIVI_WORK_2 RB 2 ; Work area for division (divisor)DRAM ENDS;SIDOU EQU 10 ; Start-up frequencyRATE EQU 250 ; Cushion rate timerC_HACARR EQU 250 ; Half -carrierCALDAT EQU 6872 ; Phase update quantity

; = 65536 x output F x 1 carrier period; = 6872 x output F x half-carrier x 1/10000H x 1/2

;INV CSEG;*******************************;* Initial Settings *;*******************************RESET:

MOVW SP,#STACK_TOP ; Set stack pointer;

CALL _INITIAL ; Initial settings;;*******************************;* Main Routine *;*******************************MAIN:

MOV FRECM,#56 ; Generate target frequency;

CALL _INVCON ; Inverter control processingJMP MAIN

;;*******************************;* Initial Settings *;*******************************_INITIAL:

MOVW A,PS ; Set interrupt levelMOVW A,#0030HANDW AMOVW PS,A

;MOVW A,PS ; Set register bank

7.3 Sample Program

7-25

MOVW A,#00FFHANDW AMOVW PS,A

;MOVW A,PS ; Clear condition code to 0MOVW A,#0FF30HANDW AMOVW PS,A

;; Set I/O portsMOV DDR4,#00001110B ; Set P41 - P43 as outputsMOV PDR4,#11110001B ; Set P41 - P43 output to "0"

;; Set interrupt levelsMOV ILR1,#11111101B ; Timer unit 1: Level = 1MOV ILR2,#11111110B ; PWM timer 1: Level = 2

;MOV CTR1,#00100001B ; Enable interrupt 0.4 µs x 16

;MOV CMR1,#156-1 ; Interrupt period 998.4 µs

;CLRB FINVDR ; Clear inverter stopped flag

;MOVW A,#0000MOVW PHASE_POINT,A ; Initialize phase angle pointer

;SETB TPE ; Start count

;SETI ; Enable interrupts

;RET

;;*******************************;* Inverter Control Processing *;*******************************_INVCON:

MOVW A,#0000MOV A,FRECM ; Target F ≠ 0 ?BZ INV_040 ; No

;BBS FINVDR,INV_010 ; Inverter stopped? No

;SETB FINVDR ; Set inverter stopped flag

;MOV FREOUT,#SIDOU ; Set start frequency

;MOV TIME,#RATE ; Set cushion rate timer

;CALL _REPHASE ; Calculate phase update quantityMOVW PHASE_UPDATE,A ; Set phase update quantity

;

7.3 Sample Program


CALL _SET_VF ; Set VF coefficient;

CALL _BEGIN_OPR ; Start waveform outputJMP INV_EXIT

;INV_010:

MOVW A,#0000MOV A,FREOUTMOV A,FRECMCMP A ; Output F ≠ target F? NoBZ INV_EXIT

;MOV A,TIMEBNZ INV_EXIT ; Cushion rate timer OVF? No

;MOV TIME,#RATE ; Set cushion rate timer

;MOVW A,#0000MOV A,FRECMMOV A,FREOUTCMP A ; Target F < output F?BNC INV_020 ; No

;MOV A,FREOUT ; Output F-1CLRCSUBC A,#1MOV FREOUT,AJMP INV_030

;INV_020:

MOV A,FREOUT ; Output F+1CLRCADDC A,#1MOV FREOUT,A

;INV_030:

CALL _REPHASE ; Calculate phase update quantityMOVW PHASE_UPDATE,A ; Set phase update quantity

;CALL _SET_VF ; Fetch VF coefficientJMP INV_EXIT

INV_040:CLRB FINVDR ; Set inverter stopped flag

;CALL _STOP_OPR ; Stop waveform output

;INV_EXIT:

RET;;***************************************************; Name _REPHASE *

7.3 Sample Program

7-27

; Function Calculate phase update quantity *; Input FREOUT *; Output A <- New phase update quantity *; Registers used A *;***************************************************_REPHASE:

MOVW A,#C_HCARR ; INPUT_WORD1 <-SWAP ; (#C_HCARR/2) x FREOUTCLRC ;RORC A ;SWAP ;RORC A ;MOV A,FREOUT ;MULU A ;MOVW INPUT_WORD1,A ;

;MOVW A,#CALDAT ; INPUT_WORD2 <- #6872MOVW INPUT_WORD2,A ;

;CALL _CALCU_MULTIPLY_2WORD ; 2-word multiply = word x wordMOVW A,H_POSITION_WRET

;;************************************; Name _SET_VF *; Function Set VF_COEFF *; Input FREOUT *; Output VF_COEFF *; Registers used A *;************************************_SET_VF:

MOVW A,#0MOV A,FREOUT ; Use output frequencyMOVW A,#TBLVF ; to lookup VF tableCLRCADDCW AMOV A,@AMOV VF_COEFF,A

;RET

;;*****************************************; Name _BEGIN_OPR *; Function Start waveform output *; Input None *; Output None *; Registers used A *;*****************************************_BEGIN_OPR:

MOVW A,#0000MOVW PHASE_POINT,A ; PHASE_POINT <- 0

7.3 Sample Program


MOVW A,PS ; RP <- 0MOVW A,#00FFHANDW AMOVW PS,A

;MOV TCSR,#00001000B ; Timer control status register

;MOV CICR,#0 ; Compare interrupt control register

; Disable OCPR0-OCPR3 interrupt requests

;MOV COER,#00001110B ; Compare/port switching register

;MOV TMCR,#01100000B ; Timer mode control register

;MOV CMCR,#00000110B ; Compare buffer mode control register

;MOV DTSR,#10000110B ; Deadtime setting register

;MOV DTCR,#00000010B ; Deadtime timer control register

;MOV OCTBR,#01010111B ; Output control buffer register

;CALL _N_C_O_M ; Set OCPBR1-OCPBR3

;MOV ZOCTR,#00001110B ; Output control register for zero detect

;MOVW A,#C_HCARR ; Compare clear buffer registerMOVW CLRBR,A

;SETB TMST ; Start timerSETB DT0 ; Enable deadtime output

;RET

;;***************************************************; Name _N_C_O_M *; Function Generate initial compare value *; Input PHASE_UPDATE *; VF_COEFF *; Output None *; Registers used A, R3, R4 *;***************************************************_N_C_O_M:

MOVW A,PHASE_POINT ; PHASE_POINT <-MOVW A,PHASE_UPDATE ; PHASE_POINT + PHASE_UPDATECLRCADDCW AMOVW PHASE_POINT,A

;MOVW DIVI_WORK1,A ; A <- PHASE_POINT/43

7.3 Sample Program

7-29

MOVW A,#43MOVW WK0,AMOVW A,#WK0MOVW IX,ACALL _CALCU_DIVIDE

;MOVW A,#254 ; A <- A/254DIVU A

;MOV R3,A ; N regionXCH A,TMOV R4,A ; α phase angle

;MOV A,#253 ; A <- 253 - αCLRCSUBC A,R4

;MOVW A,#SIN0 ; A <- (A + #SIN0)ADDCW AMOV A,@A

;MOV A,VF_COEFF ; A< <- A x VFMULU A

;AND A,#80H ; A <- A/256 x 2ROLC ASWAPROLC ASWAPROLC ASWAP

;MOVW A,#C_HCARR ; Set TICMPW ABNC LIMIT_FFH_1_0XCHW A,T

LIMIT_FFH_1_0:MOVW TI,A

;MOVW A,#0 ; A <- (α + #SINO)MOV A,R4CLRCMOVW A,#SIN0ADDCW AMOV A,@A

;MOV A,VF_COEFF ; A <- A x VFMULU A

;AND A,#80 ; A <- A/256 x 2 (TJ)ROLC A

7.3 Sample Program


SWAPROLC ASWAPROLC ASWAP

;MOVW A,TI ; A <- A + TICLRCADDCW A

;MOVW A,#C_HCARR ; Check upper limitCMPW ABNC LIMIT_FFH_2_0XCHW A,T

LIMIT_FFH_2_0:MOVW TITJ,A

;MOVW A,#C_HCARR ; OCPBR1 <- #C_HCARRMOVW OCPBR1,A

;MOVW A,TI ; OCPBR2 <- #C_HCARR - TISUBCW AMOVW OCPBR2,A

;MOVW A,#C_HCARR ; OCPBR3 <- #C_HCARR - TITJMOVW A,TITJSUBCW AMOVW OCPBR3,A

;RET

;;*****************************************; Name _STOP_OPR *; Function Halt inverter output *; Input None *; Output None *; Registers used None *;*****************************************_STOP_OPR:

CLRB TMST ; Halt timerMOV DTCR,#01101010B ; Halt deadtime timer

; Hold at inactive levelRET

;;**********************************************; Name CALCU_MULTIPLY_2WORD *; Function 2-word = word x word *; Input INPUT_WORD1, INPUT_WORD2 *; Output A <- Upper word of result *; Registers used A *;**********************************************

7.3 Sample Program

7-31

_CALCU_MULTIPLY_2WORD:MOV A,INPUT_WORD1+1 ; X2Y2MOV A,INPUT_WORD2+1MULU AMOVW PLACE_X2Y2,A

;MOV A,INPUT_WORD1 ; X1Y2MOV A,INPUT_WORD2+1MULU AMOVW PLACE_X1Y2,A

;MOV A,INPUT_WORD1+1 ; X2Y1MOV A,INPUT_WORD2MULU AMOVW PLACE_X2Y1,A

;MOV A,INPUT_WORD1 ; X1Y1MOV A,INPUT_WORD2MULU AMOVW PLACE_X1Y1,A

;MOVW A,PLACE_X1Y2 ; SUBORDINATE_W <-SWAP ; (X1Y2 << 8) + X2Y2AND A,#0MOVW A,PLACE_X2Y2CLRCADDCW AMOVW SUBORDINATE_W,A

;BNC LBL_SUBORDINATE ; Carry?MOVW A,PLACE_X1Y1,A ; PLACE_X1Y1 ++INCW AMOVW PLACE_X1Y1,A

LBL_SUBORDINATE:MOVW A,PLACE_X2Y1 ; SUBORDINATE_W <-SWAP ; SUBORDINATE_W + (X2Y1 << 8)AND A,#0MOVW A,SUBORDINATE_WCLRCADDCW AMOVW SUBORDINATE_W,A

;BNC LBL_HIGH_POSITION ; Carry?MOVW A,PLACE_X1Y1 ; PLACE_X1Y1 ++INCW AMOVW PLACE_X1Y1,A

LBL_HIGH_POSITION:MOVW A,PLACE_X1Y1 ; H_POSITION_W <-MOVW A,PLACE_X1Y2 ; X1Y1 + (X1Y2 >> 8)+(X2Y1 >> 8)AND A,#0SWAP

7.3 Sample Program


CLRCADDCW AMOVW A,PLACE_X2Y1AND A,#0SWAPADDCW AMOVW H_POSITION_W,ARET

;;**************************************************; Name CALCU_DIVIDE *; Function (word) <- (word)/(byte) *; Input DIVI_WORK1: dividend (word) *; IX: Save address of byte data *; Output A <- Result (word) *; Registers used A *;**************************************************_CALCU_DIVIDE

MOVW A,DIVI_WORK1AND A,#0SWAPMOVW A,@IXAND A,#0SWAPDIVU AMOV DIVI_WORK2,AXCH A,TSWAPMOV A,DIVI_WORK +1MOVW A,@IXAND A,#0SWAPDIVU AMOVW A,DIVI_WORK2XCH A,TRET

;;*****************************************; Name _COMPARE *; Function Generate NEXT_COMP *; Input PHASE_UPDATE *; VF_COEFF *; Output None *; Registers used Register bank 0 *; r0: (unused) *; r1: (unused) *; r2: (unused) *; r3: Region N *; r4: Phase a *; r5: (unused) *; r6: (unused) *

7.3 Sample Program

7-33

; r7: (unused) *;*****************************************_COMPARE:

PUSHW A ; Save AXCHW A,TPUSHW A ; Save T

;CLRB TZIR ; Clear interrupt requestMOVW A,#0010H ; Bank <- 0, disable interrupt, interrupt

level <- 1MOVW PS,A

;MAG_NEXT_COMP:

MOVW A,PHASE_POINT ; PHASE_POINTMOVW A,PHASE_UPDATE ; <- PHASE_POINT + PHASE_UPDATEADDCW AMOVW PHASE_POINT,A

;AND A,#0 ; A (word) <- PHASE_POINT/43SWAPMOVW A,#43DIVU AMOV DIVI_WORK_I,AXCH A,TSWAPMOV A,PHASE_POINT+1MOVW A,#43DIVU AMOVW A,DIVI_WORK_IXCH A,T

;MOVW A,#254 ; A <- A/254DIVU A ; T <- remainder

;MOV R3,A ; R3 <- Region NXCH A,T ; R4 <- Phase angle αMOV R4,A

;MOV A,#253 ; A <- 253 - R4 AH, TH = 0CLRCSUBC A,R4

;MOVW A,#SIN0 ; A <- (A + #SINO)ADDCW AMOV A,@A


;AND A,#80H ; A <- A/256 x 2ROLC A

7.3 Sample Program


SWAPROLC ASWAPROLC ASWAP

;MOVW A,#C_HCARR ; Check upper limitCMPW ABNC LIMIT_FFH_1XCHW A,T

LIMIT_FFH_1:MOVW TI,A ; Set TI

;MOVW A,#0 ; A <- (R4 + #SINO)MOV A,R4CLRCMOVW A,#SIN0ADDCW AMOV A,@A


;AND A,#80H ; A <- A/256 x 2 (TJ)ROLC ASWAPROLC ASWAPROLC ASWAP

;MOVW A,TI ; A <- A + TICLRCADDCW A

;MOVW A,#C_HCARR ; Check upper limitCMPW ABNC LIMIT_FFH_2XCHW A,T

LIMIT_FFH_2:MOVW TITJ,A ; Set TITJ

;CMP R3,#0 ; Branch based on regionBNZ B_N1

B_N0:;**********Region 0*******************MOVW A,#C_HCARR ; OCPBR1 <- #C_HCARRMOVW OCPBR1,A

;MOVW A,TI ; OCPBR2 <- #C_HCARR-TISUBCW A

7.3 Sample Program

7-35

MOVW OCPBR2,A;

MOVW A,#C_HCARR ; OCPBR3 <- #C_HCARR-TITJMOVW A,TITJSUBCW AMOVW OCPBR3,AJMP EXIT_ZERO_INT

;B_N1:

CMP R3,#1BNZ B_N2;**********Region 1*******************MOVW A,TI ; OCPBR1 <- TIMOVW OCPBR1,A

;MOVW A,TITJ ; OCPBR2 <- TITJMOVW OCPBR2,A

;MOVW A,#0 ; OCPBR3 <- #0MOVW OCPBR3,AJMP EXIT_ZERO_INT

;B_N2:

CMP R3,#2BNZ B_N3;**********Region 2*******************MOVW A,#_HCARR ; OCPBR2 <- #C_HCARRMOVW OCPBR2,A

;MOVW A,TITJ ; OPCBR1 <- #C_HCARR-TITJSUBCW AMOVW OCPBR1,A

;MOVW A,#C_HCARR ; OCPBR3 <- #C_HCARR-TIMOVW A,T1SUBCW AMOVW OCPBR3,AJMP EXIT_ZERO_INT

;B_N3:

CMP R3,#3BNZ B_N4;**********Region 3*******************MOVW A,TI ; OCPBR2 <- TIMOVW OCPBR2,A

;MOVW A,TITJ ; OCPBR3 <- TITJMOVW OCPBR3,A

;MOVW A,#0 ; OCPBR1 <- #0MOVW OCPBR1,A

7.3 Sample Program


;JMP EXIT_ZERO_INT ; RETURN

;B_N4:

CMP R3,#4BNZ B_N5;**********Region 4*******************MOVW A,#C_HCARR ; OCPBR1 <- #C_HCARR-TIMOVW A,TISUBCW AMOVW OCPBR1,A

;MOVW A,#C_HCARR ; OCPBR3 <- #C_HCARRMOVW OCPBR3,A

;MOVW A,TITJ ; OCPBR2 <- #C_HCARR-TITJSUBCW AMOVW OCPBR2,AJMP EXIT_ZERO_INT

;B_N5:

CMP R3,#5BNZ B_N6;**********Region 5*******************MOVW A,TITJ ; OCPBR1 <- TITJMOVW OCPBR1,A

;MOVW A,#0 ; OCPBR2 <- #0MOVW OCPBR2,A

;MOVW A,TI ; OCPBR3 <- TIMOVW OCPBR3,A

;JMP EXIT_ZERO_INT

;B_N6:

;**********Region 6*******************MOVW A,#C_HCARR ; OCPBR1 <- #C_HCARRMOVW OCPBR1,A

;MOVW A,TI ; OCPBR2 <- #C_HCARRSUBCW AMOVW OCPBR2,A

;MOVW A,#C_HCARR ; OCPBR3 <- #C_HCARR-TITJMOVW A,TITJSUBCW AMOVW OCPBR3,A

;EXIT_ZERO_INT:

POPW A ; Restore T

7.3 Sample Program

7-37

XCHW A,TPOPW A ; Restore A

;RETI

;;***********************************; Name _TIMERINT *; Function 1 ms interrupt *; Input TIME *; Output None *; Registers used A *;***********************************_TIMERINT:

PUSHW A ; Save AXCHW A,TPUSHW A ; Save T

;MOV CMR1,#156 ; Set 1 ms (156 x 10 MHz divided by 64)MOV CTR1,#00101001B ; Start timer

;MOV A,TIME ; Cushion rate timer set?BZ TINT_010 ; No

;MOV A,TIME ; Decrement timerCLRCSUBC A,#1MOV TIME,A

;TINT_010:

POPW A ; Restore TXCHW A,TPOPW A ; Restore A

;RETI

;;***********************************************; Name SIN0, VFTBL *; Function SIN0: SIN table *; VFTBL: VF coefficient table *; where VF = 2 x output F + 3 *; Input None *; Output None *; Registers used None *;***********************************************SIN0:

DB 000H, 001H, 002H, 003H, 004H, 005H, 006H, 007HDB 008H, 009H, 00AH, 00BH, 00CH, 00DH, 00EH, 00FHDB 010H, 011H, 012H, 014H, 015H, 016H, 017H, 018HDB 019H, 01AH, 01BH, 01CH, 01DH, 01EH, 01FH, 020HDB 021H, 022H, 023H, 024H, 025H, 026H, 027H, 028HDB 02AH, 02BH, 02CH, 02DH, 02EH, 02FH, 030H, 031H

7.3 Sample Program


DB 032H, 033H, 034H, 035H, 036H, 037H, 038H, 039HDB 03AH, 03BH, 03CH, 03DH, 03EH, 03FH, 040H, 041HDB 042H, 043H, 044H, 045H, 046H, 047H, 048H, 049HDB 04AH, 04BH, 04CH, 04DH, 04EH, 04FH, 050H, 051HDB 052H, 053H, 054H, 055H, 056H, 057H, 058H, 059HDB 05AH, 05BH, 05CH, 05DH, 05EH, 05FH, 060H, 061HDB 062H, 063H, 064H, 065H, 066H, 067H, 068H, 069HDB 06AH, 06BH, 06CH, 06DH, 06EH, 06FH, 070H, 071HDB 072H, 072H, 073H, 074H, 075H, 076H, 077H, 078HDB 079H, 07AH, 07BH, 07CH, 07DH, 07EH, 07FH, 07FHDB 080H, 081H, 082H, 083H, 084H, 085H, 086H, 087HDB 088H, 089H, 089H, 08AH, 08BH, 08CH, 08DH, 08EHDB 08FH, 090H, 090H, 091H, 092H, 093H, 094H, 095HDB 096H, 096H, 097H, 098H, 099H, 09AH, 09BH, 09CHDB 09CH, 09DH, 09EH, 09FH, 0A0H, 0A1H, 0A1H, 0A2HDB 0A3H, 0A4H, 0A5H, 0A5H, 0A6H, 0A7H, 0A8H, 0A9HDB 0A9H, 0AAH, 0ABH, 0ACH, 0ADH, 0ADH, 0AEH, 0AFHDB 0B0H, 0B0H, 0B1H, 0B2H, 0B3H, 0B3H, 0B4H, 0B5HDB 0B6H, 0B6H, 0B7H, 0B8H, 0B9H, 0B9H, 0BAH, 0BBHDB 0BBH, 0BCH, 0BDH, 0BEH, 0BEH, 0BFH, 0C0H, 0C0HDB 0C1H, 0C2H, 0C2H, 0C3H, 0C4H, 0C5H, 0C5H, 0C6HDB 0C7H, 0C7H, 0C8H, 0C8H, 0C9H, 0CAH, 0CAH, 0CBHDB 0CCH, 0CCH, 0CDH, 0CEH, 0CEH, 0CFH, 0CFH, 0D0HDB 0D1H, 0D1H, 0D2H, 0D3H, 0D3H, 0D4H, 0D4H, 0D5HDB 0D5H, 0D6H, 0D7H, 0D7H, 0D8H, 0D8H, 0D9H, 0D9HDB 0DAH, 0DBH, 0DBH, 0DCH, 0DCH, 0DDH, 0DDH, 000H

;TBLVF:

DB 21,21,21,21,21,21,21,21,21,21; 0 Hz (dummy)DB 23,25,27,29,31,33,35,37,39,41; 10 HzDB 43,45,47,49,51,53,55,57,59,61; 20 HzDB 63,65,67,69,71,73,75,77,79,81; 30 HzDB 83,85,87,89,91,93,95,97,99,101; 40 HzDB 103,105,107,109,111,113,115,117,119,121; 50 HzDB 123,125,127,129,131,133,135,137,139,141; 60 HzDB 143,145,147,149,151,153,155,157,159,161; 70 HzDB 163,165,167,169,171,173,175,177,179,181; 80 HzDB 183,185,187,189,191,193,195,197,199,201; 90 HzDB 203,205,207,209,211,213,215,217,219,221; 100 HzDB 213,215,217,219,221,223,225,227,229,231; 110 HzDB 233,235,237,239,241,243,245,247,249,251; 120 HzDB 253,255,255,255,255,255,255,255,255,255; 130 HzDB 255,255,255,255,255,255,255,255,255,255; 140 HzDB 255 ; 150 Hz

INV ENDS;;*******************************; Vector Addresses *;*******************************VECTOR CSEG ABS

ORG OFFF2H

7.3 Sample Program

7-39

DW _TIMERINT ; PWM timer 1ORG OFFFAHDW _COMPARE ; Timer unit 1

;

ORG OFFFDHDB 00H ; Reset modeDW RESET ; Reset vector

VECTOR ENDSEND

8.1 Overview

8-3

Chapter 8: Realtime I/O

8.1 Overview

Some F2MC-8L Series products have internal realtime I/O.Realtime I/O consists of 16-bit timers, input capture, and output compare. These can be used to enableeasy measurement of periods (or frequencies) and pulse widths, and easy port outputs settings.


8.2.1 Summary SpecificationThe sample program uses the realtime I/O to perform PID control of a motor.

(1) Target microcontroller

MB89660 SeriesMain clock = 10.00 MHz

(2) Realtime I/O control specification

Starts and stops the motor based on the motor start on/off switch.Motor control uses PID control to set the motor output and operates with a 10 ms pitch provided by thetimebase timer. The control uses the realtime I/O resources.

• 16-bit timer

The counter output value produced by this timer is used as the base time for the input capture andoutput compare units. The period of the timer count clock is set at 3.2 µs (for a 10 MHz sourceoscillation).

• Input capture

The 16-bit timer value is stored in the input capture at the motor rotation period signal timing (risingedge). The period is then calculated from the stored timer value and the timer operating clock. Thecalculated period is stored in RAM (for use in calculating PID control).

• Output compare

When a match between the timer value and output compare register value is detected, the match signalis output to the transfer control section of the data latch and an interrupt request generated. Theinterrupt processing sets the output compare register value for the next port output and inverts the OUTbit.


Input: P00: Motor start on/off switch P33/RTI0: Motor rotation period signal (input capture)Output: P35/RTO0: Motor control pulse output (output compare register)


8-4 Chapter 8: Realtime I/O



8.2.3 Data Format

Fig. 8-2 Transmission Data Format

VCC

RST

X0

10.00MHz

X1

VCC

VCC

VSS

P35/RTO0P33/RTI0 VCC

P00SW

Motor control pulse output Motor with encoderMotor rotation period signal

(1)

(1)′

(2) (3) (4) (6)(5) (7)

0

(2)′ (3)′ (4)′ (5)′ (6)′ (7)′

1

1

1

1

1

1

1

10

0

0

0

0

0

0

001

1

1

1 1

1

00

0

0

* The motor rotation period signals ((1)- (7)) provide the time periods used to determine the H and L widths of the motor control pulse outputs ((1)′ - (7)′).The H and L widths of the motor control pulse outputs ((1)′- (7)′) are calculated using the time periods of the motor rotation period signals ((1) - (7)) based on PID control.

Motor rotation period signal

Motor control pulse output

Data latch value

OUT bit value


8-5



YES

NO

YES

NO

YES

NO

End

Enable interrupts

Start processing

Motor control on?

SW input received?

SW_INSW input

processing

Initial settings

Main routine

Timebase timer

Disable interrupts

PID control calculationBuffer H width counter value

10 ms passed?

L width counter value buffer ← L width counter value

(H width counter value buffer ← H width counter value)




NO

YES

End

Calculate control deviation (time period)IClear first edge

detected flag

First edge detected?

(Interrupt processing)Input capture

(Interrupt processing)Output compare

Store 16-bit timer counter value to time period calculation buffer


End

Set compare register value (H width)

L width counter value control area ← L width counter value buffer

H width counter value control area ← H width counter value buffer

Output PID value?

Set compare register value (L width)

Set OUT bit to "1"Set OUT bit to "0"

NO

YES


8-7


• Timebase timer (PID control calculation)

• 16-bit timer (for time control, time period calculation)

• Input capture (time period calculation)

• Output compare (motor control pulse output setting)






0AH TBTC Timebase timer control register

0CH PDR3 Port 3 data register


28H TMCR Timer control register

29H TCHR Timer count register (H)

2AH TCLR Timer count register (L)

2BH OPCR Output control register

2CH CPR0H Output compare register 0 (H)

2DH CPR0L Output compare register 0 (L)

30H ICCR Input capture control register

31H ICIC Input capture interrupt control register

32H ICR0H Input capture register 0 (H)

33H ICR0L Input capture register 0 (L)

7CH ILR1 Interrupt level setting register 1

7EH ILR3 Interrupt level setting register 3



(3) RAM allocation

(4) Flag contents



80H FLAG0 Flag area

81H SWSIG Previous SW signal

82H SWDECI Previous SW received value

83H SWCNT SW input received counter

84H PIDCNT 10 ms counter

85H HIGHCNT H width counter value storage area

87H LOWCNT L width counter value storage area

89H HCNT H width counter value buffer (result of PID control calculation)

8BH LCNT L width counter value buffer

8DH SYUKI Save area for input capture control period

8FH INDATA Time period calculation buffer

91H OUTCNT Compare register buffer


Bit Symbol Function

0 F_SWCNGSets SW input received flag when

1: SW input received

1 F_STARTSets motor control on/off flag when

1: Motor control ON

2 F_TRGSets first edge detected flag for input capture when

1: first edge detected

3 F_PIDSets PID value output flag when

1: PID value output timing

8.3 Sample Program

8-9

8.3 Sample Program


(2) Settings of timebase timer control register

0 0 0 0 0 0 0 0

7 6 5 4 3 2 1 0

P00: Set as input port

1 1 0 1 0 1 1 1

7 6 5 4 3 2 1 0

∗ ∗ ∗ ∗ ∗∗

∗ ∗∗ ∗ ∗∗P33: Set "L"

P35: Set "L"

* As these ports are unused, set to "H".

DDR0

PDR3

∗

* As these ports are unused, set as inputs.

0 0 1 0 0 0 0 0

7 6 5 4 3 2 1 0

∗ ∗∗P33: Set as input port

P35: Set as output port

DDR3

* As these ports are unused, set as inputs.

∗ ∗∗

0 0 0 0 0 0 0 0

7 6 5 4 3 2 1 0

∗ ∗∗TBC1, TBC0: Set interval time specification bits to 3.3 ms

TBR: Clear timebase timer initialization bit

TBTC


TBOF: Clear interval timer overflow bit

TBIE: Clear interval interrupt enable bit

8.3 Sample Program


(3) Settings of timer control register

(4) Settings of timer count register

(5) Settings of output control register

(6) Output compare register

0 0 0 0 0 0 1 1

7 6 5 4 3 2 1 0

∗∗TCS1, TCS0: Set count clock selection bits to 3.2 µs

TMIR: Clear timer overflow interrupt request flag

TMCR


TMIE: Clear output enable bit for timer overflow interrupt request

STCR: Clear software timer clear bit

TMST: Clear timer start/stop bit (count enable bit)

Upper byte of the 16-bit timer count registerInitial value = 00H

7 6 5 4 3 2 1 0

7 6 5 4 3 2 1 0

Lower byte of the 16-bit timer count registerInitial value = 00H

TCHR

TCLR

0 0 0 0 0 1 1 1

7 6 5 4 3 2 1 0

∗ ∗∗RTO0: Set output enable bit for output compare

OUT0: Set output data bit

OPCR


CIE0: Set interrupt request enable bit

CIR0: Clear compare match interrupt flag

∗

Upper byte of the output compare registerInitial value = 00H

7 6 5 4 3 2 1 0

7 6 5 4 3 2 1 0

Lower byte of the output compare registerInitial value = 00H

CPR0H

CPR0L

8.3 Sample Program

8-11

(7) Input capture control register

(8) Input capture interrupt control register

(9) Input capture register 0

0 1 0 0 0 0 0 0

7 6 5 4 3 2 1 0

∗∗S0: Clear edge polarity selection bit of input capture 0

ES1: Clear edge polarity selection bit of input capture 1

ICCR


SFTE: Clear software trigger enable bit

STG0: Clear software trigger set bit of input capture 0

STG1: Clear software trigger set bit of input capture 1

IS: Set input pin selection bit (P33RTI0)

0 0 1 0 0 0 0 0

7 6 5 4 3 2 1 0

∗∗CIR0: Set input capture 0, interrupt request flag

CIR1: Clear input capture 1, interrupt request flag

ICIC


OVF0: Clear input capture 0, timer overflow flag

OVF1: Clear input capture 1, timer overflow flag

CIE0: Set output enable bit for input capture 0 interrupt requests

CIE1: Clear output enable bit for input capture 1 interrupt requests

16-bit timer register value is stored by the variable triggerClear upper byteInitial value = 00H

7 6 5 4 3 2 1 0

7 6 5 4 3 2 1 016-bit timer register value is stored by the variable triggerClear lower byteInitial value = 00H

ICR0H

ICR0L

8.3 Sample Program


(10) Interrupt level setting registers 1 and 3

(11) Flag settings

1 1 1 1 0 0 1 1

7 6 5 4 3 2 1 0

∗∗L11, L10: Set input capture 0 level to 1

ILR1

1 1 1 1 1 0 1 1

7 6 5 4 3 2 1 0

∗∗L91, L90: Set output compare 0 level to 2

ILR3


∗∗∗∗

∗ ∗

LB1, LB0: Set TBTC interval timer level to 3

0 0 0 0 0 0 1 0

7 6 5 4 3 2 1 0

∗∗F_SWCNG: Clear SW input received flag

F_START: Set motor control on/off flag

FLAG0


F_TRG: Clear first edge detected flag for input capture

F_PID: Clear PID value output flag

∗ ∗

8.3 Sample Program

8-13


Fig. 8-5 Flowchart

NO

YES

YES

NO

Set stack pointer

RESET

Motor control ON?

SW input received?

SW_INSW input

processing

Set motor control on/off flag

Set interrupt levels in control registers to be used

Set control registers to be used

Initialize I/O ports

H width counter value storage area ← Initial H width counter value setting

Set motor control on/off flag

Clear motor control on/off flag

Initialize data control area

Compare register buffer ← Initial compare register setting

L width counter value storage area ← Initial L width counter value setting

Halt counter of 16-bit timer

Clear counter of 16-bit timer

Compare register settingCPROH.L. ← Compare register buffer

Disable interrupts Enable interrupts

A

A

AMAIN

8.3 Sample Program


Fig. 8-6 Flowchart

YES

NO

TBTC_INT


Increment 10 ms counter

10 ms passed?

Clear 10 ms counter

PID_CALCPID control calculation

H width counter value buffer ← H width counter value

L width counter value buffer ← L width counter value


PID control calculations (every 3.3 ms)

(Interrupt processing)

RET I

8.3 Sample Program

8-15

Fig. 8-7 Flowchart

YES

NO

INPUT_INT

Input capture

First edge detected?



Calculate control deviation (time period)

Clear first edge detected flag

Clear input capture interrupt request flag



RET I


8.3 Sample Program


Fig. 8-8 Flowchart

YES

NO

OUTPUT_INT

RET I


Clear PID value output flag

Output PID value?

Clear compare match interrupt flag



Output compare

Compare register buffer ←Compare register buffer + L width counter value storage area

Compare register buffer ←Compare register buffer + H width counter value storage area

L width counter value storage area ← L width counter value buffer

H width counter value storage area ← H width counter value buffer

Set PID value output flag

Set OUT bit to "1"Set OUT bit to "0"

Compare register value settingCPROH.L. ← Compare register buffer

8.3 Sample Program

8-17

NAME REALTIMEIO;**************************************************;* *;* Sample Realtime I/O Program *;* *;**************************************************;;**************************************;* MB89660 Resource Definitions *;**************************************RES660 DIRSEG ABS;

ORG 0000HPDR0 RB 1 ; Port 0 data registerDDR0 RB 1 ; Port 0 I/O direction register;

ORG 000AHTBTC RB 0 ; Timebase timer control registerTBC0 RBIT 1 ; Interval time specification bitTBC1 RBIT 1 ; Interval time specification bitTBR RBIT 1 ; Timebase timer clear bitTBOF RBIT 1 ; Interval timer overflow bitTBIE RBIT 1 ; Interval interrupt enable bit


;ORG 000CH

PDR3 RB 1 ; Port 3 data registerDDR3 RB 1 ; Port 3 I/O direction register;

ORG 0028HTMCR RB 0 ; 16-bit timer control registerTCS0 RBIT 1 ; Count clock selection bitTCS1 RBIT 1 ; Count clock selection bitTMIR RBIT 1 ; Timer overflow interrupt request flagTMIE RBIT 1 ; Output enable bit for timer overflow interrupt

requestRBIT1; Dummy bit

RBIT 1 ; Dummy bitSTCR RBIT 1 ; Software timer clear bitTMST RBIT 1 ; Timer start/stop bit (count enable bit);TCHR RB 1 ; Timer count register (H)TCLR RB 1 ; Timer count register (L);OPCR RB 0 ; Output control registerRTO0 RBIT 1 ; Output compare output enable bitOUT0 RBIT 1 ; Output data bitCIE0 RBIT 1 ; Interrupt request enable bitCIR0 RBIT 1 ; Compare match interrupt flag bit

8.3 Sample Program


RTO1 RBIT 1 ; Output compare output enable bitOUT1 RBIT 1 ; Output data bitCIE1 RBIT 1 ; Interrupt request enable bitCIR1 RBIT 1 ; Compare match interrupt flag bit;CPR0H RB 1 ; Output compare register 0 (H)CPR0L RB 1 ; Output compare register 0 (L)CPR1H RB 1 ; Output compare register 1 (H)CPR1L RB 1 ; Output compare register 1 (L);ICCR RB 0 ; Input capture control registerES0 RBIT 1 ; Edge polarity selection bitES1 RBIT 1 ; Edge polarity selection bitSFTE RBIT 1 ; Software trigger enable bit

RBIT 1 ; Dummy bitSTG0 RBIT 1 ; Software trigger set bitSTG1 RBIT 1 ; Software trigger set bitIS RBIT 1 ; Input pin selection bit

RBIT 1 ; Dummy bit;ICIC RB 0 ; Input capture interrupt control registerCIR00 RBIT 1 ; Interrupt request flagCIR01 RBIT 1 ; Interrupt request flag

RBIT 1 ; Dummy bitOVF0 RBIT 1 ; Timer overflow flagOVF1 RBIT 1 ; Timer overflow flagCIE00 RBIT 1 ; Interrupt request output enable bitCIE01 RBIT 1 ; Interrupt request output enable bit

RBIT 1 ; Dummy bit;ICR0H RB 1 ; Input capture register 0 (H)ICR0L RB 1 ; Input capture register 0 (L)ICR1H RB 1 ; Input capture register 1 (H)ICR1L RB 1 ; Input capture register 1 (L);

ORG 007CHILR1 RB 0 ; Interrupt level setting register 1L00 RBIT 1 ; IRQ0: External interrupt 1 #0 (FFFAh)L01 RBIT 1 ; IRQ0: External interrupt 1 #0 (FFFAh)L10 RBIT 1 ; IRQ1: External interrupt 1 #1 (FFF8h)L11 RBIT 1 ; IRQ1: External interrupt 1 #1 (FFF8h)L20 RBIT 1 ; IRQ2: External interrupt 2 (FFF6h)L21 RBIT 1 ; IRQ2: External interrupt 2 (FFF6h)L30 RBIT 1 ; IRQ3: 8-bit PWM timer 1 (FFF4h)L31 RBIT 1 ; IRQ3: 8-bit PWM timer 1 (FFF4h);ILR2 RB 0 ; Interrupt level setting register 2L40 RBIT 1 ; IRQ4: 8-bit PWM timer 2 (FFF2h)L41 RBIT 1 ; IRQ4: 8-bit PWM timer 2 (FFF2h)L50 RBIT 1 ; IRQ5: Pulse width count timer (FFF0h)L51 RBIT 1 ; IRQ5: Pulse width count timer (FFF0h)

8.3 Sample Program

8-19

L60 RBIT 1 ; IRQ6: 16-bit timer counter (FFEEh)L61 RBIT 1 ; IRQ6: 16-bit timer counter (FFEEh)L70 RBIT 1 ; IRQ7: 8-bit serial I/O #1 (FFECh)L71 RBIT 1 ; IRQ7: 8-bit serial I/O #1 (FFECh);ILR3 RB 0 ; Interrupt level setting register 3L80 RBIT 1 ; IRQ8: 8-bit serial I/O #2 (FFEAh)L81 RBIT 1 ; IRQ8: 8-bit serial I/O #2 (FFEAh)L90 RBIT 1 ; IRQ9: A/D converter (FFE8h)L91 RBIT 1 ; IRQ9: A/D converter (FFE8h)LA0 RBIT 1 ; IRQA: Interval timer (FFE6h)LA1 RBIT 1 ; IRQA: Interval timer (FFE6h)LB0 RBIT 1 ; IRQB: Time clock (FFE4h)LB1 RBIT 1 ; IRQB: Time clock (FFE4h);

ORG 007FhITR RB 1 ; Interrupt test register (write-prohibited);RES660 ENDS;;*******************************;* RAM Definitions *;*******************************

SSEG ; Stack definitionPUBLIC STACK_TOPRW 26

STACK_TOP RW 0ENDS

;RAM DIRSEG ABS

ORG 80HFLAG0 RB 0 ; Flag areaF_SWCNG RBIT 1 ; SW input received flagF_START RBIT 1 ; Motor control on/off flagF_TRG RBIT 1 ; First edge detected flag for input captureF_PID RBIT 1 ; PID value output flag;SWSIG RB 1 ; Previous SW signalSWDEC1 RB 1 ; Previous SW received valueSWCNT RB 1 ; SW input received counterPIDCNT RB 1 ; 10 ms counter;HIGHCNT RW 1 ; Storage area for H width counter valueLOWCNT RW 1 ; Storage area for L width counter valueHCNT RW 1 ; H width counter value buffer PID control

calculation resultLCNT RW 1 ; L width counter value bufferSYUKI RW 1 ; Storage area for input capture control periodINDATA RW 1 ; Time period calculation bufferOUTCNT RW 1 ; Compare register buffer;

8.3 Sample Program


RAM ENDS;REAL_IO CSEG

PUBLIC RESETEXTRN PID_CALC

;;*******************************;* Initial Settings *;*******************************RESET:

MOVW SP,#STACK_TOP ; Set stack pointer;

MOVW A,#0030HMOVW PS,A

;MOV DDR0,#00000000B ; Set I/O portsMOV PDR3,#11010111BMOV DDR3,#00100000B

;MOV TBTC,#00000000B ; Set timebase timer control registerMOV TMCR,#00000011B ; Set 16-bit timer control registerMOVW A,#0000HMOVW TCHR,A ; Clear 16-bit timer count registerMOV ICCR,#01000000B ; Set input capture control registerMOV ICIC,#00100000B ; Input capture interrupt control registerMOVW ICR0H,A ; Clear input capture register 0MOV OPCR,#00000111B ; Set output control registerMOVW CPR0H,A ; Clear output compare register 0

;; Set interrupt levels

MOV ILR1,#11110011B ; Input capture 0 level = 1MOV ILR3,#11111011B ; TBC interval timer level = 3

; Output compare 0 level = 2;

MOVW A,#0000H ; Clear RAM usedMOVW IX,#0080HMOVW EP,#0009H

RAM_CLR:MOVW @IX,AINCW IXDECW EPBNZ RAM_CLR

;SETB F_START ; Initialize motor control ON flag

;;*******************************;* Main Routine *;*******************************MAIN:

CALL SW_IN ; SW input processing;

8.3 Sample Program

8-21

BBC F_SWCNG,MAIN ; SW input received? NoCLRB F_SWCNG ; Clear SW input received flag

;BBC F_START,MT_OFF ; Motor control ON? No

;MT_ON: ; Initialize motor control area

MOV A,#00HCLRB F_PID ; Clear PID output flagMOV PIDCNT,A ; Clear 10 ms count

;CLRB F_START ; Clear motor control on/off flagSETB F_TRG ; Set first edge detected flag for input capture

;MOVW A,#2048MOVW HIGHCNT,A ; Initialize storage area for H width counter valueMOVW LOWCNT,A ; Initialize storage area for L width counter valueMOVW OUTCNT,A ; Initialize compare register bufferCLRB OUT0 ; Set OUT bit to "0"

;MOVW A,#2048 ; Set compare register valueMOVW CPR0H,ACLRB STCR ; Clear 16-bit timer counterSETB PDR3:5 ; Set OUT bit output to "H"SETB TMST ; Start timer

;SETI ; Enable interruptsJMP MAIN

;MT_OFF:

SETB F_START ; Set motor control on/off flag;

CLRB PDR3:5 ; Set OUT bit output to "L"CLRB TMST ; Stop timerCLRI ; Disable interruptsJMP MAIN

;;******************************************************;* TBTC_INT *;* PID control calculation processing (Interrupt) *;******************************************************TBTC_INT:

PUSHAT ; Save A, T, IX registersPUSHW IX

;CLRCMOV A,PIDCNT ; Increment 10 ms counterADDC A,#01HMOV PIDCNT,A

;CMP A,#03H ; 10 ms passed?BC TBTC_EXT ; No! THEN TBTC_EXT

8.3 Sample Program


;MOV PIDCNT,#00H ; Clear 10 ms counter

;CALL PID_CALC ; PID control calculation (calculate "H" width

counter value);

CLRC ; Calculate "L" width counter valueMOVW A,#1000HMOVW A,HCNTSUBCW AMOVW LCNT,A

;TBTC_EXT:

POPW IX ; Restore A, T, IX registersPOPAT

;RETI

;;*******************************************;* INPUT_INT *;* Input capture processing (Interrupt) *;*******************************************INPUT_INT:

PUSHAT ; Save A, T registers;

CLRB CIR00 ; Clear input capture 0 interrupt request flagBBC F_TRG,INPUT_010 ; First edge detected? No! THEN INPUT_010

;CLRB F_TRG ; Clear first edge detected flag for input captureMOVW A,ICR0H ; Store 16-bit timer count in time period calculation

bufferMOVW INDATA,A

;JMP INPUT_EXT

;INPUT_010:

MOVW A,ICR0H ; Calculate control deviation (time period)MOVW A,INDATACLRCSUBCW AMOVW SYUKI,A ; Store calculation result in storage area for input

capture control periodXCHW A,T ; Store 16-bit timer value in period calculation

bufferMOVW INDATA,A

;INPUT_EXT:

POPAT ; Restore A, T registers;

RETI;

8.3 Sample Program

8-23

;********************************************;* OUTPUT_INT *;* Output compare processing (Interrupt) *;********************************************OUTPUT_INT:

PUSHAT ; Save A, T registers;

CLRB CIR0 ; Clear compare match interrupt flagBBC F_PID,OUTPUT_010 ; Output PID value? No! THEN OUTPUT_010

;CLRB F_PID ; Clear "PID value output" flagMOVW A,HCNTMOVW HIGHCNT,A ; Storage area for H width counter value ← "H"

width counter value bufferMOVW A,LCNTMOVW LOWCNT,A ; Storage area for L width counter value ← "L"

width counter value buffer;

MOVW A,HIGHCNT ; Compare register buffer += Storage area for H width counter value

MOVW A,OUTCNTCLRCADDCW AMOVW OUTCNT,ACLRB OUT0 ; Set OUT bit to "0"JMP OUTPUT_EXT

;OUTPUT_010:

SETB F_PID ; Set PID value output" flagMOVW A,LOWCNT ; Compare register buffer += Storage area for L

width counter valueMOVW A,OUTCNTCLRCADDCW AMOVW OUTCNT,ASETB OUT0 ; Set OUT bit to "1"

;OUTPUT_EXT:

MOVW A,OUTCNT ; Set compare register valueMOVW CPR0H,A

;POPAT ; Restore A, T registers

;RETI

;;*******************************;* SW processing *;*******************************SW_IN:

MOV A,PDR0 ; Equal to previous port value?AND A,#01H

8.3 Sample Program


CMP A,SWSIGBNZ SW_IN_010 ; No THEN SW_IN_010

;MOV A,SWCNT ; Increment counterCLRCADDC A,#01HMOV SWCNT,ACMP A,#03H ; Counter value matched for three times?BNZ SW_IN_EXT ; No THEN SW_IN_EXT

;MOV SWCNT,#00H ; Clear counterMOV A,SWDECIMOV A,SWSIGCMP A ; Same as previous received value?BZ SW_IN_EXT ; Yes THEN SW_IN_EXT

;MOV SWDECI,A ; Previous received value ← Current received valueCMP A,#00H ; Received on falling edge?BNZ SW_IN_EXT ; No THEN SW_IN_EXT

;SETB F_SWCNG ; Set SW input received flagJMP SW_IN_EXT

;SW_IN_010:

MOV SWSIG,A ; Previous port value ← Current port valueMOV SWCNT,#00H ; Clear counter

;SW_IN_EXT:

RET;REAL_IO ENDS;;*******************************;* Vector Addresses *;*******************************VECTOR CSEG ABS;

ORG 0FFE4HDW TBTC_INT ; IRQB (TBT interval timer)ORG 0FFE8HDW OUTPUT_INT ; IRQ9 (output compare 0)ORG 0FFF8HDW INPUT_INT ; IRQ1 (input capture 0)ORG 0FFFDHDB 0H ; Reset modeDW RESET ; Reset vector

;VECTOR ENDS

END

9.1 Example D/A Application Circuits

9-3

Chapter 9:Example D/A and VFD Application Circuits


Microcontrollers, including the F2MC-8L Series, may sometimes require analog signals to control externaldevices. However, as microcontrollers cannot output analog signals directly, it is sometimes necessary touse an external circuit to convert a digital signal output to an analog signal. The conversion to an analogsignal is performed by a D/A converter.

The following two methods are available to convert a digital value to an analog value.

(1) PWM method

(2) Resistor method

9.1.1 PWM MethodThe digital value is resolved based on the number to bits (8-bit resolution: 1/256), which determine thebasic unit. A "1" is output for the proportion to the output cycle that corresponds to the digital value.

The analog value corresponding to the digital value is obtained by integrating the PWM output (D/Aconversion).

(1) Relationship between the digital value and pulse width

The following figure shows the relationship between the digital value and pulse width for 8-bit resolution.

The PWM output from the digital signal can easily be converted to a voltage using an externally connectedintegrating circuit (resistor and capacitor). Figure 9-1 shows an example application circuit.

50%

Digital value01000000

1 output cycle

Digital value10000000

1 output cycle


9-4 Chapter 9: Example D/A and VFD Application Circuits

Fig. 9-1 PWM D/A Converter Circuit

(2) Conversion from a pulse width to a voltage

Figure 9-2 shows the waveforms for the PWM output voltage VD and the integrating circuit output voltageVA.

Although the PWM method provides high resolution with only a small number of external components, itsdisadvantages are a slow response and a ripple that accordingly appears on the analog voltage.

The following describes an example in which tLSB is 100 ¸µs, R is 255 KΩ, C is 1.0 µF, the high leveloutput from the port is 5.0 V, and the low level is 0 V. The example calculates the ripple on VA that occurswhen the data value (D) is 127.

Fig. 9-2 VD and VA Waveforms

VCC

RST

X0 X1

VCC

VCC

VSS

Crystal oscillator

Capacitor

Analog outputResistor

Integrating circuit

PWM output

tH tL

0V

VA

VD 5V

255 • tLSB

tH = D • tLSB

tL = (255 - D) • tLSB

Ripple

0V


9-5

Fig. 9-3 VRIP, VF, and VR

From the above diagram,VF - VRIP + VR = 5 ............................................... (1)

If RR is the proportional voltage increase relative to VR,VRIP = VR . RR ...................................................... (2)

and RF is the proportional voltage decrease relative to VF

VRIP = VF . RF ...................................................... (3)

Substituting (2) and (3) in (1) gives:VRIP/RF - VRIP + VRIP/RR = 5

Rearranging for VRIP gives:VRIP = 5 x RR . RF/(RF - RR . RF + RF)

Here, RR and RF can be obtained from the standard equationVRIP = VD . (1 - e-t/RC)

(VD : VF, VR)

as follows:RR = 1 - e-12.7/255 = 0.048584RF = 1 - e-12.8/255 = 0.048957

This gives:VRIP = 0.12497

5V

0V

VF VRIP

VR



9.1.2 Resistance MethodThere are two types of resistance method: weighted resistances and resistor ladder. The resistor laddermethod is most commonly used with microcontrollers.

The resistor ladder method is so named because resistors are arranged in a ladder.The ladder can be constructed with a resistance ratio of 1:2 to enable high resolution (number of bits) andhigh accuracy D/A conversion.

The software modem in Chapter 4 performs D/A conversion of a resource output using an external circuit.The following shows an example application circuit for a software-driven frequency modulation output.The MSK modulated output is output via the D/A converter (8-bit, R-2R).

Fig. 9-4 Resistor D/A Converter Circuit

VCC

RST

X0

Oscillator pins

X1

VCC

VSS

Output

P10

P11

P12

P13

P14

P15

P16

P17

150kΩ

75kΩ150kΩ

150kΩ

150kΩ

150kΩ

150kΩ

150kΩ

150kΩ

150kΩ

75kΩ

75kΩ

75kΩ

75kΩ

75kΩ

75kΩ

9.2 Example VFD Application Circuit

9-7


Some F2MC-8L Series products have internal high withstand voltage ports. Vacuum fluorescent displaytubes (VFD) are widely used in non-portable AV equipment and other household appliances. As driving aVFD requires a high voltage (up to 30 V), the high withstand voltage ports are used for this purpose.

9.2.1 Example VFD Application Circuit



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G2

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AC

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AC

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P20

P21

P22

P23

P24

P25

P26

P27

P10

P11

P12

P13

P14

P15

P16

P17

MB

899

10

Documents

F2MC-8L FAMILY 8-BITMICROCONTROLLER APPLICATIONNOTE · The sample program uses the above resource to produce an inverter output for a 3-phase induction motor using a magnetic flux